JPS61208310A - Delay time setting pulse generator - Google Patents

Abstract

PURPOSE:To control the delay quantity and pulse width with high accuracy by using a circuit element operated slowly at a low frequency in generating a pulse having a prescribed delay amount at high speed. CONSTITUTION:In order to obtain a desired time with a digital counter, the resolution of time is decided by the minimum unit of the counter. That is, when a desired time is controlled with accuracy of 10ns, the counter requires a high speed of 100MHz. In this case, the phase of the clock in use is controlled as the counter clock, then it is possible to suppress the maximum operating frequency of the counter lower. Then a count means measuring the clock pulse, a phase control means controlling the phase of the clock pulse, a minute time control means controlling the finner time than the minimum unit of the count means and a pulse generating means generating a pulse having a delay time in response to the output of the counter means and the minute time control means are provided.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field] The present invention relates to a pulse generator for setting a delay time, and particularly to an electronic scanning type ultrasonic diagnostic apparatus.

The present invention relates to a technique that is effective when applied to a control means for controlling the vibration time of a large number of ultrasonic vibrating elements when converging or deflecting an ultrasonic beam.

[Background technology]

Electronic scanning ultrasonic diagnostic equipment uses a large number of ultrasonic vibrating elements (hereinafter simply referred to as elements) to converge and deflect the ultrasonic beam by controlling the time of pulses applied to these elements. You can also do so. In order to do this, it is necessary to precisely control the time at which the transmission pulse is applied to each of the elements. As a means for finely controlling the transmission pulse application time, a delay time setting pulse generator is used which is provided with a large number of delay circuits and generates pulses having a delay time corresponding to each element at high speed.

However, such a delay time setting pulse generator using a large number of delay circuits has a problem in that the circuit configuration becomes complicated.

[Purpose of the invention]

An object of the present invention is to use circuit elements that operate at low frequency and at low speed when generating pulses with a predetermined delay time at high speed in a pulse generator for setting a delay time. Our goal is to provide technology that allows for high-precision control.

Another object of the present invention is to provide a delay time setting pulse suitable for controlling the vibration time of a large number of elements when converging or deflecting an ultrasound beam in an electronic scanning type ultrasound diagnostic device. The purpose is to provide generation technology.

The above and other objects and novel features of the present invention will become apparent from the description of this specification and the accompanying drawings.

[Summary of the invention]

A brief overview of typical inventions disclosed in this application is as follows.

That is, a counting means for measuring clock pulses, a phase control means for controlling the phase of the clock pulse, a minute time control means for controlling a time narrower than the minimum unit of the counting means, and the counting means and minute time control. By providing a pulse generating means that generates a pulse with a delay time corresponding to the output of the means, when generating a pulse with a predetermined delay amount at high speed, it is possible to use circuit elements that operate at low frequency and at low speed. This is a delay time setting pulse generation device '4 which allows the delay amount and pulse width to be controlled with high precision.

[Structure of the invention]

The configuration of the present invention will be explained below along with examples.

In addition, in all the figures for explaining an example.

Components having the same function are given the same reference numerals, and repeated explanations thereof will be omitted.

First, the focus of the delay time setting pulse generator of the present invention will be explained.

When obtaining a desired time using a digital counter, the resolution of this time is determined by the minimum unit of the counter. That is, when controlling a certain desired time with an accuracy of ]OnS, the counter needs to operate at a high speed of 100 MHz. At this time, if the phase of the clock used is controlled and used as the counter clock, the maximum operating frequency of the counter can be kept low. The present invention focuses on this point.

[Example ■]

1 and 2 are for explaining the delay time setting pulse generator according to the embodiment (2) of the present invention, FIG. 1 is a block diagram showing its schematic configuration, and FIG. FIG. 2 is a waveform diagram showing an output waveform of the phase shifter shown in FIG. 1;

In FIG. 1, 1 is an oscillator, and the oscillation frequency of this oscillator 1 is f (period t=1/f). This oscillator 1
The outputs of are connected to phase shifters 2A, 2B, and 2C. The phase shifters 2A, 2B, and 2C are each capable of changing the phase of the input by 90 degrees as shown in FIG. 3A, 3
B and 3C are delay time data setters for generating a desired amount of delay.
Memory), etc. is used. 4A, 4B, 4
C is a counter.

For example, transistor-transistor logic (TTL)
), complementary insulated gate field effect transistor (CM
O5), using a field effect transistor (FET). 5
is a control circuit for controlling each of the above-mentioned parts. #0 is the reference time, #1 to #3 are nine counters 4A, 4B, 4 respectively.
This is the output pollo of C.

In FIG. 2, φO is the oscillation pulse of oscillator 1.

φ1 is the output pulse of the phase shifter 2A, φ2 is the output pulse of the phase shifter 2B, φ3 is the output pulse of the phase shifter 2C, and I is the period of the oscillation pulse φ0 of the oscillator 1.

Next, the operation of the delay time setting pulse generator according to the first embodiment will be described.

Here, for ease of explanation, a specific numerical example will be used.

In FIGS. 1 and 2, the reference time is set as #0, and #1 to #3 are set to 120 nS and 35 nS, respectively.
It is assumed that the ultrasonic delay times of 0 nS and 1220 nS are controlled in units of 1 OnS. The phase shifters 2A and 28.2C are
Since phase control of 174 wavelengths is possible for each, 1
For a time of 0n S X 4 =40nS, that is, for the counters 4A, 4B, and 4C, the minimum count number is 40nS, and a time of 10, 20, and 30nS is phased by the phase shifters 2A, 2B, and 2C.

As a result, for the desired delay amount TnS, the counter 4A
, 4B, 4C and φn of the phase shifter can be obtained from the following relational expression.

N=　[T/40F However, [] means rounding down to the decimal point.

n = (T-N
, which indicates which phase.

In the above example, for #1, N=3 with the clock of φ0
．． #2 is the clock of φ3 and N=8, and #3 is the clock of φ2 and N=30. Therefore, these values are preset in the counters 4A, 4B, and 4C, and the phase shifter 2A
, 2B, and 2C. Here, the oscillator l is 4
Oscillate at an oscillation frequency of 0 nS, that is, 25 MHz,
If it is the subtraction pulse of counters 4A, 4B, and 4C, #0
With respect to the reference clock of #1.12. #3 is 12 each
Borrows occur in the counters 4A, 4B, and 4C after delays of 0 nS, 350 n S, and 1220 n S. This borrow timing is input to a next-stage pulse generator (not shown) to generate a pulse with a predetermined delay time. When all the desired pulses are obtained, the oscillator 1 is stopped and preparations are made for the next step.

The borrow timing can be used, for example, to set the excitation time of the element of the electronic scanning type ultrasonic diagnostic apparatus described above.

As can be seen from the above description, according to the present embodiment I, the following effects can be obtained.

(1) By providing phase shifters 2A, 2B, 2C and delay time data setters 3A, 3B, 3C, counter 4A,
It is possible to measure time with finer accuracy than the operating frequency of 4B and 4C.

(2) According to (1) above, conventionally, a circuit element that operates at 100 MHz was required to measure in Lens units, but since it can operate at 25 MHz, it is possible to use a circuit element that operates at a low frequency and low speed such as a general-purpose TTL element. It can be composed of circuit elements.

(3) According to (2) above, it is possible to obtain performance equivalent to a circuit element operating at high speed in a circuit using a circuit element operating at low frequency and at low speed, such as TTL.

(4) According to (3) above, the circuit configuration of the delay time setting pulse generator can be simplified.

(5) According to (1) above, the measurement capacity can also be reduced to 1/4, resulting in cost reduction.

[Embodiment 2] FIG. 3 is a block diagram showing a schematic configuration of a delay time setting pulse generator according to Embodiment 2 of the present invention.

The delay time setting pulse generator of this embodiment (2) is as follows.

The three phase shifters 2A, 2B, and 2C shown in FIG. 1 are shared by one phase shifter 2', and phase selection switches 6A, 6B, and 6Cti are provided at the next stage of this phase shifter 2'. Furthermore, pulse generators 7A, 7B, and 7C for generating pulses with desired pulse widths are provided at the next stage of the counters 4A, 4B, and 4C.

The pulse generation bags gf7A, 7B, and 7C are constructed of, for example, flip-flops, and the flip-flops are set by borrows from the counters 4A, 4B, and 4C, and reset after a desired time has elapsed.

With this configuration, it is possible to reduce the number of phase shifters 2A, 2B, and 2C with the complicated configuration of the embodiment I, thereby simplifying the overall circuit configuration of the delay time setting pulse generator. I can do it. This also reduces costs. In addition, it was difficult to adjust the phase of each of the phase shifters 2A, 2B, and 2C, but according to the present embodiment (2), only the phase shifter 2' needs to be adjusted, so the adjustment time can be shortened. be able to.

Although the present invention has been specifically explained above based on the embodiments, it goes without saying that the present invention is not limited to the embodiments described above, and can be modified in various ways without departing from the gist thereof.

For example, in the embodiment described above, a four-phase clock having a phase difference of 174 -periods has been described, but the number of phases can be further set to any number of multiple phases.

Of course, the above-mentioned effects can be further obtained. However, it should be noted that as the number of phases increases, restrictions on variations in the operation delay time of the elements used become stricter.

Further, the delay time data setting may be performed using means other than the memory (ROM) storing the delay time data, such as a register, a group of switches, etc.

〔effect〕

As explained above, according to the present invention, the following effects can be obtained.

(1) By providing a phase shifter and a delay time data setter, it is possible to measure time with a finer precision than the operating frequency of the counter.

(2) According to (1) above, a high-speed operation element is required to perform measurements in units of 10 nS, but it is possible to obtain performance equivalent to high-speed operation using a low-speed operation element such as a general-purpose TTL element. Therefore, one circuit can be simplified.

(3) According to (1) above, the measurement capacity can also be reduced to 1/4.

(4) According to (2) and (3) above, the cost of the device can be reduced.

[Brief explanation of drawings]

FIGS. 1 and 2 are diagrams for explaining a delay time setting pulse generator according to Embodiment 2 of the present invention. FIG. 1 is a block diagram showing its schematic configuration. FIG. 2 is a waveform diagram showing the waveform of the output pulse of the phase shifter in FIG. 1. FIG. 3 is a block diagram showing a schematic configuration of a delay time setting pulse generator according to Example H of the present invention. In the figure, ■... Oscillator, 2A, 2B, 2C, 2'...
Phase shifter, 3A, 3B, 3C... Delay time data setter, 4A, 4B, 4C... Counter, 5... Control circuit. 6A, 6B, 6C... Phase selection switch, 7A, 78°70... Pulse generator.

Claims (1)

[Claims] a counting means for measuring clock pulses, a phase control means for controlling the phase of the clock pulse, and a minute time control means for controlling time finer than the minimum unit of the counting means;
A pulse generation device for setting a delay time, comprising a pulse generation means for generating a pulse having a delay time corresponding to the output of the counting means and the minute time control means.