KR100287427B1 - Apparatus for generating pulse train - Google Patents

Abstract

PURPOSE: An apparatus for generating pulse train is provided to use a clock which is lower than a radio reference clock by utilizing an adder for compensating for an effective place. CONSTITUTION: A pulse period register(30) is used for storing a period of pulse. A pulse increase register(31) is used for storing an increase of the pulse according to a sampling time. The first, the second, and the fourth latches(34,35,36) are used for latching the stored values through data buses(32,33) by the same signal output(47) of a comparator(49). The first latch(34) is used for storing an integer value corresponding to the pulse period. The second latch(35) is used for storing a fractional value of the pulse period. An adder(39) and an adder output(43) are added by a D-flipflop(44) whenever a carry signal(50) of a timer(48) is outputted. An overflow value(42) is added to the integer value of the first latch(34). The added value is latched by a signal of the third latch(36).

Description

Pulse train generator

The present invention relates to the generation of pulse train for enabling the frequency and position command of the servo driver or stepping driver to be the desired motion operation of the pulse which is the speed command signal. The present invention relates to a pulse train generator which is designed as an integrated circuit (ASIC or FPGA) and mounted on a motion controller.

In general, in FIG. 1, the pulse train generator 3 forms a system configuration in combination with the CPU 2 and is mounted on the upper motion controller 1 of the servo driver or the stepping driver 6 and used. According to the sequence programmed by the CPU 2 of the upper motion controller 1, the lower gear 5 is commanded to the lower driving device 5 in the form of a pulse 4 to control the right or speed control of the motor 6 to control the desired angle and position. . The internal logic of the conventional pulse train generator calculates the acceleration, deceleration, frequency, and target pulse amounts to be outputted in FIG. 2 at a predetermined time point and stores them in the registers 10, 11, 12, and 13, respectively. These values are decremented by '1' by the reference clock of the timer 14 so that a pulse is generated when the timer value becomes '0', and the pulse is counted by the counter 16 and then the target pulse amount register 13 Value is compared with the comparator 17 and the timer outputs a pulse until the two values are the same. The pulse output 15 of the timer outputs the pulses P + 19 and P- 20 of the desired waveform in the pulse train form setting 18.

The conventional pulse train generator maintains the accuracy of the pulse cycle and the pulse output to the maximum by using several hundred megahertz (MHz) as a reference clock. Therefore, the characteristics of the integrated circuit used must be good and accordingly the cost increase. In addition, when the frequency of the pulse train is to be changed at an arbitrary time, the time delay reflected by the pulse output and the position and velocity pattern already calculated when implementing various online motion operations in conjunction with a peripheral device (robot or PLC) Since 3 degrees) is stored in each register, there are many restrictions in changing the position and velocity patterns at any point in time.

The motor driving pattern (24: acceleration, 25: constant speed, 26: deceleration, 27: jog speed) corresponding to the time-to-speed shape of FIG. 3 is illustrated. The pulse train 28 outputted according to each section is acceleration / deceleration and constant speed. The pulse period corresponding to the figure and the number of pulses corresponding to the target position should be generated accurately. In general, the upper controller 1 calculates an arbitrary speed and position pattern for each sampling time, and the value corresponds to a speed or position increment corresponding to one sampling interval. As described above, in the control method for immediately reflecting the information calculated by the CPU, many constraints are applied to the conventional pulse generator.

The present invention calculates the incremental amount and pulse interval of the pulse from the position information calculated at a constant sampling time in the register and stores the pulse train generation method in the register to secure the effective position of the adder (Adder) In addition, it is possible to use a clock lower than the conventional high frequency reference clock to avoid the cost increase by using a high-speed integrated circuit chip with good characteristics. In addition, the target value calculated in each sampling section is reflected in the pulse generation logic in the next sampling section to overcome the difficulties of various conventional motion implementations.

1 is a use example of the pulse train generator

2 is a block diagram of a pulse train generator used in a commercial motion controller.

3 is a waveform diagram of a pulse train

4 is a pulse train generator of the present invention

5 is a relation diagram of time and number of pulses of a pulse train processed in units of sampling time

* Explanation of symbols for main parts of the drawings

. Registers 10, 11, 12, 13, 30, and 31: Data storage places that can be read or written by the CPU 2 of FIG.

. Timer 14, 48: A device that generates a carry when it reaches '0' by decreasing '1' from the initial value loaded by the retractable timer operating as an input reference clock.

. Comparator (17, 49): A device that generates a signal when the values of two input data are the same.

. Pulse train form setting (18, 52): Device to adjust the form of pulse train according to the set mode.

. P +, P-: Pulse output signal output in the form of 'pulse signal and direction signal' or forward and reverse pulse 'or' two-phase square wave (aka encoder signal) 'according to the pulse type selection.

. S1: The carry signal pulse string output of the retractable timer 48 of FIG.

. S2: Output signal generated when two inputs of the comparator 49 of FIG. 4 are identical.

The pulse generation logic and CPU operation of FIG. 4 of the present invention are used to obtain a desired control value (pulse increment and pulse interval) of FIG. 5 to control the pulse train.

In Fig. 5, the position increment amounts P0 (62) to P4 calculated at each sampling time Ts (60) are digital values corresponding to the speed pattern 61, and the pulse periods T0 (64) to T4 corresponding to the speed and pulses. When converted into numbers and stored in the register of Fig. 4, the pulse generating logic generates the desired pulse.

In FIG. 4, a pulse interval register 30 for storing pulse intervals (T0 to T4 in FIG. 5) calculated by the CPU and a pulse increment register 31 for storing pulse increments (P0 to P4 in FIG. 5). Each value is stored as a new value at each sampling time, and each value is latched 1 (34) and latched 2 (35) by the same signal output S1 (47) of the comparator 49 through the data buses 32 and 33. And latch 4 (36). Here, the latch 1 stores an integer value corresponding to a pulse period including a significant digit below the decimal point, and the latch 2 stores a value below the decimal point of the pulse period. The value below the decimal point is added to the adder 39 and the adder output 43 by the flip-flop DFF 44 whenever the carry signal S2 50 of the loadable timer 48 is output, and the overflow value of the adder ( 42 is added to the adder 41 by the integer value of the latch 1 and the value is latched by the S2 signal to the latch 3 46. This logic is a software that is compensated by hardware logic within the sampling interval with effective digit compensation method to guarantee the accuracy of the maximum frequency that can be guaranteed with a reference clock of several tens of megahertz (MHz) to a certain degree (resolution). Fine adjustments cannot be made.

The pulse S2 generated as described above is counted by the counter 51 and transferred to the comparator 49 to be compared with the latch 4 36 which is the pulse increment, and when the same value is reached, the signal S1 47 is generated and the signal is latched 1. To load new values into latch 2 and latch 4. Therefore, the number of pulses output to each sampling is consistent with the target value, and the desired pulse shape can be output in various shapes by the pulse shape setting 52 in accordance with the input specifications of the lower servo driver or the stepping driver.

The pulse train generation method according to the present invention transmits the target position and velocity information at a constant sampling time, so that the target value can be changed at any point and smooth motion control is possible when implementing system configuration start control and synchronous operation. Can generate output. It also has the advantage of achieving the highest frequency (approximately tens of megahertz) even with a reference clock of tens of megahertz (MHz), which can be easily realized with commercially available programmable logic (eg FPGA or EPLD).

Claims (1)

In order to generate the desired frequency and number of pulse trains, pulse intervals and pulse increments are applied at certain sampling times, and an adder which is an effective position compensation device for obtaining a desired pulse frequency is added to improve the accuracy of the frequency. Is a pulse train generator that generates a continuous pulse by loading the next target value when the target value is reached by counting the counter.