RU2205446C2 - Capacitive differential transmitter signal digitizer - Google Patents

Abstract

FIELD: metrology. SUBSTANCE: device that can be used for measuring nonelectrical quantities has transducer, switching unit, reversible counter, memory unit, and timing unit; transducer has two generators; timing unit has counters, flip-flop, and decoder. EFFECT: enhanced precision. 1 cl, 4 dwg _

Description

 The invention relates to measuring technique and can be used to measure non-electric quantities, in particular pressure measurements using a differential capacitive sensor.

 Known digital signal converter of a differential capacitive sensor [1], containing a primary converter (PP), a switching unit, a reversible counter, a synchronization unit, a counter pulse generator (GSI), a memory unit, a decoder, a display, a digital-to-analog converter (DAC), a digital comparison unit and a block of auxiliary circuits, and two PP outputs through a switching block are connected to the first and second information inputs of a reversible counter, the control input of which is connected to the first output of the synchronization block, and the output - through a series-connected memory unit and a decoder with a display input, the GSI output is connected to the third input of the switching unit, the control input of which is connected to the second output of the synchronization unit, the third output of which is connected to the control input of the memory unit, and the input to the first PP output, output the memory block is connected to the input of the auxiliary circuit block and through the DAC and digital comparison unit, respectively, with the first and second outputs of the device.

 However, the known device produces an output signal proportional to the difference in capacitance of the capacitors of the differential capacitive sensor, which determines the dependence of the output signal on the drift of the parameters of the structural elements of the capacitive sensor, averaging the result does not exclude an error caused by the instability of the frequency of the GSI, and the nonlinear nature of the dependence of the output signal on the measured value makes it difficult practical use.

 The purpose of the invention is to increase noise immunity, resolution and conversion accuracy, to obtain a linear relationship between the measured value and the output signal, which is achieved by a circuit implementation of such a function of the ratio of the frequencies of the output signals of two generators operating on the capacitors of a differential capacitive sensor, which allows averaging over a given period of time relations of frequencies and linearize the nonlinear dependence of frequencies on the value of the measured parameter.

 In FIG. 1 shows a diagram of the proposed device; figure 2 - diagram of the primary Converter; figure 3 - circuit block synchronization; figure 4 - diagram of the switching unit.

 The device comprises: a primary converter (PP) 1, a switching unit 2, a reversible counter 3, a memory unit 4 and a synchronization unit 5, the first and second outputs of the PC connected to the first and second inputs of the switching unit 2 and through the switching unit connected to the information input of the reversible counter 3, the outputs of which are connected to the memory unit 4, the first and second outputs of the PP are also connected to the first and second inputs of the synchronization unit 5, the first output of which is connected to the control input of the reading of the memory unit, the second output to the input of the settings initial state down counter 3, a third output - to the control input of the switching unit and the control input of down counter counting mode 3.

PP (figure 2) contains a generator 1.1, which includes a capacitor C ₁₁ , which determines the frequency of the generated signal by the generator 1.1, and its output is connected to the first output of the PP, and generator 1.2, which includes a capacitor C ₁₂ , which determines the frequency of the generated signal generator 1.2, and its output is connected to the second output of the PP.

 The synchronization block (Fig. 3) contains a counter 5.1, a counter 5.2 and a counter 5.3, a decoder 5.4 and a trigger 5.5, with the input of the counter 5.1 connected to the first input of the synchronization block, and the output of the counter connected to the R-input of the trigger 5.5, the non-inverted output of which is connected to the third output of the synchronization unit, and the inverse output is connected to the inputs of the control mode of the prohibition of counting and setting the initial state of the counter 5.3, the input of which is connected to the second input of the synchronization unit, and the output is connected to the input of setting the initial state of the counter Fractor 5.2, the outputs of which are bitwise connected to the inputs of the descrambler 5.4, the first output of which is connected to the first output of the synchronization block, the second output is connected to the S-input of the trigger 5.5 and the second output of the synchronization block, and the third output is connected to the input of the account inhibit counter control of the decoder 5.2.

 The switching unit (Fig. 4) contains a switching element 2.1 and a counter 2.2, the first input of the switching element being connected to the first input of the switching unit, and the second input through the counter 2.2 connected to the second input of the switching unit, the control input of the switching element being connected to the third input of the switching unit .

где K₁, K₂ - коэффициенты пропорциональности, зависящие от параметров элементов электрической схемы;
C₁₁,C₁₂ - емкости конденсаторов дифференциального емкостного датчика.The device operates as follows. When the power source is connected, the generation of pulse signals by the generator 1.1 with frequency f ₁ and generator 1.2 of the pulse signals by frequency f ₂ starts, and the frequencies depend on the nominal capacitance of the capacitors of the differential capacitive sensor as follows:

where K ₁ , K ₂ are the proportionality coefficients, depending on the parameters of the elements of the electrical circuit;
C ₁₁ , C ₁₂ - capacitance of capacitors of a differential capacitive sensor.

 The processing of pulsed signals is carried out in the process of periodically repeating work cycles.

The beginning of each working cycle is characterized by the following initial conditions:
- counter 5.1 of the synchronization unit and counter 2.2 of the switching unit are in constant pulse counting mode;
- counter 5.3 of the synchronization block is in the mode of prohibition of the account and preset;
- counter control decoder 5.2 synchronization block is in a locked state;
- switching unit 2 is in permission mode for the passage of pulses along the second input;
- trigger 5.5 of the synchronization block is in the log state. 1 on uninverted output;
- the reverse counter 3 is set to the state of the original number and to the counting mode for addition;
- the memory unit 4 is in the prohibition mode of recording information and storing information recorded in a previous work cycle.

 From the moment the work cycle begins, the pulse signal from the first output of the PCB goes to the first input of the synchronization unit and the first input of the switching unit, and from the second output of the PCB the pulse signal goes to the second input of the synchronization unit and the second input of the switching unit, therefore, the signal goes from the first output to the clock inputs of the counters 5.1 and 5.2, and from the second output through the counter 2.2 and the switching element 2.1 to the clock input of the reverse counter 3, where the addition of the current number of pulses with the original value of the number is established wth on the reverse counter 3, at the beginning of the working cycle.

 The pulse signal received at the clock input of the counter 5.1, after a predetermined division of the frequency, is fed to the R-input of trigger 5.5, setting the trigger on the non-inverted output to the log state. 0, while the switching unit at the control input is transferred to the mode of allowing the signal to pass through the first input, and the reverse counter 3 at the input of the switching of the counting mode is transferred to the mode of subtracting the number of incoming pulses. The signal from the inverted output of trigger 5.5 arriving at the input for controlling the counter prohibition mode and the input for setting the initial state of the counter 5.3 puts the counter in the frequency division mode of the pulse signal supplied to the synchronization block at the second input.

After dividing the frequency in counter 5.3, the signal from the output of the counter is fed to the input of setting the initial state of the counter for controlling the decoder 5.2 of the synchronization unit, while the counter is unlocked and, in accordance with the clock pulses, the counter 5.2 generates a bitwise binary code to the inputs of the decoder 5.4, which in turn gives control signals at the outputs, ensuring the sequential execution of the following operations:
- on the first output - parallel rewriting of the number accumulated in the reverse counter 3 numbers in the memory block 4;
- on the second output — setting the initial number and trigger 5.5 on the reverse counter to the log state. 1 on the non-inverted output, and the trigger, in turn, on the non-inverted output sets the switching unit 2 to the mode for allowing the passage of pulses at input 2, and also sets the counting mode for addition and the inverse output to set the counting and preset mode to the inverse output 3 counter 5.3;
- on the third output - self-locking of the decoder control counter 5.2.

 The duty cycle is completed, the information in the output register is updated, the initial states of the circuit elements correspond to the states of the beginning of the duty cycle.

Sources of information
1. Copyright certificate of the USSR 1613864, cl. G 01 R 27/26, 1990 - prototype.

 2. Copyright certificate of the USSR 1599809, cl. G 01 R 27/26, 1990.

 3. Copyright certificate of the USSR 1659909, cl. G 01 R 27/26, 1991.

Claims (1)

 A digital signal converter of a differential capacitive sensor comprising a series-connected primary converter, a switching unit, a reversible counter and a memory unit, as well as a synchronization unit, characterized in that the primary converter contains two generators, the generators working on the sensor capacities, the synchronization unit provides a sequence of operations cycle, the switching unit provides the input to the clock input of a reverse counter of signals from different generators at different In these modes, the counter counts and a memory block for storing information for the duration of the operating cycle, while the output of the first generator is connected to the clock inputs of two counters of the synchronization block, the output of the first of which is connected to the R-input of the trigger, and the output of the decoder control counter is bitwise connected to the inputs of the decoder , the output of the second generator is connected to the clock input of the third counter of the synchronization unit and the clock input of the counter of the switching unit, and the output of the third counter of the synchronization unit is connected to the input ki of the initial state of the decoder control counter, the non-invertible output of the trigger is connected to the control input of the switching unit and the input of switching modes of counting of the reverse counter, and the inverse output is connected to the inputs of the control mode of the counter prohibition and setting the initial state of the third counter of the synchronization block, the output of the switching unit is connected to the clock input a reverse counter, the information outputs of which are connected to the information inputs of the memory block, the first output of the decoder is connected to the input -parallel entry storage unit, a second output connected to the input for setting the initial number up-down counter and the S-input of the flip-flop and a third output coupled to an input of the decoder accounts prohibition control counter.

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