JP2800326B2 - Frequency transducer - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION <Industrial application field> The present invention relates to a frequency transducer for measuring a frequency within a predetermined measurement range and converting the frequency into an analog signal corresponding to the frequency, and in particular, stably increasing the measurement range. A frequency transducer modified to expand.

<Prior Art> FIG. 5 is a block diagram showing a configuration of a conventional frequency transducer.

Measurement frequency f _im such commercial frequency is outputted to the waveform shaping circuit 11 via the isolation transformer 10 to insulate a DC voltage, to waveform shaping in the frequency signal f _i of the rectangular wave in the waveform shaping circuit 11, further one-shot circuit Output to 12.

The one-shot circuit 12 converts the frequency signal f _i to the pulse signal P _i having a predetermined pulse width.

On the other hand, a pulse signal is applied to the inverting input terminal (-) of the addition smoothing circuit 13 whose non-inverting input terminal (+) is connected to the common potential point COM.
Reference voltage V _R through the resistor R ₂ for bias with a reference voltage -V _R through the switch SW ₁ and a resistor R ₁ that is opened and closed by the P _i is applied is applied. Then, the inverting input terminal - to obtain an output voltages V ₁ in parallel circuit is connected the output terminal of a resistor and a capacitor between the output terminal ().

Next, the operation of the frequency transducer shown in FIG. 5 configured as described above will be described with reference to the waveform diagram shown in FIG. 6 and the characteristic diagram shown in FIG.

Figure 6 is a frequency signal f _i with repetition period T _i shown in (a) This is a pulse signal P _i having a predetermined pulse width τ as shown in FIG. 6 (b) by one shot circuit 12 switch
Since SW ₁ is turned on in response to the frequency signal f _i resistor R ₁
Current in response to the product of the reference voltage -V _R and the frequency signal f _i is the
i ₁ flows.

On the other hand, the resistor R ₂ measurement range of the frequency signal f _i (f _m ~f _M)
And it flows in the opposite direction from the frequency f _m to the corresponding current i ₂ is the reference voltage V _R of lower current i ₁ as a bias current of.

Therefore, the output voltage V _m (= 0) corresponding to the lower limit of the frequency f _m of the output voltage V _i and the measurement range corresponding to the frequency signal f _i as shown in FIG. 7 to the output terminal of the adder smoothing circuit 13 and The output voltage is obtained as the difference between B is a DC bias for expanding the measurement range.

That is, to expand the measurement range of the measurement frequency output voltage for a range of 0 to V _M by subtracting the current i ₁ from the current i ₂ from (0 to F _M) to (f _m ~f _M) it can.

For example, the output voltage V _i when the frequency signal f _i is input
Can be obtained as follows.

V _i = (f _i / f _M ) (R ₂ / R ₁ ) V _R −i ₂ R ₂ (1) Here, since f _i = f _m and V _i = 0, (f _m / f _{M) (R 2 / R 1} ) becomes V _R = i _{2 R 2.} Thus, (1) _{V i = (f i / f} M) is _{(R 2 / R 1) V} R - (f m / f M) (R 2 / R 1) V R = (f i -f m ) V _R R ₂ / f _M R ₁ ∝ (f _i −f _m ) (2)

<Problems The present invention is to solve> However, such a frequency transducers requires two reference voltages of the reference voltage V _R and -V _R obtained by inverting it. Accordingly, since the reference power supply V _R require such amplifiers to make reference voltage -V _R obtained by inverting this contaminated with variables here, one of the reference voltages of the two reference voltages of the other even stable There is a problem that the reference voltage becomes unstable.

<Means for Solving the Problems> In order to solve the above problems, the present invention provides a frequency dividing means for dividing a measurement frequency, and outputs a first trigger pulse in synchronization with an output of the frequency dividing means. First trigger pulse means;
Second trigger pulse means for outputting a second trigger pulse using the measurement frequency and an output related to the output of the frequency dividing means;
A clock oscillator that outputs a clock signal; a period counter that counts the clock signal for a period corresponding to the period of the measurement frequency set by the first trigger pulse and stores it as count data; and a count data preset by the second trigger pulse The counter value of the clock signal corresponding to the upper limit frequency of the measurement range is set, the clock signal is counted, and the count value of the clock signal is output. When the count value is reached, a presettable counter is output. Flip-flop means for outputting a pulse signal having a pulse width corresponding to the difference between the count value and the count data, and a switch connected to a reference voltage at one end and connected to a resistor at the other end and opened and closed by the pulse signal Means for converting the current into an output signal corresponding to the current flowing through the resistor. It is obtained so as to include a conversion unit.

<Operation> The first trigger pulse is output in synchronization with the divided output obtained by dividing the measurement frequency by the first trigger pulse means, and the measurement frequency and the output related to the divided output are used by the second trigger pulse means. To output a second trigger pulse.

The cycle counter is reset by the first trigger pulse, counts the clock signal during a period corresponding to the cycle of the measurement frequency, and stores the count as count data.

The presettable counter counts a clock signal in which the count data is preset by the second trigger pulse and the count value of the clock signal corresponding to the upper limit frequency of the measurement range is set, and outputs a carry signal when the count value is reached. I do.

Next, the flip-flop means is set by the first trigger pulse and reset by the carry signal to output a pulse signal having a pulse width corresponding to a difference between the count value and the count data.

The switch means to which the reference voltage is applied at one end is opened / closed by the pulse signal, and the current flowing therethrough is subjected to current exchange to produce an output signal.

<Example> Hereinafter, an example of the present invention will be described with reference to the drawings.
FIG. 1 is a block diagram showing the configuration of one embodiment of the present invention. Parts having the same functions as the conventional ones shown in FIGS. 5 to 7 are denoted by the same reference numerals, and the description thereof will be appropriately omitted.

14 is a frequency divider that divides the frequency signal f _i for example 1/2 minutes. Pulse signal P ₁ which is divided by 2 the frequency signal f _i is the output terminal Q is the pulse signal at its inverting output terminal <Q>
Pulse signal obtained by inverting the P ₁ <P _1> are output.

The pulse signal P ₁ is an input terminal of the trigger pulse circuit 15 to which the clock signal CLK is input, and an enable terminal of the cycle counter 16.
EN and EN are input to the enable end EN of the presettable counter 17, respectively.

The gate circuit 18 is output to the trigger pulse circuit 19 when the clock signal CLK is input by calculating the AND of the pulse signal <P _1> signals with the frequency f _i as a pulse signal P _2. In synchronism with the rising of the trigger pulse circuit 19 outputs a pulse signal P ₃ to a reset terminal RS of the presettable counter 17 as a reset signal.

Reference numeral 20 denotes a clock oscillator using a crystal, which outputs the generated clock signal CLK to the cycle counter 16, the clock end CL of the presettable counter 17, and the like.

Trigger pulse circuit 15 outputs a pulse signal P ₄ to its output in synchronization with the rising of the pulse signal P _1.

The period counter 16 counts the clock signal CLK during a period corresponding to the period T _i of the frequency signal f _i and stores it as count data N. The presettable counter 17 previously stores a clock signal corresponding to the upper limit frequency f _M of the measurement range. count M of CLK are preset, and outputs a carry pulse signal P ₅ reaches this count value M from the output terminal Q.

The flip-flop 21 outputs the pulse signal P ₄ to the set end S,
Carry pulse signal P ₅ is inputted to a reset terminal RS, and outputs a pulse signal P ₆ having a pulse width corresponding to the time width of this such as a pulse signal to the switch SW _1.

Switch SW ₁ is turned on for a time corresponding to the pulse width of the pulse signal P _6, the resistance from the reference voltage -V _R only this time
A current i ₃ flows through R ₁ .

This current i ₃ is converted into an output voltage V ₂ by a current exchange circuit 21 having a smoothing function and output to its output terminal.

Next, the operation of the frequency transducer configured as described above will be described with reference to the waveform diagram shown in FIG.

Figure 2 frequency signal f _i shown in (b) of the divider circuit 14 by 1/2
Is converted into a pulse signal P ₁ shown in Figure 2 half are circumferential (b). On the other hand, the pulse signal obtained by inverting the pulse signal P ₁ as shown in FIG. 2 (c) is <P _1> is output at its inverting output terminal <Q>.

AND circuit 18 outputs a pulse signal P ₂ shown in FIG. 2 by calculating the AND of the pulse signal <P _2> and the frequency signal f _i (D) to the trigger pulse circuit 19. Pulse signal P ₃ (FIG. 2 (f)) in synchronization with the rising of the pulse signal P ₂ is the trigger pulse circuit 19 to the reset terminal of the presettable counter 17
Output to RS.

On the other hand, the period counter 16 during the high-level pulse signal P ₁ which corresponds to one period T _i of the frequency signal f _i appearing at the output terminal Q of the frequency divider circuit 14 state (FIG. 2 (b)) Enabled state is a, is further counting value reset by the pulse signal P ₄ output from the trigger pulse circuit 15 holds the new clock signal counts the number of CLK the count value N (Fig. 2 (g)). Therefore, the count value N is equal to the clock signal CLK.
Assuming that the frequency is f _c , N = f _c / f _i (3)

Next, the presettable counter 17 is reset by the pulse signal P ₃ (FIG. 2), and the count value N is downloaded from the cycle counter 16. The presettable counter 17, which is the Enabled state pulse signal P ₁
Counts the clock signal CLK in addition to the count value N and reaches a preset preset value M (second
FIG outputs a carry-pulse signal P ₅ shown in (h)) and the second diagram from the output terminal Q (Li). The preset value M is set to be a value of _{M = f c / fm ... (} 4).

Flip-flop 21 outputs a pulse signal P ₆ shown in FIG. 2 as a low level (j) The carry-pulse signal P ₅ is reset to a high level in the pulse signal P ₄ to the switch SW _1. The pulse signal P ₆ has a pulse width corresponding to the difference between the preset value M and the count value N (M-N). The repetition period T ₆ is T ₆ = 2 / f _i = 2N / f _c (5) as can be seen from FIG.

Therefore, the switch SW ₁ controlled by the pulse signal P ₆
When the reference voltage V _R is switched and smoothed by the current conversion circuit 22, the output voltage V ₂ generated at the output terminal becomes as follows.

_{V 2 = [(M-N} ) / f c] V R R 3 / R 1 T 6 = (M-N) R 3 V R / 2NR 1 = [(M / N) -1] R 3 V R / R ₁ (6) Here, R ₃ is a resistor connected to the inverting input terminal and the output terminal of the current conversion circuit 22.

Here, using equations (3) and (4), V ₂ = (f _i −f _m ) R ₃ V _R / 2R ₁ f _{m m} (f _i −f _m ) (7) obtaining (f _i -f _m) output voltage V ₂ is proportional to.

FIG. 3 is a circuit diagram showing a partial embodiment showing the configuration of an input unit when a measurement signal is exchanged for a high frequency signal.

Frequency signals f _im resistor R _4, Zener diode Z _D, photodiode P _D is input to the circuit connected in series. Then, to obtain the frequency signal 2f _i light pulses that have been multiplied doubled its output is outputted to the photo-transistor P _T from the frequency signal f _i photodiode P _D corresponding. Incidentally, constitute a Fuotokapura 23 in photodiode P _D and phototransistor P _T.

In the above configuration, the measurement frequency shown in FIG.
The frequency f _im is doubled by the circuit shown in FIG. 3 and is output as 2f _im at its output terminal as shown in FIG. 4 (b).

By entering the measurement frequency 2f _im instead of the frequency signal f _i shown in FIG. 1 and waveform shaping, it can be twice the frequency to be measured fundamental frequency of operation. Doubling the basic operating frequency in this way has the advantage that the filter can be small and the response is fast.

<Effects of the Invention> As described above in detail with the embodiment, according to the present invention, the frequency measurement range is expanded by reducing the number of reference voltages to one. Based instability factors can be eliminated.

[Brief description of the drawings]

FIG. 1 is a block diagram showing the configuration of one embodiment of the present invention, FIG. 2 is a waveform diagram for explaining the operation of the embodiment shown in FIG. 1, and FIG. 3 is an input section when converted to a high frequency signal. FIG. 4 is a waveform diagram showing waveforms of various parts of the circuit shown in FIG. 3, FIG. 5 is a block diagram showing a configuration of a conventional frequency transducer, and FIG. Fifth
FIG. 7 is a waveform diagram for explaining the operation of the frequency transducer shown in FIG. 7, and FIG. 7 is a characteristic diagram showing characteristics of the frequency transducer shown in FIG. 11: Waveform shaping circuit, 12: One shot circuit, 13: Addition smoothing circuit, 14: Frequency divider circuit, 15: Trigger pulse circuit, 16: Period counter, 17: Presettable counter, 19 ... ... Trigger pulse circuit, 20 ... Clock oscillator,
21 ... Flip-flop, 22 ... Current conversion circuit.

Claims (1)

(57) [Claims] 1. A frequency dividing means for dividing a measuring frequency, a first trigger pulse means for outputting a first trigger pulse in synchronization with an output of the frequency dividing means, an output of the measuring frequency and an output of the frequency dividing means. A second trigger pulse means for outputting a second trigger pulse by using an output associated with the first trigger pulse, a clock oscillator for outputting a clock signal, and a period set by the first trigger pulse and corresponding to a period of the measurement frequency. A period counter that counts the clock signal and stores it as count data; and a count value of the clock signal corresponding to the upper limit frequency of the measurement range, wherein the count data is preset by the second trigger pulse, and A presettable counter for counting and outputting a carry signal when the count value is reached; Flip-flop means which is reset by the carry signal and outputs a pulse signal having a pulse width corresponding to the difference between the count value and the count data, a reference voltage is applied to one end and a resistor is connected to the other end A frequency transducer comprising: switch means opened / closed by the pulse signal; and current conversion means for converting an output signal corresponding to a current flowing through the resistor.