SU1695267A1 - Linear interpolator - Google Patents

Abstract

This invention relates to automation and computing. A linear interpolator is designed to convert numeric information about coordinate increments into output control signals and can be used in software systems for controlling machine tools. The purpose of the invention is to improve the accuracy of interpolation and the expansion of the field of application. The interpolator contains the master pulse generator, the shift register and increment counters along the coordinate axes, the register and counter of the length of the interpolated segment, the program reading unit, the control unit, logic elements and output frequency dividers. The advantage of the interpolator is the unambiguous dependence of the speed of movement of the controlled working organ on the frequency of the master oscillator. 2 Il.

Description

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The invention relates to automation and computer technology and is intended for use in software systems for controlling machine tools.

The purpose of the invention is to improve the accuracy of interpolation and the expansion of the field of application.

FIG. 1 shows a functional diagram of a linear interpolator; in fig.

2 shows a pulse shaper; FIG.

3- time diagram of work.

In the proposed interpolator, the frequency of the pulse sequence (fn) from the output of the counter (U) is proportional to the speed of movement of the working body along the interpolating segment

fn U / A qk

where U is the speed along the interpolable curve;

A is the magnitude of the unit displacement;

q is the base of the number system of coordinate increments (in this case, q 10);

k is the maximum possible size of digital equivalents of increments.

The linear interpolator contains a program 1 readout block, the shift register 2, the bits of which are divided into four groups 3-6 for writing the codes L, Dy, Ax, U, respectively, pulse generator 7, pulse counter 8 (counter L), pulse counter 9 (counter Ay), counter 10 pulses (counter Dx), counter 11 pulses (counter U), generator 12 pulses (constant frequency), dividers 13 and 14 frequencies, first 15, second 16 and third 17 triggers And 18 elements -20.

The pulse shaper 7 comprises a delay element 21 with a delay time τ, an element OR 22, and a divider 23 with a division factor q.

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FIG. For given pulses from the output of the counter 11; b - control pulses from the first output of the control unit, arriving at triggers 15-17 and counters 8-10; c — overflow pulses from the output of counter 10 (counter Lx), setting trigger 17 to the zero state; d — pulses of filling of the divider 13; d - overflow pulses from the output of counter 9 (Lu counter), setting trigger 16 to the zero state; e - the pulses of the filling of the divider 14,

The interpolator works as follows.

In order for the interpolator to function properly, it is necessary to ensure that the speed of movement of the working body along the coordinate axes depends on the increment value over them, while ensuring that the speed of movement along the interpolated segment is independent of its length L For this, the clock frequency is inversely proportional to L

The process of forming clock pulses with a frequency fT fn / L is carried out as follows.

The pulses from the output of the element And 18 with the frequency of the sequence fn fill the counter 8 pulses. When pulses enter it, corresponding to the value of L, the overflow signal from its output at a frequency fn / L is fed to the second input of the imaging unit 7. The imaging unit of the impulses 7 generates a pulse at the first output, which is a clock pulse. .

Each interpolation cycle begins with the input of information from the program frame by block 1, the initial start of which is made by a signal supplied from the outside, and then at the input of each frame, the start is made automatically by the signal from the second output of the pulse former 7.

Each frame includes codes: feed rates, which correspond to the inverse of the speed of movement of the working body along the interpolated segment.

-rj, increments of the abscissa Ah, increments of the ordinates Ay, interpolated length

segment L VA x + A /.

Information is entered into the interpolator from the frame by block 1 in the reverse binary-decimal code into the lower bits of group 3 of the shift register 2. Codes in block 1 are read from the frame and entered into the register.

2 in the following sequence: the feed rate code, the code Ax, the code A y, the code L. Thus, when a signal about the end of the frame entry appears, block 1 stops,

and in register 2 in group 6, the feed rate code is recorded, in group 5, the codes are Ah, in group 4, the code is Ay, in group 3, the code is L.

A signal from the output of block 1 about the end of the frame frame to the contents of the register 2 groups

shifting through their counting inputs is added one, frequency dividers 13 and 14 are set to zero. The same signal is fed to the first input of the driver 7 pulses, while at its output

with a delay r, a pulse is generated, which is fed to the control inputs of counters 8-10 and single inputs of flip-flops 15-17. In this case, on the leading edge of the pulse

there is a census of the contents of the groups of bits into counters 8-10, respectively, and on its falling edge triggers 15-17 are set to one. A time delay is necessary to ensure the summation of the unit in g / pp bits of register 2.

When switching triggers 15-17, the unit state And elements 18-20 open and the pulses from the output of counter 11 (Fig.

Over) enters the counters 8-10 and dividers 13 and 14. When the counter 10 is filled, an overflow pulse from its output (fig. Sv) flips the trigger 17 to the zero state at which the element 19 closes, the number of pulses received in the divider 13 frequency (Fig. 3g) on this clock corresponds to the increment A x. When the counter 9 is filled, an overflow pulse from its output (Fig. A) flips trigger 16 into

a zero state in which the AND element 20 is closed. The number of pulses received in the frequency divider 14 (Fig. ZE) at this time step corresponds to the increment of Ay. Upon receipt of pulses in the counter 8

in the quantity corresponding to the value of L, it is set to the zero state. The overflow signal from its output goes to the second input of the driver 7 pulses. This completes one cycle.

the work of the interpolator.

The pulse shaper 7, according to the signal received at its second input, generates at the first output a pulse (Fig. 36), from which the next clock cycle of the interpolator begins. The leading edge of this pulse, in the pause between pulses from the output of counter 11, rewrites the contents of groups of bits 3-5 into counters 8-10, respectively, and along its falling edge triggers 16 and 17 are set to

the single state and the previous, single, state of the trigger 15 is confirmed.

After the interpolator operation repeats qk times, at the second output of the imaging unit 7, a pulse is formed, the leading edge of which pushes the trigger 15 into the zero state, in which the element 18 closes and the back edge of this pulse starts block 1 to read the next program frame . During the qk clock cycles of each interpolation cycle, the frequency divisors Ah and qk come to the dividers 13 and 14. qk pulses, respectively, and Dx and D from the control pulses are output from the outputs of the dividers.

The frequency of the clock pulses from the first output of the driver 7 pulses is equal to fT fn / L. At each clock cycle, the Dh and Dy pulses are fed to the frequency dividers 13 and 14. Thus, for 1 s, Ax “fn / L pulses arrive at divider 13, and divider 13 receives impulses fn / L. The dividers 13 and 14 frequencies divide the frequency of the corresponding pulse sequence by qk. Thus, the frequency of the pulse sequences at the outputs of the dividers

13 and 14 is equal to Dx - fn / L qk and Ay.fn / bgk, respectively.

The use of an interpolator allows for high speed in software control systems to provide accurate interpolation of both large and small increments and, in addition, to withstand the speed of movement of the controlled working body according to its values specified for technological reasons.

Claims (1)

A linear interpolator comprising a pulse generator, three AND elements, a first frequency divider, three pulse counters, and a program reading unit, the control output of which is connected to the shift control input of each of the four groups of bits of the shift register, the count input which are connected to the output of the input of the program reading unit and the first input of the pulse former, the bit outputs of each group the shift register bits are connected to the group of information inputs of the corresponding pulse counter, the first output the pulse former is connected to the recording control inputs of the first, second, and third pulse counters and the S inputs of the first and second triggers, whose outputs are connected to the first inputs of the first and second And elements, respectively, the second input of the first And element, and , the output of the first pulse counter is connected to the second input of the pulse generator, the second output of which is connected to the input. Start of the program reading unit, the information output of which is connected to the information input of small Sheha discharge shift register and the output of the first element I is connected to the counting inputs of the second pulse counter and the first frequency divider, characterized in that, in order to increase the interpolation accuracy and expand the field of application, into it entered the third trigger, the fourth pulse counter and the second frequency divider, the input Setting in About which is connected to the output End of the input of the program reading unit and the input Setting in About the first the frequency divider, the counting input of the second frequency splitter is connected to the output of the third element I and to the counting input of the third pulse counter, the output of which is connected to the control input of the third the trigger, the setup input of which is connected to the S-input of the first trigger, the control input of which is connected to the second output of the pulse generator, the second input of the second element I is connected to the control input and the overflow output of the fourth pulse counter, the counting input of which is connected to the output of the pulse generator, and the group of information inputs — with the bit outputs of the corresponding fourth group of bits of the shift register; the outputs of the first and second frequency dividers are the outputs of a linear interpolator; g of the second pulse counter is connected to the control the second trigger trigger, and the counting input of the first pulse counter - with the output of the second element I. 1 21 8 move 2 1 Output1  Output 2 , 11GShLShSh1G1LLLLLL. s JI Dx l JlЛJlШlГL lГl ГLГL I LU . ppppppp ppp Fm 3