JPS61207032U - - Google Patents
Info
- Publication number
- JPS61207032U JPS61207032U JP9070285U JP9070285U JPS61207032U JP S61207032 U JPS61207032 U JP S61207032U JP 9070285 U JP9070285 U JP 9070285U JP 9070285 U JP9070285 U JP 9070285U JP S61207032 U JPS61207032 U JP S61207032U
- Authority
- JP
- Japan
- Prior art keywords
- semiconductor wafer
- groove
- cross piece
- holding device
- thickness
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 claims description 10
Landscapes
- Packaging Frangible Articles (AREA)
Description
第１図は本考案装置の１実施例の部分斜視図、
第２図は同装置の部分平面図、第３図は同装置の
部分側面図である。
１…ボート、２…半導体ウエハ、７，８，９，
１０…クロスピース、３，４，５，６…凹溝。
FIG. 1 is a partial perspective view of one embodiment of the device of the present invention;
FIG. 2 is a partial plan view of the same device, and FIG. 3 is a partial side view of the same device. 1...Boat, 2...Semiconductor wafer, 7, 8, 9,
10...Cross piece, 3, 4, 5, 6... Concave groove.
Claims (1)
支持する凹溝を有する複数のクロスピースと、各
クロスピースの端部を連結する連結部とを備える
半導体ウエハ保持装置において、第１クロスピー
スの第１凹溝と第２クロスピースの第２凹溝とは
その開口幅が何れも前記半導体ウエハの厚さに比
べて十分大きく、かつ、前記第１凹溝は前記半導
体ウエハの第１表面にまた第２凹溝は前記半導体
ウエハの第２表面にそれぞれ対接するように構成
してなることを特徴とする半導体ウエハ保持装置
。 (2) 前記第１凹溝と前記第２凹溝の、前記半導
体ウエハに対接する各側壁面が該半導体ウエハの
厚さに相当する分だけ変位していることを特徴と
する実用新案登録請求の範囲第(1)項記載の半導
体ウエハ保持装置。[Claims for Utility Model Registration] (1) Semiconductor wafer holder comprising a plurality of cross pieces, each having a groove for receiving and supporting the outer periphery of the semiconductor wafer, and a connecting portion connecting the ends of each cross piece. In the apparatus, the opening widths of the first groove of the first cross piece and the second groove of the second cross piece are both sufficiently larger than the thickness of the semiconductor wafer, and the first groove is A semiconductor wafer holding device characterized in that a second groove is configured to be in contact with the first surface of the semiconductor wafer and the second groove is in contact with the second surface of the semiconductor wafer, respectively. (2) A request for registration of a utility model characterized in that each side wall surface of the first groove and the second groove facing the semiconductor wafer is displaced by an amount corresponding to the thickness of the semiconductor wafer. A semiconductor wafer holding device according to scope (1).
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP9070285U JPS61207032U (en) | 1985-06-14 | 1985-06-14 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP9070285U JPS61207032U (en) | 1985-06-14 | 1985-06-14 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS61207032U true JPS61207032U (en) | 1986-12-27 |
Family
ID=30645930
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP9070285U Pending JPS61207032U (en) | 1985-06-14 | 1985-06-14 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS61207032U (en) |
-
1985
- 1985-06-14 JP JP9070285U patent/JPS61207032U/ja active Pending