JPS61206261A - High withstanding-voltage planar type semiconductor device - Google Patents
High withstanding-voltage planar type semiconductor deviceInfo
- Publication number
- JPS61206261A JPS61206261A JP4646785A JP4646785A JPS61206261A JP S61206261 A JPS61206261 A JP S61206261A JP 4646785 A JP4646785 A JP 4646785A JP 4646785 A JP4646785 A JP 4646785A JP S61206261 A JPS61206261 A JP S61206261A
- Authority
- JP
- Japan
- Prior art keywords
- base
- collector
- guard ring
- layer
- voltage
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims description 7
- 238000000926 separation method Methods 0.000 claims description 3
- 239000000758 substrate Substances 0.000 claims description 3
- 238000002955 isolation Methods 0.000 abstract description 5
- 230000005684 electric field Effects 0.000 abstract description 3
- 230000015556 catabolic process Effects 0.000 description 4
- 239000012535 impurity Substances 0.000 description 3
- 230000007423 decrease Effects 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
- H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
- H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
- H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
- H01L29/0619—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE] with a supplementary region doped oppositely to or in rectifying contact with the semiconductor containing or contacting region, e.g. guard rings with PN or Schottky junction
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
- H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
- H01L29/0638—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for preventing surface leakage due to surface inversion layer, e.g. with channel stopper
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Bipolar Transistors (AREA)
Abstract
Description
【発明の詳細な説明】
〔発明の目的〕
（産業上の利用分野）
本発明は高耐圧プレーナ型半導体装置におけるベース・
コレクタ間耐圧の向上に関するものである。[Detailed Description of the Invention] [Object of the Invention] (Industrial Field of Application) The present invention is directed to the base and
This relates to improving collector-collector breakdown voltage.
（従来技術およびその問題点）
２以上のベース領域をもつ高耐圧プレーナ型半導体装置
として、例えば第１図（ａ）（ｂ）ｌ二本す上面図およ
びＡ−Ａ部断面図の如く、Ｎ型基板上に選択的Ｃ：Ｎ型
不純物を拡散してコレクタ層（１）を形成し、次（二Ｐ
型不純物を選択的に拡散してベース領域（２）（３）と
、１乃至複数箇のガードリング領域（４）（５１（６）
を形成する。そして更にＮ型不純物を選択的に拡散して
エミッタ領域（７）（８）と、チャンネルストッパ領域
（９）を形成した前段トランジスタＡと、後段トランジ
スタＢとからなる高耐圧プレーナ型ダーリントントラン
ジスタがよく知られている。(Prior art and its problems) As a high voltage planar semiconductor device having two or more base regions, for example, as shown in FIGS. A collector layer (1) is formed by selectively diffusing C:N type impurities on the type substrate, and then a collector layer (1) is formed on the type substrate.
Type impurities are selectively diffused to form base regions (2) (3) and one or more guard ring regions (4) (51 (6).
form. A high breakdown voltage planar Darlington transistor consisting of a front-stage transistor A and a rear-stage transistor B, in which emitter regions (7) and (8) and a channel stopper region (9) are formed by selectively diffusing N-type impurities, is often used. Are known.
しかし以上のようにベース領域を高抵抗領域（高抵抗分
離層）ｆｉｎにより分離して、前・後段トランジスタＡ
、 Ｂを形成したものでは、空乏層の拡がりを示す第
２図のように、前・後段トランジスタＡ、 Ｈのそれ
ぞれのベース領域（２）（３）間の分離用高抵抗分離層
（１０ａ）と、これが対面するガードリング（４）間の
高抵抗領域顛中に空乏層の拡がりにくい部分（ａ）を生
じて電界の集中を招く。従ってダーリントントランジス
タの電流対電圧特性を示す第３図中の実線図示のように
、ベース・コレクタ間耐圧が低電流領域において急激に
低下する所謂２段落特性にな番）、図中点線図示のよう
に電流に対して一定にならない。その結果ベース・コレ
クタ間の耐圧が低電流時において低下する欠点がある。However, as described above, the base region is separated by the high resistance region (high resistance separation layer) fin, and the front and rear transistors A
, B, as shown in Figure 2, which shows the expansion of the depletion layer, there is a high-resistance isolation layer (10a) for isolation between the base regions (2) and (3) of the front and rear transistors A and H, respectively. This creates a portion (a) in which the depletion layer is difficult to expand in the high resistance region between the opposing guard rings (4), leading to concentration of the electric field. Therefore, as shown by the solid line in Figure 3, which shows the current vs. voltage characteristics of the Darlington transistor, the base-collector breakdown voltage rapidly decreases in the low current region, resulting in a so-called two-stage characteristic (number), as shown by the dotted line in the figure. The current is not constant. As a result, there is a drawback that the withstand voltage between the base and the collector decreases at low current.
本発明は上記の如き従来の高耐圧プレーナ型半導体装置
が持つ欠点の除去を目的としてなされたものであって、
次に図面を用いてその詳細を説明する。The present invention was made for the purpose of eliminating the drawbacks of the conventional high voltage planar semiconductor device as described above.
Next, the details will be explained using the drawings.
（問題点を解決するための手段）
第４図（ａＯｂ）は本発明の一実施例を示す上面図、そ
のＡ−Ａ部矢視断面図（第１図と同一符号部分は同等部
分を示す）であって、本発明の特徴とするところは次の
点（＝ある。即ち本発明においては前段トランジスタＡ
のベース領域（２）と、後段トランジスタＢのベース領
域（３）とをそれぞれ高抵抗分離層ａαを介して島状に
囲む８の字形のガードリング層（４）を設け、その外側
に共通のガードリング層（５）（６１を設けて、前段ト
ランジスタＡと後段トランジスタＢとがガードリング層
（４）（＝よって分離される構造にしたことを特徴とす
るものである。(Means for Solving the Problems) Fig. 4 (aOb) is a top view showing an embodiment of the present invention, and a cross-sectional view taken along the line A-A (the same reference numerals as in Fig. 1 indicate the same parts). ), and the present invention is characterized by the following points (=).In other words, in the present invention, the front stage transistor A
A figure-8 guard ring layer (4) is provided which surrounds the base region (2) of the transistor B and the base region (3) of the subsequent transistor B in an island shape through a high-resistance isolation layer aα. The structure is characterized in that a guard ring layer (5) (61) is provided so that the front-stage transistor A and the rear-stage transistor B are separated by the guard ring layer (4).
（作用および効果）
以上のように高抵抗分離層ααにより、それぞれ独立に
島状に囲まれた前・後段トランジスタのベース領域（２
）（３）の対向面およびその周囲に、ガードリング層（
４）を設けた構造にすれば、前記第１図で説明した従来
構造のように、ベース領域（２１ｆ３）間の高抵抗分離
層（１０ａ）の端部がこれと直角に交わる高抵抗分離層
αｌを介してガードリング層（４）と対面する部分がな
い。従って第２図で前記したような空乏層の拡がりにく
いデルタ状部分（ａ）を生ずることがないので、ベース
領域（２）（３）の角部付近における電界の集中は緩和
される。その結果ベース（２）とコレクタ（１）、或い
はベース（３）とコレクタ（１）間にバイアス電圧を印
加したとき、第３図中に点線によって図示するように、
ベース・コレクタ間の耐圧は電流の大小にか＼わりなく
一定になり、第１図で前記した従来構造のように２段落
ちになることがない。従って本発明によれば従来構造の
欠点を一掃して低電流時においても、ベース・コレクタ
間耐圧の低下を招くおそれのないダーリントントランジ
スタを提供しつる。(Functions and Effects) As described above, the base regions (2
)(3) and its surroundings, a guard ring layer (
4), as in the conventional structure explained in FIG. There is no portion facing the guard ring layer (4) via αl. Therefore, since the delta-shaped portion (a) in which the depletion layer is difficult to spread as described above in FIG. 2 is not generated, the concentration of the electric field near the corners of the base regions (2) and (3) is alleviated. As a result, when a bias voltage is applied between the base (2) and the collector (1) or between the base (3) and the collector (1), as shown by the dotted line in FIG.
The withstand voltage between the base and the collector remains constant regardless of the magnitude of the current, and there is no drop in two stages as in the conventional structure described above in FIG. Therefore, according to the present invention, it is possible to eliminate the drawbacks of the conventional structure and provide a Darlington transistor that does not cause a drop in the base-collector breakdown voltage even at low currents.
（変形例）
以上はベース領域に最も近く設けられたガードリング層
（４）によＩ）、前段と後段トランジスタＡ。(Modification) The above is based on the guard ring layer (4) provided closest to the base region (I), front stage and rear stage transistors A.
Ｂとを分離した例について説明した。しかしガードリン
グ層を複数箇備えた場合には、例えば第５図のように最
内側の第１番目のガードリング層（４ａ） （４ｂ）に
よってベース領域（２Ｈ３１をそれぞれ独立に囲むよう
にし、２番目のガードリング層（５）により分離するよ
うにしてもよい。また第６図に示すように第１．第２番
目のガードリング層（４）（５）により、それぞれベー
ス領域（２）（３）を独立に囲んだものを、第３番目の
ガードリング層（６）により）分離するようにしてもよ
い。An example in which B is separated has been explained. However, when a plurality of guard ring layers are provided, for example, as shown in FIG. They may be separated by the first and second guard ring layers (5).Also, as shown in FIG. 3) may be separated by a third guard ring layer (6).
（適用例）
なお以上においては２つのベース領域をもつダーリント
ントランジスタを例にとって説明したが、３箇以上のベ
ース領域をもつこの種高耐圧ブレーナ型半導体装置に適
用して、前記本発明の効果を得ることができる。(Application example) Although the explanation has been given above using a Darlington transistor having two base regions as an example, it is possible to apply the effects of the present invention to this type of high-voltage Brehner type semiconductor device having three or more base regions. Obtainable.
第１図（ａ）（ｂ）は従来のダーリントントランジスタ
の上面図およびそのＡ−Ａ部矢視断面図、第２図はその
空乏層の拡がり図、第３図は電流−電圧特性図、第４図
（ａ）（ｂ）は本発明の一実施例を示す上面図、そのＡ
−Ａ部矢視断面図、第５図および第６図はそれぞれ本発
明の変形例を示す上面図である。
Ａｏ・−前段トランジスタ、
Ｂ・・・・後段トランジスタ、 （１）・・・・コレク
タ、（２）（３）・・・・ベース、 （４）（５１（６
）・・・・ガードリング、（７）（８）・・・・エミッ
タ、（９）・・０チヤンネルストツパ。
θｌ） （１０ａ）・・・・高抵抗分離層、（ａｌ・・
・・空乏層の拡がっていない部分（高抵抗層）。Figures 1 (a) and (b) are a top view of a conventional Darlington transistor and a sectional view taken along the line A-A, Figure 2 is a diagram showing the spread of its depletion layer, Figure 3 is a current-voltage characteristic diagram, and 4 (a) and (b) are top views showing one embodiment of the present invention, and its A
5 and 6 are top views showing modified examples of the present invention, respectively. Ao - front stage transistor, B... rear stage transistor, (1)... collector, (2) (3)... base, (4) (51 (6)
)...Guard ring, (7) (8)...Emitter, (9)...0 channel stopper. θl) (10a)... High resistance separation layer, (al...
...The part where the depletion layer has not expanded (high resistance layer).
Claims (1)
型の複数箇のベース領域を備えると共に、これらのベー
ス領域を囲むように第２導電型のガードリング層を備え
た高耐圧プレーナ型半導体装置において、それぞれ高抵
抗分離層により囲まれた上記複数箇のベース領域を共通
に包囲し、かつ各ベース領域間が分離されるようにガー
ドリング層を設けたことを特徴とする高耐圧プレーナ型
半導体装置。A high-voltage planar semiconductor comprising a first conductivity type semiconductor substrate serving as a collector layer, a plurality of base regions of a second conductivity type, and a guard ring layer of a second conductivity type surrounding these base regions. A high-voltage planar type device, characterized in that a guard ring layer is provided to commonly surround the plurality of base regions each surrounded by a high-resistance separation layer and to isolate each base region. Semiconductor equipment.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP4646785A JPS61206261A (en) | 1985-03-11 | 1985-03-11 | High withstanding-voltage planar type semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP4646785A JPS61206261A (en) | 1985-03-11 | 1985-03-11 | High withstanding-voltage planar type semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS61206261A true JPS61206261A (en) | 1986-09-12 |
Family
ID=12747973
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP4646785A Pending JPS61206261A (en) | 1985-03-11 | 1985-03-11 | High withstanding-voltage planar type semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS61206261A (en) |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS60119770A (en) * | 1983-12-01 | 1985-06-27 | Fuji Electric Co Ltd | Semiconductor device |
-
1985
- 1985-03-11 JP JP4646785A patent/JPS61206261A/en active Pending
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS60119770A (en) * | 1983-12-01 | 1985-06-27 | Fuji Electric Co Ltd | Semiconductor device |
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