JPS61206232A - Sheet type annealing apparatus - Google Patents

Sheet type annealing apparatus

Info

Publication number
JPS61206232A
JPS61206232A JP60046525A JP4652585A JPS61206232A JP S61206232 A JPS61206232 A JP S61206232A JP 60046525 A JP60046525 A JP 60046525A JP 4652585 A JP4652585 A JP 4652585A JP S61206232 A JPS61206232 A JP S61206232A
Authority
JP
Japan
Prior art keywords
ring
substrate
annealing
annealed
temperature
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP60046525A
Other languages
Japanese (ja)
Inventor
Shizunori Ooyu
大湯　静憲
Nobuyoshi Kashu
夏秋　信義
Tadashi Suzuki
匡 鈴木
Yasuo Wada
恭雄 和田
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP60046525A priority Critical patent/JPS61206232A/en
Publication of JPS61206232A publication Critical patent/JPS61206232A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/324—Thermal treatment for modifying the properties of semiconductor bodies, e.g. annealing, sintering
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/26—Bombardment with radiation
    • H01L21/263—Bombardment with radiation with high-energy radiation
    • H01L21/268—Bombardment with radiation with high-energy radiation using electromagnetic radiation, e.g. laser radiation
    • H01L21/2686—Bombardment with radiation with high-energy radiation using electromagnetic radiation, e.g. laser radiation using incoherent radiation

Abstract

PURPOSE:To enable to perform annealing process doing no damage to a substrate at all due to difference in temperature by a method wherein a substrate is annealed as it is held by a ring which is held by specimen holding quartz bars in an annealing vessel. CONSTITUTION:An annealing vessel 1 is provided with quartz-made holding bars 2 around 2mm in diameter to hold a ring 3. The diameter of holding bars 2 is made small enough actually coming into point contact with the ring 3 so that the thermal capacity of holding bars 2 may have no effect on the temperature A of ring 3 at all due to the contact with ring 3. Next a tungsten halogen lamp is used as a heating light source while the light emitted from the lamp is not absorbed into the quartz-made annealing vessel 1 but to be absorbed into the silicon-made ring 3 and a silicon-made substrate 4. In such a constitution, the temperature distribution B may be made even within the silicon substrate 4 and a part of the ring 3 although the temperature may become lower than that in the central part within the range around 5-10mm distant from the outer diameter end of ring 3.

Description

【発明の詳細な説明】 〔発明の利用分野〕 本発明は、枚葉式アニール装置に係り、特に、被アニー
ル基板全体の温度を均一に保つのに好適な枚葉式アニー
ル装置に関する。DETAILED DESCRIPTION OF THE INVENTION [Field of Application of the Invention] The present invention relates to a single-wafer type annealing apparatus, and particularly to a single-wafer type annealing apparatus suitable for maintaining a uniform temperature over the entire substrate to be annealed.

〔発明の背景〕[Background of the invention]

従来の急熱・急冷の７ニール処理を行なう短時間アニー
ル装置において、アニール時における被アニール基板を
アニール容器に保持する場合、例えは米国Ａ　、　Ｇ　
、　Ａ　５ｓｏｃｉａｔａｓ社のＨＥＡＴＰＵＬＳＥ　
、モデル２１０１に用いられているように、被アニール
基板を複数の石英棒で支持するように構成となっていた
。このような構成では被アニール基板端部が上記基板中
央附近より低温になるために、急冷時に上記基板端部に
熱的損傷（例えば、シリコン基板の端部でのスリップラ
イン）が発生するという問題がある。また、同社製のＨ
ＥＡＴＰＵＬＳＥ　、モデル２１０Ｔでは。In a short-time annealing device that performs a conventional seven-annealing process of rapid heating and rapid cooling, when the substrate to be annealed is held in an annealing container during annealing, for example, in the United States A, G
, A 5sociatas HEATPULSE
, model 2101, the structure was such that the substrate to be annealed was supported by a plurality of quartz rods. In such a configuration, since the edge of the substrate to be annealed is at a lower temperature than near the center of the substrate, there is a problem that thermal damage (for example, slip line at the edge of the silicon substrate) occurs at the edge of the substrate during rapid cooling. There is. In addition, the company's H
EATPULSE, model 210T.

上記基板の端部周辺にリングを設は上記熱的損傷を軽減
するような構成となっていたが、上記基板の自動搬送に
対する配慮がなされていなかった。Although a ring was provided around the edge of the substrate to reduce the thermal damage, no consideration was given to automatic transportation of the substrate.

さらに、上記熱的損傷を軽減するために、特開昭５９−
１２１８３２号に記載されているように、アニール容器
内の基板の端部周辺に補助ヒータを設けた構成とする提
案がある。しかし、急冷時の温度変化に対する補助ヒー
タによる温度制御が困難であるため、完全な熱的損傷の
発生を防止することができなかった。Furthermore, in order to reduce the above-mentioned thermal damage,
As described in Japanese Patent No. 121832, there is a proposal for a structure in which an auxiliary heater is provided around the edge of the substrate in the annealing container. However, because it is difficult to control the temperature using the auxiliary heater against temperature changes during rapid cooling, it has not been possible to completely prevent thermal damage.

〔発明の目的〕[Purpose of the invention]

本発明の目的は、上記従来装置の有する問題点を解決し
、自動搬送が可能であり、かつ、被アニール基板の端部
への熱的損傷の発生を防止する枚葉式短時間アニール装
置を提供することにある。An object of the present invention is to provide a single-wafer type short-time annealing apparatus that solves the problems of the conventional apparatus described above, is capable of automatic transportation, and prevents thermal damage to the edges of the substrate to be annealed. It is about providing.

〔発明の概要〕[Summary of the invention]

上記目的を達成するために、本発明は第１図（ａ）、（
ｂ）に示すようにアニール容器１の試料支持用石英棒２
上に支持されたリング３により、被アニール基板４を保
持してアニールを行なう構成とする。ここで、リング３
の材質を被アニール基板４と同じ材質とするのが最も好
ましい、リング３の内径は、被アニール基板４の外径よ
り５ｍｍ程度以内小さくするのが好ましい、その理由は
、加熱源５からのエネルギーを被アニール基板およびリ
ングに直接吸収させ、リングと被アニール基板との接触
部をできるだけ小さくすることにより。In order to achieve the above object, the present invention has been developed as shown in FIGS.
As shown in b), the quartz rod 2 for supporting the sample in the annealing container 1
The ring 3 supported above holds the substrate 4 to be annealed and performs annealing. Here, ring 3
It is most preferable that the material of the ring 3 is the same as that of the substrate 4 to be annealed.The inner diameter of the ring 3 is preferably smaller than the outer diameter of the substrate 4 to be annealed by about 5 mm. is absorbed directly into the annealed substrate and the ring, and the contact area between the ring and the annealed substrate is made as small as possible.

リングと被アニール基板の加熱状態を等しくできるから
である。このようにすれば、上記リング３および上記被
アニール基板における、アニール時の温度分布は、第１
図（Ｑ）に示したような分布となる。従って、上記リン
グ３の温度差の大きい端部には熱的損傷が生じるものの
、上記被アニール基板４の温度分布が実質的に均一なた
め、上記被アニール基板には熱的損傷が生じない。This is because the heating state of the ring and the substrate to be annealed can be made equal. In this way, the temperature distribution during annealing in the ring 3 and the substrate to be annealed is
The distribution will be as shown in Figure (Q). Therefore, although thermal damage occurs at the ends of the ring 3 where the temperature difference is large, the temperature distribution of the annealing target substrate 4 is substantially uniform, so no thermal damage occurs to the annealing target substrate.

また、被アニール基板４のアニール容器１内への搬入お
よびアニール容器１からの搬出は、第２図に示したよう
に、被アニール基板４を保持したリング３も含めて自動
搬送を行なうことができる。Further, as shown in FIG. 2, the substrate to be annealed 4 can be automatically transported, including the ring 3 holding the substrate to be annealed, into and out of the annealing container 1. can.

ここで、リング３には、被アニール基板４が搬送中にリ
ング３から落下・移動しないように、溝６を設けるのが
よい、また、自動搬送用のアーム７には、リング３を真
空チャックする部分８、真空チャック用配管９およびリ
ング３および被アニール基板４の落下防止用ビン１０を
設けることが好ましい。Here, it is preferable to provide a groove 6 in the ring 3 to prevent the substrate 4 to be annealed from falling or moving from the ring 3 during transportation. It is preferable to provide a portion 8, a vacuum chuck pipe 9, a ring 3, and a bottle 10 for preventing the substrate 4 to be annealed from falling.

従って、本発明によれば、被アニール基板に対する熱的
損傷を効果的に防止しつつアニール処理が可能で、自動
搬送が可能な枚葉式短時間アニール装置が構成できる。Therefore, according to the present invention, it is possible to construct a single-wafer type short-time annealing apparatus that can perform annealing treatment while effectively preventing thermal damage to the substrate to be annealed, and can automatically transport the substrate.

〔発明の実施例〕[Embodiments of the invention]

以下１本発明の一実施例を第１図ないし第３図により説
明する。An embodiment of the present invention will be described below with reference to FIGS. 1 to 3.

第１図のように、被アニール基板４を直径１００膳腸１
厚さ５００ｐｍのシリコン基板とした場合に。As shown in Figure 1, the substrate 4 to be annealed is
When using a silicon substrate with a thickness of 500 pm.

直径１２５ｍｍ、厚さ５００μｍのシリコン基板を以下
のように加工してリング３とした。リングの内径３ａは
、被アニール基板４がリング３との接触部での熱的影響
を受けることをできるだけ少なくするために、被アニー
ル基板径約５脂脂小さくし、また、溝の部分の径３ｂは
、被アニール基板４がアニール中および搬送中にズレや
落下を生じないように被アニール基板径より約２ｍ１大
きくした。A silicon substrate with a diameter of 125 mm and a thickness of 500 μm was processed to form a ring 3 as follows. In order to minimize the thermal influence of the annealed substrate 4 at the contact portion with the ring 3, the inner diameter 3a of the ring is made approximately 5 times smaller than the diameter of the annealed substrate, and the diameter of the groove portion is 3b was made approximately 2 m1 larger than the diameter of the annealed substrate 4 to prevent the annealed substrate 4 from shifting or falling during annealing and transportation.

ここで、リングの内径３ａは９６＋ｓｎφとし、溝６の
部分の径３ｂを１０２５ｍφとした。また、溝６の部分
のリング３の厚さは、約２００μｍとした。Here, the inner diameter 3a of the ring was set to 96+snφ, and the diameter 3b of the groove 6 portion was set to 1025 mφ. Further, the thickness of the ring 3 at the groove 6 portion was approximately 200 μm.

この溝によれば、アニール中および搬送中にリング３か
らの被アニール基板のズレや落下が生じない、このリン
グ３用シリコン基板の加工は、シリコン窒化膜をマスク
材とし、４０ｗｅｔ％のＫＯＨエツチング液（液温的６
０℃）によりシリコンをエツチングして行なった。According to this groove, the substrate to be annealed does not shift or fall from the ring 3 during annealing and transportation.The silicon substrate for the ring 3 is processed using 40 wet% KOH etching using a silicon nitride film as a mask material. liquid (liquid temperature 6
This was done by etching silicon at 0°C.

また、アニール容器１は１石英製とし、窒素等の雰囲気
ガスが供給できるようにした。このアニール容器１には
、リング３を支持するための、直径が約２鳳璽程度の石
英製支持棒２を取り付けた。Further, the annealing container 1 was made of quartz so that an atmospheric gas such as nitrogen could be supplied thereto. A quartz support rod 2 having a diameter of about 2 mm was attached to this annealing container 1 to support the ring 3.

上記支持棒２の径は、リング３との接触部において支持
棒の熱容量がリング３の温度に影響を与えないように、
十分小さくする必要があるため、上記のように細くし、
上記支持棒２とリング３とは実質上点接触させた。The diameter of the support rod 2 is set such that the heat capacity of the support rod does not affect the temperature of the ring 3 at the contact portion with the ring 3.
It needs to be small enough, so make it thin as above,
The support rod 2 and ring 3 were substantially in point contact.

次に、加熱源５としては、タングステン・ハロゲンラン
プを用いた。このランプからの光は、石英製アニール容
器に吸収されることなく、シリコン製リング３とシリコ
ン基板４に吸収される。上記寸法のリングを用いれば、
上記光の吸収量がリング３とシリコン基板４で同じにな
るため、リング３とシリコン基板４の加熱状態は等しく
なる。Next, as the heat source 5, a tungsten halogen lamp was used. The light from this lamp is absorbed by the silicon ring 3 and the silicon substrate 4 without being absorbed by the quartz annealing container. If you use a ring with the above dimensions,
Since the amount of light absorbed by the ring 3 and the silicon substrate 4 are the same, the heating states of the ring 3 and the silicon substrate 4 are equal.

従って、リング３の外径内での温度分布は、リング３の
外径の端５〜１１０ｌ１程度の部分で中心部より低温に
なるものの、シリコン基板４およびリング３の一部では
均一な温度分布となる。尚、被アニール基板４およびリ
ング３の部分で均一な温度にするため、加熱源５からの
ランプ強度を、中心部で弱く、周辺部で強くしてアニー
ル処理を行なった。アニール温度の範囲を、９００℃〜
１２００℃とし、また、アニール時の昇降温速度を２０
０℃／秒程度とした場合、リング３の周辺部でスリップ
ラインが発生したものの、被アニール基板４であるシリ
コン基板にはスリップラインの発生は認められなかった
。Therefore, although the temperature distribution within the outer diameter of the ring 3 is lower at the edge of the outer diameter of the ring 3 from about 5 to 110 l1 than the center, the temperature distribution is uniform in the silicon substrate 4 and a part of the ring 3. becomes. In order to maintain a uniform temperature in the substrate 4 and the ring 3, the annealing process was performed with the lamp intensity from the heat source 5 weak at the center and strong at the periphery. The range of annealing temperature is 900℃~
The temperature was set at 1200°C, and the temperature increase/decrease rate during annealing was set at 20°C.
When the temperature was about 0° C./second, slip lines were generated around the ring 3, but no slip lines were observed on the silicon substrate, which is the substrate to be annealed 4.

次に、搬送系は第２図に示すように、以下のようにした
。自動搬送用のアーム７は、上下左右の移動および回転
ができる機能を有し、リング３を真空チャックする石英
製の容器８、真空チャック用の真空配管９．および、リ
ング３および被アニール基板４の落下防止用の石英製ビ
ン１０を具備している。Next, as shown in FIG. 2, the conveyance system was constructed as follows. The arm 7 for automatic conveyance has the function of being able to move vertically and horizontally and rotate, and is equipped with a quartz container 8 for vacuum chucking the ring 3, and a vacuum piping 9 for the vacuum chuck. A quartz bottle 10 for preventing the ring 3 and the substrate 4 to be annealed from falling is also provided.

搬送の実施例を第３図に示す、試料（被アニール基板お
よびリング）１１は、未処理カセット部１２→アニール
部１３→処理カセット部１４の順に、第２図で示したア
ーム１５を用いて搬送した。An example of transportation is shown in FIG. 3. The sample (substrate to be annealed and ring) 11 is transported in the order of unprocessed cassette part 12 → annealed part 13 → treated cassette part 14 using the arm 15 shown in FIG. Transported.

まず、試料１１をアーム１５の真空チャックにより保持
して未処理カセット部１２から取り出す（ａ）０次に、
アニール部１３に試料１１を入れるべきアーム１５の回
転を行ない（ｂ）、試料１１を７ニ一ル部１３に挿入す
る（Ｃ）、その後。First, the sample 11 is held by the vacuum chuck of the arm 15 and taken out from the unprocessed cassette part 12 (a) Next,
The arm 15 for inserting the sample 11 into the annealing section 13 is rotated (b), and the sample 11 is inserted into the annealing section 13 (c), and then.

真空チャックの動作を停止させ、試料１１をアニール部
にセットしたのちアーム１５を引き出す（ｄ）、ここで
、所定のアニールを行ない、アニール処理後の試料１１
をアーム１５に真空チャックにより保持し、アニール部
１３から引き出す（ｅ）、そして、アニール後の試料１
１を処理カセット１４に搬送する（ｆ−ｈ）、この搬送
系では、被アニール基板をリングから落下させることな
く搬送でき、スルーブツトとして、約６０〜１００枚／
時間の自動搬送が可能である。After stopping the operation of the vacuum chuck and setting the sample 11 in the annealing section, the arm 15 is pulled out (d). Here, predetermined annealing is performed and the sample 11 after the annealing process is
is held on the arm 15 by a vacuum chuck and pulled out from the annealing section 13 (e), and the sample 1 after annealing is
1 to the processing cassette 14 (fh). With this transport system, the substrates to be annealed can be transported without falling from the ring, and approximately 60 to 100 substrates/substrate can be transported as a throughput.
Automatic transportation of time is possible.

〔発明の効果〕〔Effect of the invention〕

本発明によれば、急冷・急熱プロセスである短時間アニ
ールによっても、被アニール基板に温度差に起因する熱
的損傷を生じることなしに、アニール処理が可能である
ので、アニール処理の信頼性が高になるという効果を有
する。また、被アニール基板を保持したリングごと搬送
できるので、枚葉式短時間アニール処理の自動化に効果
がある。According to the present invention, even by short-time annealing, which is a rapid cooling/heating process, the annealing process can be performed without causing thermal damage to the annealed substrate due to temperature difference, thereby increasing the reliability of the annealing process. This has the effect of increasing the Furthermore, since the ring holding the substrate to be annealed can be transported, it is effective in automating single-wafer type short-time annealing processing.

【図面の簡単な説明】[Brief explanation of drawings]

第１図は本発明の詳細な説明する図、第２図は本発明の
搬送構成を示す図、第３図は本発明における搬送系の動
きの例を示した図である。 １・・・アニール容器、２・・・支持棒、３・・・リン
グ、４・・・被アニール基板、５・・・加熱源、６・・
・リングの溝、７．１５・・・アーム、８・・・真空チ
ャック部、９・・・真空チャック用配管、１０・・・ビ
ン、１１・・・試料。 １２・・・未処理カセット部、１３・・・アニール部、
ＶＪｌ　　　口 Ｔｈ　−罵シ配°フ１：：、−ノＬ靭すＪピｔ　Ｓ　ｎ
１ｍ１→菖　３　図 ′ｆＪ３FIG. 1 is a diagram for explaining the present invention in detail, FIG. 2 is a diagram showing a conveyance structure of the present invention, and FIG. 3 is a diagram showing an example of the movement of the conveyance system in the present invention. DESCRIPTION OF SYMBOLS 1... Annealing container, 2... Support rod, 3... Ring, 4... Substrate to be annealed, 5... Heat source, 6...
- Ring groove, 7.15... Arm, 8... Vacuum chuck part, 9... Vacuum chuck piping, 10... Bottle, 11... Sample. 12... Unprocessed cassette section, 13... Annealing section,
VJl Mouth Th - Abusive Arrangement F1::, -ノL J Pit S n
1m1→Iris 3 Figure'fJ3

Claims (1)

【特許請求の範囲】[Claims] 　枚葉式の被アニール基板の搬送系、上記基板をアニー
ルするアニール容器、および、加熱源を少なくともそな
え上記基板の端部周辺を保持する上記基板と同材質また
は、上記基板と熱的性質が実質的に同じ材質のリングを
設け、上記リングに上記基板を保持したまま搬送および
、アニール容器内に支持することを特徴とする枚葉式ア
ニール装置。A transport system for a single-wafer substrate to be annealed, an annealing container for annealing the substrate, and at least a heating source that holds the periphery of the substrate and is made of the same material as the substrate or has substantially the same thermal properties as the substrate. 1. A single wafer annealing apparatus, characterized in that a ring is provided with a ring made of the same material, and the substrate is transported and supported in an annealing container while being held by the ring.
JP60046525A 1985-03-11 1985-03-11 Sheet type annealing apparatus Pending JPS61206232A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP60046525A JPS61206232A (en) 1985-03-11 1985-03-11 Sheet type annealing apparatus

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP60046525A JPS61206232A (en) 1985-03-11 1985-03-11 Sheet type annealing apparatus

Publications (1)

Publication Number Publication Date
JPS61206232A true JPS61206232A (en) 1986-09-12

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ID=12749692

Family Applications (1)

Application Number Title Priority Date Filing Date
JP60046525A Pending JPS61206232A (en) 1985-03-11 1985-03-11 Sheet type annealing apparatus

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JP (1) JPS61206232A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US10559479B2 (en) 2018-02-27 2020-02-11 Toshiba Memory Corporation Semiconductor manufacturing apparatus and manufacturing method of semiconductor device

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US10559479B2 (en) 2018-02-27 2020-02-11 Toshiba Memory Corporation Semiconductor manufacturing apparatus and manufacturing method of semiconductor device

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