JPH0750273A - Short time annealing equipment - Google Patents

Short time annealing equipment

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Publication number
JPH0750273A
JPH0750273A JP18393194A JP18393194A JPH0750273A JP H0750273 A JPH0750273 A JP H0750273A JP 18393194 A JP18393194 A JP 18393194A JP 18393194 A JP18393194 A JP 18393194A JP H0750273 A JPH0750273 A JP H0750273A
Authority
JP
Japan
Prior art keywords
wafer
short
short time
semiconductor substrate
diameter
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP18393194A
Other languages
Japanese (ja)
Other versions
JP2876994B2 (en
Inventor
Kiyotsugu Tanaka
清嗣 田中
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sony Corp
Original Assignee
Sony Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sony Corp filed Critical Sony Corp
Priority to JP6183931A priority Critical patent/JP2876994B2/en
Publication of JPH0750273A publication Critical patent/JPH0750273A/en
Application granted granted Critical
Publication of JP2876994B2 publication Critical patent/JP2876994B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

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Abstract

PURPOSE:To provide a short time annealing equipment wherein the uniformity and the controllability of wafer temperature can be obtained while the wafer is maintained in a necessary gas pressure atmosphere. CONSTITUTION:In an equipment wherein an almost disk-shaped semiconductor substrate 1 is put on a retainer 2 which is heated in a short time by a heating means 6, short time anneal of the semiconductor substrate 1 is performed mainly by the heat conduction from the retainer 2, a ring-shaped cover 3 which covers the outer periphery of the semiconductor substrate 1 and has a hole whose diameter is 55-80% of the diameter of the semiconductor substrate 1 in the central part is put on the retainer 2.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【産業上の利用分野】本発明は、SiやGaAs等の半
導体基板の特性向上のための短時間アニール装置に関す
る。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a short-time annealing apparatus for improving the characteristics of semiconductor substrates such as Si and GaAs.

【0002】[0002]

【従来の技術】短時間アニール法は、SiやGaAsの
半導体基板(以下ウエハと言う)のキャリアの高濃度活
性化や急峻な濃度プロファイルを得ることが可能であ
り、ウエハへの熱的影響が少ないことから開発段階では
盛んに用いられるようになっている。
2. Description of the Related Art A short-time annealing method is capable of obtaining a high concentration activation of carriers and a steep concentration profile of a semiconductor substrate of Si or GaAs (hereinafter referred to as a wafer), and thus has no thermal influence on the wafer. Since it is scarce, it is widely used in the development stage.

【0003】しかし、短時間アニール法では、基本的
に、ウエハ保持体(以下サセプタと言う)、加熱炉本体
及び雰囲気ガスが熱的平衡になっていないことから、ウ
エハの温度の均一性を得ることが難しく、また正確な温
度制御も困難である。このために再現性に乏しく更に大
口径ウエハのアニールにおいては、ウエハ内の温度不均
一からスリップラインなる結晶欠陥が生じ易いという実
用上の大きな問題がある。
However, in the short-time annealing method, the wafer holder (hereinafter referred to as a susceptor), the heating furnace main body, and the atmosphere gas are not in thermal equilibrium, so that the temperature uniformity of the wafer is obtained. Is difficult and accurate temperature control is also difficult. For this reason, there is a serious problem in practical use that crystal defects such as slip lines are likely to occur due to temperature non-uniformity in the wafer when annealing a large diameter wafer with poor reproducibility.

【0004】S.J.Pearton等は、GaAsウ
エハの短時間アニールにおいて、カーボン・グラファイ
ト製サセプタからの間接的熱伝導を利用し、更に蓋で追
って温度均一性をよくすることによって、スリップライ
ンの発生を防止できたと報告(J.Appl.Phy
s.Vol 66(1989)pp663)している。
また、同報告によれば、アニール中のウエハの中央部
と、外周辺部で6℃〜7℃以上の温度差があるとスリッ
プラインが発生する。
S. J. Pearton et al. Reported that in the short-time annealing of GaAs wafers, the indirect heat conduction from the carbon-graphite susceptor was used, and the temperature uniformity was improved by following the lid to prevent the occurrence of slip lines ( J. Appl. Phy
s. Vol 66 (1989) pp 663).
Further, according to the report, a slip line occurs when there is a temperature difference of 6 ° C. to 7 ° C. or more between the central part of the wafer being annealed and the outer peripheral part.

【0005】[0005]

【発明が解決しようとする課題】しかしながら、上記の
方法によっても充分な温度均一性を得ることが難しい。
また蒸気圧の高い構成元素を含む化合物、例えばGaA
sのウエハのアニールを行なう場合には蒸発し易いAs
の解離を抑えるために雰囲気中のAs分圧の制御が不可
欠である。
However, it is difficult to obtain sufficient temperature uniformity even by the above method.
Also, compounds containing constituent elements with high vapor pressure, such as GaA
When the wafer of s is annealed, As easily evaporates.
It is essential to control the As partial pressure in the atmosphere in order to suppress the dissociation of As.

【0006】例えば、n型ドーパントであるSiを5×
1013cm-2注入されたGaAsウエハを900℃12
0秒の短時間アニールした場合のシートキャリア濃度と
アニール時の雰囲気としてのAsH3 分圧の関係は図3
のように得られる。この結果から、AsH3 分圧が3T
orr以下では、ウエハ中のAsの解離によりキャリア
濃度が減少してしまうことが示される。従って、この場
合、蓋でウエハを完全に覆うようなサセプタは好ましく
ない。
For example, if the Si which is an n-type dopant is 5 ×
GaAs wafers implanted at 10 13 cm -2 at 900 ° C 12
Fig. 3 shows the relationship between the sheet carrier concentration in the case of annealing for a short time of 0 second and the partial pressure of AsH 3 as the atmosphere during annealing.
Is obtained as. From this result, AsH 3 partial pressure is 3T
It is shown that below orr, the carrier concentration decreases due to the dissociation of As in the wafer. Therefore, in this case, a susceptor in which the lid completely covers the wafer is not preferable.

【0007】本発明の課題は、ウエハを必要なガス圧雰
囲気に保ちつつ、ウエハ温度の均一性、制御性が得られ
る短時間アニール装置を提供することである。
An object of the present invention is to provide a short-time annealing apparatus capable of obtaining uniformity and controllability of wafer temperature while keeping the wafer in a necessary gas pressure atmosphere.

【0008】[0008]

【課題を解決するための手段】本発明短時間アニール装
置は例えば図1,図2に示す如く、略円板状のウエハ1
をサセプタ2上に載せてサセプタ2を加熱手段6で短時
間加熱し、主としてサセプタ2からの熱伝達によってウ
エハ1の短時間アニールを行なう短時間アニール装置に
おいて、ウエハ1の外周部を覆う、中央部にウエハ1の
直径の55%〜80%の直径の穴を有するリング状の覆
い3をサセプタ2上に載せた短時間アニール装置であ
る。
The short-time annealing apparatus of the present invention has a substantially disk-shaped wafer 1 as shown in FIGS. 1 and 2, for example.
Is placed on the susceptor 2, the susceptor 2 is heated for a short time by the heating means 6, and the wafer 1 is annealed in a short time mainly by heat transfer from the susceptor 2. This is a short-time annealing apparatus in which a ring-shaped cover 3 having a hole having a diameter of 55% to 80% of the diameter of the wafer 1 is placed on the susceptor 2.

【0009】[0009]

【作用】サセプタ2上のウエハ1は、先に昇温するサセ
プタ2からの熱伝達によって加熱されるので、ウエハ1
の厚み方向に、温度分布(下面側ほど温度が高い)が生
じ、熱膨張のためにウエハ1は上に反ってしまう。その
結果、ウエハ1の周辺部はサセプタ2から離れるために
熱伝達が減少して、ウエハ2の外周部の温度は中央部に
比べて低くなってしまう。このようにして生ずる温度分
布を防止するために、特にウエハ1の外周部のみを覆う
リング状の覆い3を用いることが効果的である。ウエハ
1の中央部まで覆う覆いの使用は、中央部の温度も高め
てしまいかえって温度均一化の効果を損なうことにな
る。本発明者の実験によればウエハ径の55%から80
%の範囲の直径の穴を中央部にもうけたリング状の覆い
3でウエハ1の外周部のみを覆うのが温度均一化に有効
である。
The wafer 1 on the susceptor 2 is heated by the heat transfer from the susceptor 2 which is heated first.
A temperature distribution (the temperature is higher toward the lower surface) occurs in the thickness direction of the wafer 1, and the wafer 1 warps upward due to thermal expansion. As a result, since the peripheral portion of the wafer 1 is separated from the susceptor 2, heat transfer is reduced, and the temperature of the outer peripheral portion of the wafer 2 becomes lower than that of the central portion. In order to prevent the temperature distribution generated in this manner, it is particularly effective to use the ring-shaped cover 3 that covers only the outer peripheral portion of the wafer 1. The use of the cover that covers the central portion of the wafer 1 also raises the temperature of the central portion and rather impairs the effect of temperature uniformity. According to the experiments conducted by the present inventor, 55% to 80% of the wafer diameter
It is effective to uniformize the temperature to cover only the outer peripheral portion of the wafer 1 with the ring-shaped cover 3 having a hole with a diameter in the range of%.

【0010】またこのような大きな開口の穴をもつリン
グ状の覆い3の使用は、必要な雰囲気ガス圧を保つ上で
殆ど障害とならない。更に、覆いの穴を通し放射温度計
によりアニール中のウエハ中央部の表面温度をモニター
できるので、アニールにおける温度制御性が向上する。
Further, the use of the ring-shaped cover 3 having such a large opening hole causes almost no obstacle in maintaining the required atmospheric gas pressure. Further, since the surface temperature of the central portion of the wafer during annealing can be monitored by the radiation thermometer through the hole in the cover, the temperature controllability during annealing is improved.

【0011】[0011]

【実施例】以下、図面を参照して本発明短時間アニール
装置の実施例につき説明する。図1は本発明の実施例の
短時間アニール装置の構成を示す概念図である。また図
2はその要部の拡大図である。
Embodiments of the short-time annealing apparatus of the present invention will be described below with reference to the drawings. FIG. 1 is a conceptual diagram showing the configuration of a short-time annealing apparatus according to an embodiment of the present invention. Further, FIG. 2 is an enlarged view of the main part thereof.

【0012】図1の中で、1はアニールすべきウエハ、
2はウエハ1を載せるための円形状のサセプタであっ
て、ウエハ1が乗る部分は厚さdでその外周部には、ウ
エハ1を安定に置くための段部2a及びリング状の覆い
3をウエハ1の上面から離して安定して置くための段部
2bをもつ堰堤が設けられている。
In FIG. 1, 1 is a wafer to be annealed,
Reference numeral 2 denotes a circular susceptor on which the wafer 1 is placed. A portion on which the wafer 1 is mounted has a thickness d and a stepped portion 2a and a ring-shaped cover 3 for stably placing the wafer 1 are provided on the outer peripheral portion thereof. A dam having a step portion 2b for stably placing the wafer 1 away from the upper surface of the wafer 1 is provided.

【0013】ここで段部2aの高さはアニール中の反っ
たウエハが接触しない程度であればよい。このサセプタ
2は透明な溶融石英管4の中に透明な溶融石英板5を介
して水平に支持される。
Here, the height of the step portion 2a may be such that the warped wafer during annealing does not come into contact with it. The susceptor 2 is horizontally supported in a transparent fused quartz tube 4 via a transparent fused quartz plate 5.

【0014】この溶融石英管4の内部は雰囲気としてN
2 とH2 とAsH3 の混合ガスが流される。溶融石英管
4の外部下方に複数本の加熱用電球6、例えばハロゲン
電球(参照、物理学辞典、培風館昭和59年発行)が設
けられている。7,8,9,10は金メッキした金属板
から成る熱遮蔽板である。
The inside of the fused quartz tube 4 is filled with N 2 as an atmosphere.
A mixed gas of 2 , H 2, and AsH 3 is flown. A plurality of heating light bulbs 6, for example, halogen light bulbs (for example, reference, physics dictionary, Baifukan, published in 1984) are provided below the fused silica tube 4. Reference numerals 7, 8, 9, and 10 denote heat shield plates made of a metal plate plated with gold.

【0015】以上のように構成される短時間アニール装
置において、ハロゲン電球6を点燈することによって、
ハロゲン電球6からの輻射光が溶融石英管4及び溶融石
英板5を通してサセプタ2に吸収され、サセプタ2は急
速に昇温する。そしてウエハ1はサセプタ2からの熱伝
達により加熱される。ここで、サセプタ2の温度は熱電
対12によって測定され、また、ウエハ1の中央部の上
表面温度は熱遮蔽板7,8に連通して開けられた穴7
a,8a及び溶融石英管4を通して放射温度計13によ
ってモニタされる。
In the short-time annealing device configured as described above, by turning on the halogen bulb 6,
Radiant light from the halogen bulb 6 is absorbed by the susceptor 2 through the fused quartz tube 4 and the fused quartz plate 5, and the susceptor 2 rapidly rises in temperature. Then, the wafer 1 is heated by heat transfer from the susceptor 2. Here, the temperature of the susceptor 2 is measured by the thermocouple 12, and the upper surface temperature of the central portion of the wafer 1 is a hole 7 which is opened in communication with the heat shield plates 7 and 8.
It is monitored by a radiation thermometer 13 through a, 8a and the fused silica tube 4.

【0016】後述する実施例及び比較例に於けるウエハ
の短時間アニールは覆いの内径の大きさ以外は全て下記
の条件で行われた。
The short-time annealing of the wafers in Examples and Comparative Examples described later was performed under the following conditions except for the inner diameter of the cover.

【0017】ウエハ‥‥Siを5×1013/cm-2イオ
ン注入されたGaAs基板で径76mm、厚さ0.6m
mのもの。
Wafer: A GaAs substrate on which Si is ion-implanted at 5 × 10 13 / cm -2 , diameter: 76 mm, thickness: 0.6 m
m.

【0018】サセプタ‥‥材質はカーボン・グラファイ
トで外形100mm、ウエハの載る部分の厚さ(d)2
mmのもの。
The susceptor is made of carbon graphite and has an outer diameter of 100 mm, and the thickness of the portion on which the wafer is placed (d) 2
mm.

【0019】覆い‥‥材質はカーボン・グラファイトで
外形86mm、厚さ0.5mmの円板の中央部に実施
例、比較例における所定の径の穴を開けたもの。
Cover: A material made of carbon graphite having an outer diameter of 86 mm and a thickness of 0.5 mm, and a hole having a predetermined diameter in the examples and comparative examples is formed in the center of the disk.

【0020】雰囲気‥‥N2 とH2 とAsH3 の混合ガ
スでAsH3 の分圧は5Torrとした。
Atmosphere: A mixed gas of N 2 , H 2 and AsH 3 and a partial pressure of AsH 3 was set to 5 Torr.

【0021】加熱‥‥ハロゲン電球により加熱、昇温速
度を50℃/secとしサセプタの設定温度900℃で
120sec保持し、その後自然冷却した。
Heating: heating with a halogen bulb, heating rate at 50 ° C./sec, holding at a preset temperature of the susceptor of 900 ° C. for 120 sec, followed by natural cooling.

【0022】アニール結果に対する評価手段としては、
次の方法を用いた。 イ)X線トポグラフによるスリップライン等の欠陥の観
察 ロ)エッチピットによる欠陥密度の観察(エッチング液
としてKOH溶液を使用) ハ)ホール測定によるシートキャリア濃度測定(Van
der Pauw法);アニールしたウエハの中央部
及び周辺部から5mm×5mmを切り出して測定した。
As an evaluation means for the annealing result,
The following method was used. A) Observation of defects such as slip lines by X-ray topography b) Observation of defect density by etch pits (KOH solution is used as etching liquid) c) Sheet carrier concentration measurement by hole measurement (Van
der Pauw method); 5 mm × 5 mm was cut out from the central portion and the peripheral portion of the annealed wafer and measured.

【0023】実施例1 覆いとして、カーボン・グラファイト製の円板の中心に
ウエハ直径の80%の穴を開けたリング状の覆いを用い
て上記の条件で短時間アニールを行った。その結果、ス
リップラインの発生は、X線トポグラフで認められなか
った。またアニール前のウエハと比較してエッチピット
の増加は認められなかった。ホール測定によるキャリア
濃度は、ウエハ中央部で3.06×1013cm-2、ウエ
ハの外周部で2.95×1013cm-2でウエハの中央部
と外周部との差は殆どなかった。
Example 1 As a cover, a ring-shaped cover in which a hole of 80% of the diameter of the wafer was formed in the center of a carbon graphite disk was used, and annealing was performed for a short time under the above conditions. As a result, the occurrence of slip lines was not recognized on the X-ray topography. No increase in etch pits was observed as compared with the wafer before annealing. The carrier concentration by hole measurement was 3.06 × 10 13 cm -2 in the central part of the wafer and 2.95 × 10 13 cm -2 in the outer peripheral part of the wafer, and there was almost no difference between the central part and the outer peripheral part of the wafer. .

【0024】実施例2 覆いとして、カーボン・グラファイト製の円板の中心に
ウエハ直径の55%の穴を開けたリング状の覆いを用い
て実施例1と同様に短時間アニールを行った。その結果
は実施例1と同様の結果で、スリップラインの発生は認
められなかった。
Example 2 As a cover, a ring-shaped cover having a hole of 55% of the diameter of the wafer formed in the center of a carbon-graphite disk was used and annealed in the same manner as in Example 1 for a short time. The result was the same as that of Example 1, and no slip line was observed.

【0025】比較例1 覆いとしても何も用いないこと以外は実施例1と同様に
短時間アニールを行った。その結果アニールされたウエ
ハは著しい密度のスリップラインの発生がX線トポグラ
フにより認められた。また、エッチピット密度もアニー
ル前のウエハに比べて増大が認められた。
Comparative Example 1 Short-time annealing was performed in the same manner as in Example 1 except that nothing was used as a cover. As a result, the annealed wafer was found by the X-ray topography to show the occurrence of slip lines with a significant density. Also, the etch pit density was increased compared to the wafer before annealing.

【0026】ホール測定によるキャリア濃度は、ウエハ
中央部で3.05×1013cm-2、ウエハの外周部で
2.6×1013cm-2でウエハ外周部のキャリア濃度は
中央部に比べてかなり小さい。これらの結果から、覆い
のない場合、短時間アニールに於いて、ウエハ外周部は
ウエハ中央部に比べて加熱温度がかなり低くなっている
ことが示される。
The carrier concentration by hole measurement is 3.05 × 10 13 cm -2 in the central portion of the wafer and 2.6 × 10 13 cm -2 in the outer peripheral portion of the wafer. The carrier concentration in the outer peripheral portion of the wafer is higher than that in the central portion. Is quite small. From these results, it is shown that the heating temperature in the outer peripheral portion of the wafer is much lower than that in the central portion of the wafer in the short-time annealing without the cover.

【0027】比較例2 覆いとして、カーボン・グラファイト製の円板の中央に
ウエハ直径の85%の穴を開けたリング状の覆いを用い
て実施例1と同様の短時間アニールを行った。
Comparative Example 2 The same short-time annealing as in Example 1 was performed using a ring-shaped cover having a hole of 85% of the wafer diameter formed in the center of a carbon graphite disk as a cover.

【0028】比較例3 覆いとして、カーボン・グラファイト製の円板の中央に
ウエハ直径の50%の穴を開けたリング状の覆いを用い
て実施例1と同様の短時間アニールを行った。
Comparative Example 3 As a cover, a ring-shaped cover having a hole of 50% of the diameter of the wafer in the center of a carbon / graphite disk was used, and short-time annealing similar to that in Example 1 was performed.

【0029】比較例4 覆いとして、カーボン・グラファイト製の円板の中心に
ウエハ直径の30%の穴を開けたリング状の覆いを用い
て実施例1と同様の短時間アニールを行った。
Comparative Example 4 As a cover, a ring-shaped cover having a hole of 30% of the diameter of the wafer formed in the center of a carbon / graphite disk was used and the short-time annealing similar to that in Example 1 was performed.

【0030】比較例5 覆いとして、穴のないカーボン・グラファイト製の円板
を用いて実施例1と同様の短時間アニールを行った。
Comparative Example 5 A short-time annealing similar to that in Example 1 was performed using a carbon-graphite disk having no holes as a cover.

【0031】比較例1〜比較例5ではいずれもスリップ
ラインの発生やエッチピットの増大が認められた。スリ
ップラインの発生密度はX線トポグラフの写真から判断
して、比較例1〜比較例5について、次の順であった。 比較例5>比較例1>比較例4>比較例3≒比較例2 エッチピットの密度も上記の順であった。
In each of Comparative Examples 1 to 5, the occurrence of slip lines and the increase of etch pits were recognized. The density of occurrence of slip lines was determined from the photographs of the X-ray topography, and was in the following order for Comparative Examples 1 to 5. Comparative Example 5> Comparative Example 1> Comparative Example 4> Comparative Example 3≈Comparative Example 2 The density of etch pits was also in the above order.

【0032】また比較例5ではアニールしたウエハ表面
は白濁して荒れており、Asの解離が生じたものと思わ
れる。なお、穴のない覆いを用いた比較例5においてス
リップラインの発生が最も著しかったことは、前述の
S.J.Pearon等の報告と合わないが、その理由
は不明である。
In Comparative Example 5, the surface of the annealed wafer was clouded and rough, and it is considered that As was dissociated. It should be noted that the occurrence of the slip line was most remarkable in Comparative Example 5 using the cover having no hole. J. It does not match the report of Pearon et al., But the reason is unknown.

【0033】[0033]

【発明の効果】本発明によれば、ウエハを必要なガス圧
雰囲気に保ちつつ、ウエハ温度を均一にでき、その結果
スリップライン等の欠陥の発生を防止した短時間アニー
ルが可能となる。またウエハ中央部の表面の温度を放射
温度計でモニターできるのでアニールにおける温度制御
性が向上する。
According to the present invention, the wafer temperature can be made uniform while maintaining the wafer in a necessary gas pressure atmosphere, and as a result, short-time annealing can be performed while preventing the occurrence of defects such as slip lines. Further, since the temperature of the surface of the central portion of the wafer can be monitored by the radiation thermometer, the temperature controllability in annealing is improved.

【図面の簡単な説明】[Brief description of drawings]

【図1】本発明の実施例の短時間アニール装置の構成を
示す概念図である。
FIG. 1 is a conceptual diagram showing a configuration of a short-time annealing apparatus according to an embodiment of the present invention.

【図2】本発明の要部拡大図である。FIG. 2 is an enlarged view of a main part of the present invention.

【図3】Siをイオン注入したGaAsウエハの短時間
アニールの雰囲気(AsH3 分圧)とシートキャリア濃
度の測定結果を示す図である。
FIG. 3 is a diagram showing a measurement result of a short-time annealing atmosphere (AsH 3 partial pressure) and a sheet carrier concentration of a GaAs wafer into which Si ions are implanted.

【符号の説明】[Explanation of symbols]

1 ウエハ 2 サセプタ 3 リング状覆い 4 溶融石英管 6 ハロゲン電球 12 熱電対 13 放射温度計 1 Wafer 2 Susceptor 3 Ring Cover 4 Fused Quartz Tube 6 Halogen Light Bulb 12 Thermocouple 13 Radiation Thermometer

Claims (1)

【特許請求の範囲】[Claims] 【請求項1】 略円板状の半導体基板を保持体上に載せ
て保持体を加熱手段で短時間加熱し、主として前記保持
体からの熱伝達によって前記半導体基板の短時間アニー
ルを行なう装置において、前記半導体基板の外周部を覆
う、中央部に前記半導体基板の直径の55%〜80%の
直径の穴を有するリング状の覆いを保持体上に載せるこ
とを特徴とする短時間アニール装置。
1. An apparatus for placing a substantially disk-shaped semiconductor substrate on a holder, heating the holder for a short time by a heating means, and for annealing the semiconductor substrate for a short time mainly by heat transfer from the holder. A short-time annealing apparatus, characterized in that a ring-shaped cover having a hole having a diameter of 55% to 80% of the diameter of the semiconductor substrate in the central portion, which covers the outer peripheral portion of the semiconductor substrate, is placed on a holder.
JP6183931A 1994-07-13 1994-07-13 Short-time annealing equipment Expired - Fee Related JP2876994B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP6183931A JP2876994B2 (en) 1994-07-13 1994-07-13 Short-time annealing equipment

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP6183931A JP2876994B2 (en) 1994-07-13 1994-07-13 Short-time annealing equipment

Publications (2)

Publication Number Publication Date
JPH0750273A true JPH0750273A (en) 1995-02-21
JP2876994B2 JP2876994B2 (en) 1999-03-31

Family

ID=16144319

Family Applications (1)

Application Number Title Priority Date Filing Date
JP6183931A Expired - Fee Related JP2876994B2 (en) 1994-07-13 1994-07-13 Short-time annealing equipment

Country Status (1)

Country Link
JP (1) JP2876994B2 (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2012009885A (en) * 2011-08-25 2012-01-12 Ushio Inc Lighting system
JP2019153736A (en) * 2018-03-06 2019-09-12 株式会社Screenホールディングス Substrate processing apparatus

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6365631A (en) * 1986-09-05 1988-03-24 Nec Corp Specimen heating holder
JPH02159720A (en) * 1988-12-14 1990-06-19 Nec Corp Heat treatment of semiconductor device

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6365631A (en) * 1986-09-05 1988-03-24 Nec Corp Specimen heating holder
JPH02159720A (en) * 1988-12-14 1990-06-19 Nec Corp Heat treatment of semiconductor device

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2012009885A (en) * 2011-08-25 2012-01-12 Ushio Inc Lighting system
JP2019153736A (en) * 2018-03-06 2019-09-12 株式会社Screenホールディングス Substrate processing apparatus
US11495476B2 (en) 2018-03-06 2022-11-08 SCREEN Holdings Co., Ltd. Substrate treating apparatus

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