JPS61204748A - Program tracing system - Google Patents

Abstract

PURPOSE:To trace a data at the optional part of a program without taking trouble at all to the program of a body, by setting a trace element bit and a trace parameter to a parity use memory. CONSTITUTION:A trace controlling circuit 7 is provided, and a trace element bit and a trace parameter are stored in a parity data use ROM 3, so that a trace use program is stored in a RAM 4. The trace controlling circuit 7 is constituted with an interruption generating circuit 71 and a trace parameter latching circuit 72, etc. Also, in the parity data use ROM 3, trace element bits T0,T1......and trace parameters TP0,TP1......are stored together with parity bits P0,P1.......

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a method for tracing a program stored in a ROM (J-only memory) in an information processing device or the like.

[Conventional technology]

FIG. 4 is a block diagram showing a general configuration of an information processing device. In the figure, 1 is a microprocessor (μ
2 is a memory (ROM) for storing programs, 3 is a memory (OM) for storing parity data, and 4 is a memory (RAM) for storing processing data, etc. ), 5 is a memory control circuit, 6 is a parity check circuit, AB is an address bus,
DB is a data bus, CB is a control bus, CL is a control signal line (control signal; MC) for controlling the memories 2 and 3.4, and LP is an interrupt signal line (interrupt signal line) that notifies processor 1 of the occurrence of a parity error. The processor 1 executes instructions and processes based on the program code and parity data stored in the ROM.

Here, we will explain the operation and parity check when the processor 1 fetches an instruction, as well as the conventional tracing method, etc.0 First, the processor 1 transfers the address value indicated by its internal program counter to the address bus AB, and Each control signal such as a read signal is output to the control bus CB. At this time, the control circuit 5 outputs a memory control signal MC for reading data to the memories 2 and 3, and thereby the memories 2 and 3 output data at the specified address and parity data at a predetermined timing. be done. The parity check circuit 6 checks these data, and if there is a parity error, an error occurrence interrupt signal PI is notified to the processor 1. Processor 1 performs error processing based on this interrupt signal, and if there is no parity error, processor 1 takes program data into the processor at a predetermined timing and performs the processing specified by this data. A predetermined process is performed by repeatedly performing the operation.

[Problem that the invention seeks to solve]

Now, when running these programs, if you want to know the operating status and progress of processor 1 from the outside, it is normal to connect a debugging tool dedicated to the processor, but it is easy to use a debugging tool that is built into the device. It is not possible to connect a debugging tool to the system, and even if it is possible to do so, in the case of complex phenomena, problems may not actually occur due to the trap of stopping execution midway through, and it is difficult to trace the problem.
It may become impossible to do so. For this reason, it is possible to add a trace program to sample events in advance to the necessary part of the ROM program, collect the trace result data in RAM, read it externally, and analyze it. will be carried out. However, since tracing is performed without knowing the cause, there may be situations where the entire process has to be recreated if predictions are wrong. Or, because the necessary data is not available,
You may have to recreate it many times.

Furthermore, in order to make the tracing program more powerful, the main program itself must be modified, and the preparation work is complicated and takes an extremely long time, among other problems.

[Means for solving problems]

a first memory that stores trace request bits and trace parameters of each program executed by the processor; a second memory that stores a tracing program for tracing each program; and a trace request bit that is set. In this case, a trace control circuit is provided which temporarily stores trace parameters and generates an interrupt signal to the processor.

[Effect]

When the processor receives an interrupt signal from the trace control circuit, it refers to the trace parameters, branches to the trace program registered in the second memory, and performs the specified trace processing. This will allow you to run the main program.

〔Example〕

#! Figure 1 is a block diagram showing an embodiment of the present invention, Figure #IIA is a block diagram showing a concrete example of the trace control circuit in Figure 1, and Figure 1B is a configuration diagram showing a concrete example of the parity data ROM in Figure 1. It is a diagram.

The main differences between FIG. 1 and FIG. 4 are that a trace control circuit 7 is provided, trace request bits and trace parameters are stored in the parity data ROM 3, and the trace program is stored in the RAM 4. It is a point. The trace control circuit 7 is comprised of a 1-interrupt generation circuit 71, a trace parameter latch circuit 72, etc., as specifically shown in FIG. 1A. In addition, the parity data hole OM3 has a trace request bit 'ro*'.
r1... and trace parameters TPO, T
Pl... is the parity bit poe Pi...
... and \ are stored, for example, as shown in FIG. 1B. Note that the trace request bit and trace parameters are R
It is not OM memory 3 (-It is possible to store it in the appropriate memory of Ryu, and the trace program is also ELA
It can be stored not in the M memory 4 (, R,0M2, etc.) but in an empty space.

Here, its operation will be explained.

First, the processor 1 takes in a program code from the memory 2. At this time, parity data is output from the memory 3 to the data line DL at a predetermined timing, so
The parity check circuit 6 performs a parity check, and if an error occurs, outputs a parity error interrupt signal PI to the processor 1. Further, at the same time as the parity data is read from the memory 3, the trace request bit TH (i is a positive integer) and the trace parameter TPi as shown in FIG. 1B are output to the data line DL. The trace bit is input to the interrupt generation circuit 71 in the @IA diagram,
Trace parameters are trace parameter latch circuit 7
2 is input. And the trace request bit is @1”
At this time, the trace request interrupt signal TI is output from the interrupt generation circuit 71 to the line LT at a predetermined timing, and the trace parameters are latched by the latch circuit 72. When an interrupt signal is input to the processor 1, the processor 1 reads a prespecified interrupt process, that is, a trace parameter from the latch circuit 72, and executes the trace process specified by this parameter.

Regarding the interrupt processing operation, with reference to FIGS. 2 and 3,
Let me explain in more detail. Note that FIG. 2 is a reference diagram showing an example of a program executed by the processor, and FIG. 3 is an explanatory diagram for explaining an interrupt processing operation.

Now, as shown in Fig. 2, there are instructions Oo to On+2 to be executed sequentially by the processor IK, and each instruction Om is stored in the memory 3.
, the processor 1 stores the contents of the memory at the address Am, that is, the instruction O
It takes in the code of m and operates according to its instructions. At this point, the trace request bit at address An+1 is set to ``1'' in advance, and the value of the trace parameter is set to a predetermined value, for example 2''. Assuming that memory 3 consists of 8 bits, the range of trace parameter values for address Am is 'OO' to '3F' in hexadecimal, that is, 6
It is possible to set trace parameters in four ways. In this way, the processor sequentially executes the instructions, and when the instruction On+1 is now executed, a trace request interrupt is generated in the processor as described above. As a result, the processor performs a predetermined interrupt processing routine, that is, monitor processing such as saving registers and masking interrupts, and then reads trace parameters from the latch circuit 72 of FIG. 1A and discriminates them. In the above example, the trace parameter was set to 2'', so the trace process corresponding to this value is executed.The process for trace parameter 2 is, for example, after executing the instruction On+t, as shown in Figure 3. Program counter PC, status register S, memory contents, etc.
0 device or RAM. As a result, i1
0 The result after executing the following instructions can be known from the output of the device and the RAM data.

Note that, as described above, the programs for these trace processes are stored in advance in the RAM 4 or the like before starting the trace.

In addition, as mentioned above, the trace parameters are set to 00''~'''
If you set the trace processing corresponding to each bit of 6 bits instead of "3F", it becomes possible to execute multiple trace processing.In addition, in the above, the program is stored in ROM. However, it goes without saying that exactly the same results can be obtained even if the program is in RAM.

〔Effect of the invention〕

According to this invention, by setting the trace request bit and trace parameters in the parity memory,
It is possible to trace data anywhere in the program without making any changes to the main program. Furthermore, when actually investigating the cause of a failure, it is extremely easy to change the trace location, and by storing the data sampling program in RAM, the data to be sampled can be easily changed on site. This provides the advantage that it is possible to know the cause of a failure extremely efficiently.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing an embodiment of the present invention, FIG. 1A is a block diagram showing a specific example of the trace control circuit in FIG. 1, and FIG. 1B is a specific example of the parity data storage memory shown in FIG. FIG. 2 is a reference diagram for explaining the relationship between the execution program, trace request pits, and trace parameters; FIG. 3 is an explanatory diagram for explaining the interrupt processing operation;
FIG. 4 is a block diagram showing a general data processing system.
OM for program storage, 3... OM for storing parity data, 4. Song/RAM, 5.. Song memory control circuit, 6... Parity check circuit, 7...
... Trace control circuit, 71 ... Interrupt generation circuit, 72 ... Trace parameter latch circuit,
AB...address bus, DB...data bus, CL...memory control signal line, MC...
・Memory control signal, LP, LT... Interrupt signal line, P■... Song parity error interrupt signal, TI...
・Trace interrupt signal, DL・・Song data line, 几T・
...Trace parameter successive signal. Agent: Patent Attorney Akio Namiki Agent: Patent Attorney Kiyohaku Matsuzaki! ■ Tomi IA Figure 1B Officer 2 Figure 3 Figure 1 ----J Wi4 Figure

Claims (1)

[Claims] a processor, a first memory that stores trace request bits and trace parameters corresponding to each program executed by the processor, and a second memory that stores a tracing program for tracing each program; a trace control circuit that refers to a trace request bit read from a first memory by the processor, temporarily stores trace parameters according to the contents thereof, and generates an interrupt signal to the processor; A program characterized in that when an interrupt signal is received via the trace control circuit, a trace program designated by a trace parameter temporarily stored therein is read out from the second memory and executed. Trace method.