JPH0683987A - Microcomputer - Google Patents

Abstract

PURPOSE:To easily analyze a fault of a hardware. CONSTITUTION:The microcomputer is provided with a data bus 1, a hardware such as a TEMP (temporary register) 2, etc., a data writing means 3 for writing data from the data bus 1 in the TEMP 2, and a data reading-out means 4 for reading out the data from the TEMP 2 to the data bus 1. First of all, first data is written in the TEMP 2, and a check for reading out its contents to the data bus 1 is executed. Subsequently, second data obtained by inverting first data is written in the TEMP 2, and a check for reading out its contents to the data bus 1 is executed. By inverting such data, write and read-out are checked by both of '0' and '1', and the hardware is analyzed.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a microcomputer, and more particularly to a microcomputer containing a micro program.

[0002]

2. Description of the Related Art A conventional microcomputer includes a program counter, various arithmetic registers, temporary registers and the like. This temporary register (hereinafter referred to as TEMP) has a function of temporarily saving addresses and data during instruction processing.
When the MP has a defect, the following cause analysis is performed.

FIGS. 6 (a) and 6 (b) are a flow diagram of a register content exchange instruction and a hardware configuration operated by this flow, respectively, for explaining an example of the related art.

As shown in FIG. 6A, since the data is previously set in the register 1 and the register 2 in this case, the contents of the register 1 are read in the read step S28. Next, in step S29, the contents of register 1 are set to TE
The contents of register 2 are read out while writing to MP. Next, in a write step S30, the contents of register 2 are written in register 1. Further, writing step S3
At 1, the contents of TEMP are written to register 2.

Next, as shown in FIG. 6B, the hardware operated in the above-described flow is the bus 1 to which data is transferred, and the register RAM 23 connected to this bus 1.
And TEMP2, and means 24 for reading data from the RAM address generating means 22 and the register RAM 23. The means 24 for reading data from the register RAM 23 reads information in the register RAM 23 and switches the timing. 25 is a register RAM 23
Data to be written in, data 26 in the register RAM 23 whose timing is switched, data 27 to be written in TEMP2, data 28 to be read from TEMP2 to the data bus 1.

Further, the operation will be described using the above-mentioned flow and hardware. First, when the contents of the register 1 are read in step S28, the RAM address generation means 2
At 2, a RAM address is generated. The contents of the register 1 are output from the register RAM 23 by this RAM address.

Next, when the operation of writing the contents of register 1 into TEMP is performed in step S29, register R
The information (register 1) 26 whose timing is recut by the means 24 for reading data from the AM 23 is output to the data bus 1. Then, the information (register 1) 27 of the data bus 1 is written to TEMP2. At the same time, by the operation of reading the contents of the register 2 in step S29, the contents of the register 2 are similarly output to the reading means 24.

Next, when the operation of writing the contents of the register 2 to the register 1 in step S30 is performed, the information (register 2) 26 whose timing has been recut by the means 24 for reading the data from the register RAM 23 is transferred to the data bus 1. Is output. At the same time, the RAM is generated by the RAM address generation means 22, and the information (register 2) 25 of the data bus 1 is written in the register RAM 23 (register 1) designated by the RAM address.

Further, by the operation of writing the contents of TEMP2 to the register 2 in step S31, TEMP2
Information (register 1) 28 written in the data bus 1
Is output to. Similarly, the information (register 1) 25 of the data bus 1 is written in the register RAM (register 2) 23.

Therefore, if there is a problem in writing to TEMP2, it can be found in step S29, and T
If there is a problem in reading from the EMP2, it can be found in step S31.

[0011]

In testing the hardware, the above-described conventional microcomputer is realized by an instruction to write data in the register in advance and an instruction to read the execution result in addition to the above-mentioned instruction. . In other words, even when testing one piece of hardware, its function is confirmed by executing many instructions in combination. Therefore, the number of steps of the microprogram activated by many instructions is further increased, and the internal hardware and control signals operated by the microorder issued thereby are further increased. Therefore,
If a part of the internal hardware has a defect, or if a large number of defects occur, these are not executed normally, which makes analysis difficult.

An object of the present invention is to provide a microcomputer capable of easily performing such hardware failure analysis.

[0013]

The microcomputer of the present invention is, in a microcomputer having a built-in microprogram, hardware such as temporary register for temporarily storing various data, and writing means for writing data to the hardware. And a reading means for reading data from the hardware, and the data writing means and the data using a dedicated microprogram issued by a dedicated instruction code having data required for the writing means. The reading means are sequentially operated.

[0014]

[Function] Separately from the microprogram that makes the instruction specifications used by the user function, a dedicated microprogram that checks the individual hardware contained in the microcomputer used for development, design, and verification by the developer Equipped with. This dedicated microprogram can significantly reduce the number of steps required for hardware failure analysis.

[0015]

Embodiments of the present invention will now be described with reference to the drawings. 1 (a) and 1 (b) are respectively a flow chart of a register content exchange instruction and a diagram showing hardware operated by this flow for explaining the first embodiment of the present invention. As shown in FIG. 1A, the exchange instruction flow includes a step S1 of writing the first data to the TEMP, a step S2 of reading the contents of the TEMP to the data bus, and a second data which is the inversion of the first data. To T
It comprises a step S3 of writing to the EMP and a step S4 of reading the contents of TEMP onto the data bus. Further, as shown in FIG. 1B, the hardware operable in the above-described flow is a data bus 1 for transferring data,
TEMP2 for storing data, data writing means 3 for writing data from the data bus 1 to TEMP2,
The data read means 4 is provided for reading data from the TEMP 2 on the data bus 1.

FIG. 2 is a block diagram of the instruction code in FIG. As shown in FIG. 2, in executing the dedicated microprogram, an instruction code is given from the outside. This instruction code is the entry instruction code 5 that determines the entry address of the dedicated microprogram, and the TEM
The first data 6 written in P2 and the first data 6 written in TEMP2 are inverted second data 7
Includes and.

Next, the operation of the microcomputer will be described with reference to FIGS. 1 (a), 1 (b) and 2. When the instruction is executed by giving the first data 6 and the second data 7 to the instruction code shown in FIG. 2, step S1 shown in FIG.
A microprogram having the flow of ~ S4 is executed. First, in step S1, the first data 6 is changed to TEMP2.
By the operation of writing to, the first data 6 of the instruction code given from the outside is transmitted to the data bus 1 and written to the TEMP 2 by the data writing means 3.
Next, in step S2, the contents of TEMP2 are transferred to the data bus 1
The first data 6 written in TEMP2 is read out to the data bus 1 by the data reading means 4 by the operation of reading out to. Next, by the operation of writing the second data 7 to TEMP2 in step S3, the second data 7 of the instruction code given from the outside is sent to the data bus 1 and similarly written to TEMP2. Furthermore, the operation of reading the contents of TEMP2 to the data bus 1 in step S4 causes the second data written in TEMP2 to be read.
Data 7 in the same manner is read out to the data bus 1.

By the above operation, the write check and the read check, which are the functions of TEMP2, can be verified independently of other hardware. here,
The inversion of the first data 6 and the second data 7 is caused by checking the writing and reading with two types of information "0" and "1", which is "0".
This is to prevent the omission of verification when there is a case where it is normal in either case and "1" and abnormal in either case.

In this embodiment, the special microprogram for checking the temporary has been described as an example, but the special microprogram for checking the program counter, the loop counter, the program status word, the incrementer, and the arithmetic unit is also the same. Will be described in the second embodiment below.

FIGS. 3 (a) and 3 (b) are a data exchange flow diagram and a configuration diagram of an instruction code in this flow, respectively, for explaining the second embodiment of the present invention. Figure 3
As shown in (a), this embodiment uses TEMP, a program counter (hereinafter referred to as PC), a loop counter (hereinafter referred to as L).
In checking the writing and reading of the program status (hereinafter referred to as PSW) and the program status (hereinafter referred to as PSW), first, in step S5, a check is performed to write the first data in the TEMP. Then, in the second step S6, the second is stored in the PC that holds the address of the program to be executed next.
Check to write the data. Further, in the third step S7, a check is performed to write the third data to the loop counter LC when the microprogram is repeatedly processed. Next, in the fourth step S8, a check is made to write the fourth data to the PSW composed of various flags set or reset by the execution of the instruction.
Then, in a fifth step S9, a check is performed to read the contents of PSW to the data bus.

Next, in the sixth step S10, it is checked whether the fifth data, which is the inverted fourth data, is written in the PSW. Next, in the seventh step S11, a check is made to read the contents of LC to the data bus. Subsequently, in the eighth step S12, a check is made to write the sixth data, which is the inverted third data, to the LC. Further, in the ninth step S13, a check is made to read out the contents of the PC to the data bus. Next, in the tenth step S14, a check is performed to write the seventh data, which is the inverted second data, to the PC. In addition, in the eleventh step S15, a check is made to read out the contents of TEMP to the data bus. Next, in the twelfth step S16, the eighth data obtained by inverting the first data is set to T
Check to write to EMP. Furthermore, in the thirteenth step S17, a check is made to read the contents of TEMP onto the data bus.

As shown in FIG. 3B, the instruction code is an instruction code for executing the dedicated microprogram shown in FIG.
And the first to fourth data 9 to 12 and these fourth to first data
And the fifth to eighth data 13 to 16 which are the reverse of the above data. As for the hardware that can be operated by the dedicated microprogram, FIG. 1B is adopted.

FIGS. 4A and 4B are respectively shown in FIG.
It is the check flow figure of the incrementer in (a), (b) and the block diagram of the instruction code. As shown in FIG. 4A, the incrementer is hardware that automatically increases the value of the PC to "+1" by reading the instruction code, and checks whether this incrementer is operating normally. In doing so, first, in the first step S21, a check is made to write data to the PC. Then the second
The value of the PC is incremented by "+1" by reading 1 byte of the instruction code in step S22. Further, by reading the contents of the PC to the data bus 1 in the third step S23, it is checked whether or not the contents of the PC are "+1". Thus, the incrementer is checked.

As shown in FIG. 4B, this instruction code is an instruction code for executing the dedicated microprogram of FIG. 4A, and the instruction code for entry 17
And the first data 18 are included. The configuration is shown in FIG.
It is the same as the instruction code of.

FIGS. 5A and 5B are respectively shown in FIG.
3A and 3B are a check flow diagram of the arithmetic unit in FIGS. 1A and 1B and a configuration diagram of an instruction code in the flow. Figure 5
As shown in (a), in checking whether or not the arithmetic unit normally operates and the arithmetic result is normal, data is first input to the arithmetic unit in the first step S24.
Next, in the second step S25, the data is input to the arithmetic unit. As a result, in the third step S26, the processing is performed by the arithmetic unit. Further, in the fourth step S27, the calculation result is read out to the data bus 1. By the above steps, it is checked whether or not the arithmetic processing is normally performed.

Further, as shown in FIG.
The instruction code for executing the dedicated microprogram of (a) includes the entry instruction code 19, the first data 20 and the second data 21, and its configuration is shown in FIG.
Is the same as.

[0027]

As described above, the microcomputer of the present invention operates the writing means for writing the data of the built-in hardware such as temporary storage, the reading means for reading the data, and the writing means. By providing a dedicated microprogram, it is possible to verify the individual hardware built in,
This has the effect of significantly reducing the man-hours required for failure analysis.

[Brief description of drawings]

FIG. 1 is a diagram showing a flow of a register content exchange instruction for explaining a first embodiment of the present invention and hardware operated by this flow.

FIG. 2 is a configuration diagram of an instruction code in FIG.

FIG. 3 is a diagram showing a data exchange flow for explaining a second embodiment of the present invention and a configuration of an instruction code in this flow.

FIG. 4 is a diagram showing a check flow of the incrementer in FIG. 3 and a configuration of an instruction code in the flow.

5 is a diagram showing a check flow of the arithmetic unit in FIG. 3 and a configuration of an instruction code in the flow.

FIG. 6 is a diagram showing a flow of a register content exchange instruction and a hardware operated by the flow for explaining an example of the related art.

[Explanation of symbols]

 1 Data Bus 2 Temporary Register (TEMP) 3 Data Writing Means 4 Data Reading Means 5, 8, 17, 19 Entry Instruction Codes 6, 7, 9-16, 18, 20, 21 Data

Claims (1)

[Claims] 1. A microcomputer including a micro program, wherein hardware such as a temporary register for temporarily storing various data, writing means for writing data to the hardware, and reading of data from the hardware are performed. Read means and sequentially operate the data writing means and the data reading means by using a dedicated microprogram issued by a dedicated instruction code having data necessary for the writing means. Microcomputer to do.