JPS61203680A - Mis semiconductor device - Google Patents

Mis semiconductor device

Info

Publication number
JPS61203680A
JPS61203680A JP4431985A JP4431985A JPS61203680A JP S61203680 A JPS61203680 A JP S61203680A JP 4431985 A JP4431985 A JP 4431985A JP 4431985 A JP4431985 A JP 4431985A JP S61203680 A JPS61203680 A JP S61203680A
Authority
JP
Japan
Prior art keywords
region
input terminal
type semiconductor
transistor
mis
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP4431985A
Other languages
Japanese (ja)
Other versions
JPH0440868B2 (en
Inventor
Kazuhito Misu
三須　一仁
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP4431985A priority Critical patent/JPS61203680A/en
Publication of JPS61203680A publication Critical patent/JPS61203680A/en
Publication of JPH0440868B2 publication Critical patent/JPH0440868B2/ja
Granted legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/1025—Channel region of field-effect devices
    • H01L29/1029—Channel region of field-effect devices of field-effect transistors
    • H01L29/1033—Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure

Abstract

PURPOSE:To obtain the MIS semiconductor device which is proof against an input surge voltage by apparently enhancing the reverse conductive type semiconductor layer resistance from an input terminal to the region where a protective MIS transistor is energized firstly apparently. CONSTITUTION:A distance between the drain region consisting of a reverse conductive type semiconductor region and the source region consisting of a reverse conductive type semiconductor region 19 present under an input terminal 11 is so contrived that a channel length L' in a part C is gradually reduced from the edge of the input terminal 11 toward the internal part by inclining a part of the source region with respect to the drain region by a predetermined angle. When a surge voltage is applied to the input terminal 11, the region where a protective MIS transistor is energized firstly is the region of channel length L of a low threshold voltage. The surge voltage is divided into a resistance R1' and an on-state resistance of the protective MIS transistor and a voltage applied to a gate oxide film of the input transistor is reduced.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明は、ＭＩＳトランジスタ（絶縁ゲート型電界効果
トランジスタ）からなるＭＩＳ型半導体装置の入力保護
回路を改良したＭＩＳ型半導体装置に関する。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a MIS type semiconductor device having an improved input protection circuit of a MIS type semiconductor device including MIS transistors (insulated gate field effect transistors).

〔従来の技術〕[Conventional technology]

上記入力保護回路の一般的な例を第３図に、そのマスク
パターンを第４図に示ｔ。A general example of the above input protection circuit is shown in FIG. 3, and its mask pattern is shown in FIG.

第３図において、仁の従来例の入力保護回路は、入力ト
ランジスタＴＦＬｏのゲートと入力端子１１間に直列接
続された保護抵抗”　１　＋　”　２と、ゲートを入力
端子１１にドレインを節点人にソースをｌｌ接地電位に
それぞれ接続された保護ＭＩＳ）ランジスタＴＲ，とか
ら成っている。なおｒはＴａ１のオン抵抗である。In FIG. 3, Jin's conventional input protection circuit includes a protection resistor "1 + "2 connected in series between the gate of the input transistor TFLo and the input terminal 11, and the gate is connected to the input terminal 11 and the drain is connected to the node. It consists of a protection MIS) transistor TR whose sources are respectively connected to the ground potential. Note that r is the on-resistance of Ta1.

そして実際には第４図に示すように、保護抵抗ａ、、ａ
、は一端が入力端１１と半導体基板とは逆導電型の入力
端子取出し領域１８と接続され、他端がコンタクト１６
を介して入を配線にて入力トランジスタＴＦＬ０のゲー
トに接続された逆導電型半導体領域１２ａ及び１２ｂと
からなっている。In reality, as shown in Fig. 4, the protective resistances a, , a
, has one end connected to the input terminal 11 and the input terminal extraction region 18 of the opposite conductivity type to the semiconductor substrate, and the other end to the contact 16.
It consists of opposite conductivity type semiconductor regions 12a and 12b connected to the gate of the input transistor TFL0 via wiring.

そして逆導電型半導体領域１２ｂの一部分は７Ｖｌ！か
らなる入力端子１１の下部になるように設けられる。一
方、保護ＭＩＳトランジスタは、前記入力端１１下の逆
導電型半導体領域をドレイン領域。A portion of the opposite conductivity type semiconductor region 12b is 7Vl! It is provided below the input terminal 11 consisting of. On the other hand, the protection MIS transistor uses the opposite conductivity type semiconductor region below the input terminal 11 as a drain region.

入力端子１１をゲート電極として保＠ＭＩＳ）ランジス
タＴＲ１のソース領域を構成する通導′ｆｌＬ型半導体
領域１９とからなるいわゆる寄生ＭＩＳ）ランジスタを
用いる。そしてこの逆導電型半導体領域１９はコンタク
ト１６を介してＡｔ配線１７にさらにコンタクト１５を
介して入力電極１１に接続される。ここで、逆導電型半
導体領域は不純物拡散層やポリシリコン層で形成される
。A so-called parasitic MIS transistor is used in which the input terminal 11 is used as a gate electrode and a conductive 'flL type semiconductor region 19 constitutes the source region of the MIS transistor TR1. This opposite conductivity type semiconductor region 19 is connected to the At wiring 17 via a contact 16 and further to the input electrode 11 via a contact 15. Here, the opposite conductivity type semiconductor region is formed of an impurity diffusion layer or a polysilicon layer.

第４図において、入力端子１１に印加されたサージ電圧
は、抵抗ａ１を形成する逆導電型半導体領域１２ａを通
シ、保護ＭＩ８）ランジスタＴＲ。In FIG. 4, the surge voltage applied to the input terminal 11 passes through the opposite conductivity type semiconductor region 12a forming the resistor a1 and protects the resistor MI8) transistor TR.

のドレインに加わ、９．ＴＲ１は既に導通状態になって
いるために、節点への電位は接地電位（ＯＶ）に放電さ
れる。9. Since TR1 is already in a conductive state, the potential to the node is discharged to the ground potential (OV).

〔発明が解決しようとする問題点〕[Problem that the invention seeks to solve]

しかしながら、実際には保ｇＭＩ８トランジスタのオン
抵抗ｒが存在するため、印加された節点Ａの電位は抵抗
Ｒ１とｒで抵抗分圧される。従って、逆導電型半導体領
域１２ａによる抵抗＆１の抵抗値が小さく、保ｆｉＭＩ
８トランジスダｍｌのドレインに加わる電圧が大きい場
合、つまシ節点人の電位が大きい場合、入力トランジス
タＴＲｏのゲート電圧（節点Ｂの電位）が大きく、入力
トランジスタＴａｏのゲート酸化膜の破壊などを引き起
こし、信頼性上問題となっていた。又、サージ耐圧を上
げるために保護抵抗のパターンを変えることは、寸法上
制限を受け、自由に変更できないという問題があった。However, in reality, since the on-resistance r of the GMI8 transistor exists, the applied potential at the node A is divided by the resistors R1 and r. Therefore, the resistance value of resistance &1 due to the opposite conductivity type semiconductor region 12a is small, and the
8 If the voltage applied to the drain of transistor ml is large, if the potential at the node B is large, the gate voltage of input transistor TRo (potential at node B) will be large, causing destruction of the gate oxide film of input transistor Tao, etc. There was a problem with reliability. Further, changing the pattern of the protective resistor in order to increase the surge withstand voltage has a problem in that it cannot be changed freely due to size limitations.

本発明の目的は、上記問題点を解消することによシ、サ
ージ耐圧に強いＭＩａ型半導体装置を提供するととＫあ
る。An object of the present invention is to provide an MIa type semiconductor device that is strong against surge voltage by solving the above-mentioned problems.

〔問題点を解決するための手段〕[Means for solving problems]

本発明のＭＩＳ型半導体装置は、一導電型の半導体基板
上に形成されたＭＩａ型半導体装置において、一端が入
力端子に接続されＩ他端が前記ＭＩｓ型半導体装置の入
力トランジスタのゲー）Ｋ接続されかつその一部分が前
記入力端子下になるように設けられ保膿抵抗を構成する
第１の逆導電型半導体領域と、前記入力端子下の前記第
１の逆導電型半導体領域をドレイン領域前記入力端子を
ゲート電極として保護ＭＩＳトランジスタのソース領域
を構成する第２の逆導電型半導体領域とを含み、前記保
護ＭＩＳ）ランジスタのソース領域とドレイン領域の間
隔が一部分において前記入力端子の端部よ＃）本内部の
方が漸次小さくなっていることからなっている。The MIS type semiconductor device of the present invention is an MIa type semiconductor device formed on a semiconductor substrate of one conductivity type, in which one end is connected to an input terminal and the other end is connected to the gate of the input transistor of the MIs type semiconductor device. a first opposite conductivity type semiconductor region which is provided so as to be partially under the input terminal and constitutes a purulent storage resistor, and a first opposite conductivity type semiconductor region under the input terminal is connected to the drain region of the input terminal a second opposite conductivity type semiconductor region constituting a source region of a protection MIS transistor with the terminal as a gate electrode; ) The interior of the book gradually becomes smaller.

〔実施例〕〔Example〕

以下、本発明の実施例について図面を参照して説明する
。Embodiments of the present invention will be described below with reference to the drawings.

第１図は本発明の一実施例の保護回路のマスクパターン
を示す平面図で、第４図に示す従来例に対して本発明を
適用したものである。FIG. 1 is a plan view showing a mask pattern of a protection circuit according to an embodiment of the present invention, in which the present invention is applied to the conventional example shown in FIG.

本実施例は、第４図に示す従来例のマスクパターンにお
いては、入力端子１１下にある逆導電型半導体領域から
なるドレイン領域と逆導電型半導体領域１９からなるソ
ース領域との間隔、すなわち保￥ｋＭＩ８）ランジスタ
のゲート長りが一定なのに対し、第１図に示すように、
ドレイン領域に対してソース領域の一部を一定の角度で
傾斜させ、Ｃ部分において、チャネル長Ｌ′を入力端子
１１の端部よりも内部の方が漸次小さくなるようにした
ものである。In this embodiment, in the conventional mask pattern shown in FIG. ¥kMI8) While the transistor gate length is constant, as shown in Figure 1,
A part of the source region is inclined at a constant angle with respect to the drain region, and in the C portion, the channel length L' is made gradually smaller inside the input terminal 11 than at the end thereof.

ところで、ここで使用している保＠ＭＩＳトランジスタ
についてチャネル長りとしきい値電圧Ｖ！の関係の一例
を示すと第２図のように、チャネルＬが大になると共に
しきい値電圧Ｖ！は急激に大きくなる。By the way, the channel length and threshold voltage V of the MIS transistor used here! As shown in FIG. 2, as the channel L increases, the threshold voltage V! increases rapidly.

従って、第１図の実施例においては、図のＣ部分におい
てしきい値電圧が高くなる。今この状態において、入力
端子１１にサージ電圧が印加された場合、保護ＭＩＳト
ランジスタの最初に導通する領域はしきい値電圧の低い
チャネル長りの領域であシ、第３図に示す等価回路にお
ける節点人の位置が、実質的に第１図に示す節点Ａ′ま
で延びることになる。Therefore, in the embodiment shown in FIG. 1, the threshold voltage becomes high at portion C in the figure. In this state, when a surge voltage is applied to the input terminal 11, the first region of the protection MIS transistor that becomes conductive is the channel length region with a low threshold voltage. The position of the node person extends substantially to node A' shown in FIG.

この結果、逆２４寛型半導体領域２　ａ／の抵抗をル１
′、逆導電型半導体領域２　ｂ　／の抵抗を［（、、／
とすると、第４図の従来例におけるそれぞれの抵抗Ｒ，
，，Ｒ，との関係は、 ａｔ　＜Ｒｔ’、　ａｔ　＞”ａ’ｐ　Ｒ１１＋　１．
＝［（、、’＋　ａ、’となる。As a result, the resistance of the inverted 24-circular semiconductor region 2a/
′, the resistance of the opposite conductivity type semiconductor region 2 b / is [(,, /
Then, the respective resistances R, in the conventional example shown in FIG.
,,R, are as follows: at <Rt', at >"a'p R11+ 1.
= [(,,'+ a,'.

従って、本実施例によると、入力端子１１にサージ電圧
が印加された場合、サージ電圧は抵抗Ｒｌｌと保護ＭＩ
Ｓトランジスタのオン抵抗ｒとに分圧され、入力トラン
ジスタのゲート酸化膜にかかる電圧を緩和する。Therefore, according to this embodiment, when a surge voltage is applied to the input terminal 11, the surge voltage is applied to the resistor Rll and the protection MI
The voltage is divided by the on-resistance r of the S transistor, and the voltage applied to the gate oxide film of the input transistor is relaxed.

かくして、本実施例によると、保護抵抗の全体の大きさ
を従来例と変えることなしにサージ耐圧を上げることで
きる。Thus, according to this embodiment, the surge withstand voltage can be increased without changing the overall size of the protective resistor from the conventional example.

〔発明の効果〕〔Effect of the invention〕

以上、詳細説明したとおシ、本発明によれば、寄生ＭＩ
Ｓ）ランジスタからなる保護ＭＩＳトランジスタのドレ
イン領域である逆導電型半導体領域に対してソース領域
である逆導電型半導体領域の間隔を一部分において、入
力端子の端部から内部に向って漸次小さくして、保護Ｍ
ＩＳ）ランジスタのチャネル長を太きくシ、そのチャネ
ル長を大きくした領域のしきいＩ［ｔ　’＃ｉ、圧Ｖ丁
は上昇するため、入力端子から保護ＭＩ８トランジスタ
の最初に導通する領域までの逆導電型半導体層抵抗を（
入力端子と入力トランジスタ間に存在する逆導電型半導
体層抵抗を一定として）見かけ上増大することができる
。従って、入力端子にサージ電圧が加わった場合、サー
ジ電圧は入力端子から保護ＭＩＳトランジスタの最初に
導通する領域までの逆２４電型半導体領域の抵抗と保釉
ＭＩＳ）？ンジスタのオン抵抗とに分圧され、入力トラ
ンジスタのゲート酸化膜にかかる電圧を緩和し、入力サ
ージ耐圧に強いＭＩＳｉ半導体装置を得ることができる
。As described above in detail, according to the present invention, parasitic MI
S) The distance between the opposite conductivity type semiconductor region which is the drain region and the opposite conductivity type semiconductor region which is the source region of the protective MIS transistor consisting of a transistor is partially reduced from the end of the input terminal toward the inside. , protection M
IS) Increase the channel length of the transistor, and the threshold I[t'#i and voltage Vd in the region where the channel length is increased increases, so the distance from the input terminal to the first conductive region of the protection MI8 transistor increases. The opposite conductivity type semiconductor layer resistance (
(assuming that the resistance of the opposite conductivity type semiconductor layer existing between the input terminal and the input transistor is constant) can be increased in appearance. Therefore, when a surge voltage is applied to the input terminal, the surge voltage is the resistance of the inverted 24 voltage semiconductor region from the input terminal to the first conductive region of the protection MIS transistor (MIS)? The voltage is divided between the on-resistance of the transistor and the voltage applied to the gate oxide film of the input transistor, thereby making it possible to obtain a MISi semiconductor device that is resistant to input surge voltage.

【図面の簡単な説明】[Brief explanation of the drawing]

第１図は本発明の一実施例の入力保護回路のマスクパタ
ーンを示す平面図、第２図は保＠ＭＩ８トランジスタの
チャネル長としきい値電圧の関係を示す特性図、第３図
は一従来例の入力保護回路を示す回路図、第４図はその
マスクパターンを示す平面図である。 １１・・・・・・入力端子、１２ａ、１２ａ’、１２ｂ
、１２ｂ’・・・・・・逆導電型半導体領域、１３・・
・・・・埋込みコンタクト、１４・・・・・・ポリシリ
コン層、１５，１６・・・・・・コンタクト、１７・・
・・・・Ｉｔ配線、１８・・・・・・入力端Ｒ＋、、Ｒ
１，’・・・・・・保護抵抗、ＴＲＯ・・・・・・入力
トランジスタ、Ｔａｌ・・・・・・保＠ＭＩｓ）ランジ
スタ、ｒ・・・・・・保護ＭＩＳ）ランジスタのオン抵
抗。 ｌｌ−入り端子 ｌｚａ　７ｔｚｂ電逆導電至早導イ本列３に１５、　／
乙　：　コ）タクト ／７　：　　ＡＪ丙乙線 １８：入ｆＪ塙壬取忠り考頁玖 第　１　図 ＋マネル長Ｌ（ｐｍ） 第２図 第３図 １に入υ塙子 ／２ａ、／２ｂ：逆導電型半導イ本祁城１５．１６　　
：　コンタクト １７：Ａｌｌ内線 線８　：　入乃瑞子取出１４頂３＾゛ １９二　　逆導電型半導イ本碩滅゛ 第４図　　　′″　′。Fig. 1 is a plan view showing a mask pattern of an input protection circuit according to an embodiment of the present invention, Fig. 2 is a characteristic diagram showing the relationship between channel length and threshold voltage of a protection @MI8 transistor, and Fig. 3 is a conventional one. FIG. 4 is a circuit diagram showing an example input protection circuit, and FIG. 4 is a plan view showing its mask pattern. 11...Input terminal, 12a, 12a', 12b
, 12b'... Opposite conductivity type semiconductor region, 13...
...Buried contact, 14...Polysilicon layer, 15, 16...Contact, 17...
...It wiring, 18...Input terminal R+,,R
1,'... Protection resistance, TRO... Input transistor, Tal... Protection@MIs) transistor, r... Protection MIS) On-resistance of transistor. 15, /
Otsu: Ko) Tact/7: AJ Hei Otsu Line 18: Entering fJ Hanawa Mitori Tadashiko Page 1 Figure + Manel Length L (pm) Figure 2 Figure 3 Figure 1 Entering υ Hanako/2a,/ 2b: Reverse conductivity type semiconductor 15.16
: Contact 17: All extension line 8 : Iruno Mizuko extraction 14 top 3 ＾゛ 192 Reverse conductivity type semiconductor main destruction ゛ Fig. 4 ′″ ′.

Claims (1)

【特許請求の範囲】[Claims] （１）一導電型の半導体基板上に形成されたＭＩＳ型半
導体装置において、一端が入力端子に接続され他端が前
記ＭＩＳ型半導体装置の入力トランジスタのゲートに接
続されかつその一部分が前記入力端子下になるように設
けられ保護抵抗を構成する第１の逆導電型半導体領域と
、前記入力端子下の前記第１の逆導電型半導体領域をド
レイン領域前記入力端子をゲート電極として保護ＭＩＳ
トランジスタのソース領域を構成する第２の逆導電型半
導体領域とを含み、前記保護ＭＩＳトランジスタのソー
ス領域とドレイン領域の間隔が一部分において前記入力
端子の端部よりも内部の方が漸次小さくなっていること
を特徴とするＭＩＳ型半導体装置。(1) In a MIS type semiconductor device formed on a semiconductor substrate of one conductivity type, one end is connected to an input terminal, the other end is connected to the gate of an input transistor of the MIS type semiconductor device, and a portion thereof is connected to the input terminal. A first reverse conductivity type semiconductor region provided below and constituting a protection resistor, and a protection MIS using the first reverse conductivity type semiconductor region below the input terminal as a drain region and the input terminal as a gate electrode.
a second opposite conductivity type semiconductor region constituting a source region of the transistor, and a distance between the source region and the drain region of the protection MIS transistor is gradually smaller at the inside than at the end of the input terminal. An MIS type semiconductor device characterized by:
JP4431985A 1985-03-06 1985-03-06 Mis semiconductor device Granted JPS61203680A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP4431985A JPS61203680A (en) 1985-03-06 1985-03-06 Mis semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP4431985A JPS61203680A (en) 1985-03-06 1985-03-06 Mis semiconductor device

Publications (2)

Publication Number Publication Date
JPS61203680A true JPS61203680A (en) 1986-09-09
JPH0440868B2 JPH0440868B2 (en) 1992-07-06

Family

ID=12688163

Family Applications (1)

Application Number Title Priority Date Filing Date
JP4431985A Granted JPS61203680A (en) 1985-03-06 1985-03-06 Mis semiconductor device

Country Status (1)

Country Link
JP (1) JPS61203680A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH02312277A (en) * 1989-05-26 1990-12-27 Fujitsu Ltd Semiconductor input protective device
US8672098B2 (en) 2008-10-20 2014-03-18 Fujitec Co., Ltd. Elevator safety device with foreign matter detection using a light beam

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH02312277A (en) * 1989-05-26 1990-12-27 Fujitsu Ltd Semiconductor input protective device
US8672098B2 (en) 2008-10-20 2014-03-18 Fujitec Co., Ltd. Elevator safety device with foreign matter detection using a light beam

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