JPS61203376U - - Google Patents
Info
- Publication number
- JPS61203376U JPS61203376U JP8795085U JP8795085U JPS61203376U JP S61203376 U JPS61203376 U JP S61203376U JP 8795085 U JP8795085 U JP 8795085U JP 8795085 U JP8795085 U JP 8795085U JP S61203376 U JPS61203376 U JP S61203376U
- Authority
- JP
- Japan
- Prior art keywords
- signal
- frequency
- output terminals
- shift register
- modulated signal
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 230000004044 response Effects 0.000 claims 1
Description
第1図は、この考案の実施例を示す。 FIG. 1 shows an embodiment of this invention.
Claims (1)
から供給されるパレス列に応答して順次これらの
データを送出する記憶器と、 該記憶器からの信号に基づいて周波数変調され
た信号を生成する信号発生器と、 この周波数変調された信号を発射する送波器と
、 上記周波数変調された信号を受信する受波器と 該受波器からの出力信号を記憶しその複数の出
力端子に記憶される信号を出力するシフトレジス
タと、 上記周波数変調された信号と同じように周波数
変調された信号を上記シフトレジスタの出力端子
に対応する複数の出力端子に出力する基準信号発
生器と、 上記シフトレジスタの複数の出力端子に送出さ
れる信号と、上記基準信号発生器の上記シフトレ
ジスタの出力端子に対応する複数の出力端子に送
出される信号とを互いに加算し、更に各出力端子
毎に得られた値を互いに加算する加算器を具備す
ることを特徴とする送受信装置。[Claims for Utility Model Registration] A pulse generator that sends out a pulse train; a memory that stores predetermined data in advance and sequentially sends out the data in response to the pulse train supplied from the pulse generator; a signal generator that generates a frequency-modulated signal based on the signal from the memory; a transmitter that emits the frequency-modulated signal; and a receiver that receives the frequency-modulated signal. A shift register that stores the output signal from the receiver and outputs the signal to be stored at its plurality of output terminals, and a frequency-modulated signal similar to the above-mentioned frequency-modulated signal to the output terminal of the shift register. a reference signal generator that outputs to a plurality of corresponding output terminals, a signal that is sent to a plurality of output terminals of the shift register, and a plurality of output terminals of the reference signal generator that correspond to the output terminals of the shift register. 1. A transmitting/receiving device characterized by comprising an adder that mutually adds the transmitted signals and further adds the values obtained for each output terminal to each other.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP8795085U JPH025426Y2 (en) | 1985-06-11 | 1985-06-11 |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP8795085U JPH025426Y2 (en) | 1985-06-11 | 1985-06-11 |
Publications (2)
Publication Number | Publication Date |
---|---|
JPS61203376U true JPS61203376U (en) | 1986-12-20 |
JPH025426Y2 JPH025426Y2 (en) | 1990-02-08 |
Family
ID=30640635
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP8795085U Expired JPH025426Y2 (en) | 1985-06-11 | 1985-06-11 |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPH025426Y2 (en) |
-
1985
- 1985-06-11 JP JP8795085U patent/JPH025426Y2/ja not_active Expired
Also Published As
Publication number | Publication date |
---|---|
JPH025426Y2 (en) | 1990-02-08 |
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