JPS61202233A - Control method of microcomputer - Google Patents

Abstract

PURPOSE:To increase the control speed of a microcomputer by keeping the data stored before a runaway occurs in a reset mode of the program runaway and therefore using effectively the previous stored data to eliminate the time delay due to initialization. CONSTITUTION:When a program runaway occurs, a closed loop action of processes (1) (2) (1) is started. Under such conditions, a P-RUN terminal of a CPU 101 is kept at a fixed H or L level. Then the signal of an L level is delivered from a watchdog timer 2. Thus the output of an AND circuit is set at an L level and a reset signal is applied to the CPU 101. Thus a program is started again. In such a runaway mode the memory contents of a RAM 103 are not broken in general and therefore the decision data is kept. Thus a processing program is started without carrying out the initialization again.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a control method for a microcomputer, and more particularly to a control method during a reset operation.

[Description of Prior Art] As is well known, in a microcomputer, a reset signal is input when power is turned on or when a program runs out of control.
This causes the program to restart. Conventionally, a method has been adopted in which initial settings are performed and the process is transferred to a processing program each time a reset signal is input, without distinguishing between a reset when the power is turned on and a reset when a program runs out of control. Therefore, the data accumulated before the runaway of the program is lost due to a reset caused by the runaway, resulting in an operational disadvantage that the previously accumulated data cannot be used.

Further, in the conventional method, even if a program runs out of control, the program is simply reset repeatedly, so even if runaway occurs frequently, this fact cannot be recognized from the outside. Therefore, control is continued under conditions where runaway frequently occurs, which may impair controllability.

[Object of the Invention] The present invention has been made based on the above viewpoint, and its purpose is to provide a control method for a microcomputer that can leave accumulated data before the runaway when resetting the program when the program runs out of control. It is in.

Another object of the present invention is to provide a microcomputer control method that allows external recognition of program runaways that occur frequently.

[Means for Achieving the Object] In the present invention, judgment data stored in a ROM of a microcomputer is written to a RAM of the microcomputer during initial setting, and a reset signal is input to the microcomputer. In this case, the judgment data in the ROM and the judgment data in the RAM are compared prior to the initial setting, and if they match, the processing program is executed without performing new initial settings, and if they do not match, the processing program is executed. By executing the processing program after writing the judgment data and performing the initial setting, it is possible to leave the accumulated data at the time of resetting when the program runs out of control.

Further, by counting the number of inputs of a reset signal in which the judgment data in the ROM and the judgment data in the RAM match, and issuing a program runaway warning when the count reaches a predetermined number, the program runaway can be prevented frequently. make it possible to recognize the facts that are occurring from the outside.

Embodiments of the Invention] FIG. 1 is a block diagram for implementing the method of the present invention, and FIG. 2 is a flowchart showing an embodiment of the method of the present invention.

In Fig. 1, l is a microcomputer, and the CPU
10I, ROM102, and RAM103. 2 is a watchdog timer, P- of the CPU 101
A program run signal output from a RUN (program run) terminal is input, and runaway of the program is detected when this signal is at a constant H level or a constant L level. The watchdog timer 2 outputs an L level signal when a program runaway is detected, and outputs an H level signal in a steady state. 3 is an AND circuit, one input terminal of which is connected to the output side of the watchdog timer 2, and the other input terminal of which is connected to one end of a resistor R via a connection with a capacitor C whose end is grounded. The other end of the resistor R is connected to the power switch 4. Since one input terminal of the AND circuit 3 is connected to the power switch 4 via the resistor R and the capacitor C, an H level signal is applied to the input terminal at the same time as the power switch 4 is closed. The H-level signal is applied after a predetermined short time has elapsed after the closure. The output terminal of the AND circuit 3 is connected to the 1-1 (reset) terminal of the CPU10I, and the reset signal caused by power-on and the reset signal caused by a runaway program are sent to the CPU1 as an L level signal.
01. The ROM 102 of the microcomputer 1 stores predetermined judgment data along with control programs and the like. This judgment data is
This serves as a criterion for determining whether a reset signal is given due to power-on or a runaway program, and can be composed of arbitrary data. This judgment data is used when initializing the RA as described below.
It will be written to M103.

With this configuration, when the power switch 4 is closed, A
An H level signal from the watchdog timer 2 and a signal provided via a resistor R and a capacitor C are applied to an input terminal of the ND circuit 3. The signal applied via the resistor R and the capacitor C is at the L level until a predetermined short time has elapsed after the power switch 4 is closed, and then becomes the H level. Therefore, at the same time as the power switch 4 is closed, an L level reset signal is applied from the AND circuit 3 to the CPU10I, and the program according to the flowchart of FIG. 2 is started. In addition, power switch 4
When the above-mentioned short period of time has elapsed after the opening of the AND circuit 3, both input levels of the AND circuit 3 become H level, so that the reset caused by turning on the power is canceled.

Upon input of a reset signal upon power-on, a match is determined between the determination data in the ROM 102 and the determination data in the RAM 103 (step 5). The judgment data previously stored in the ROM 102 is transferred to the RA in the next step 6.
It is written to M103. When the power is turned on, the previous contents of the RAM 103 are destroyed, so even if judgment data was written in the RAM 103 during the previous operation, the judgment data is in a destroyed state. Therefore, when a reset signal is input due to power-on, the judgment data in the ROM 102 and the judgment data in the RAM 103 do not match. As a result, the process moves from step 5 to step 6, where new judgment data is written into the RAM 103 and initial settings are performed.

Thereafter, the target process is performed by circulating in a closed loop formed by the process steps. Step 7 in this closed loop is to invert the output of the P-RUN terminal of the CPU I O1 every round of the closed loop. Therefore,
If the processing program circulates in a closed loop without running out of control, a pulse train is given to the watchdog timer 2, and as a result, an H level signal is given from the watchdog timer 2 to the AND circuit 3, so that an L level signal is given to the AND circuit 3. A reset signal is never output.

On the other hand, the program may run out of control, such as processing (
Assuming that a closed-loop operation is started in the order of 1) → Processing (2) → Processing (1), the P-RUN terminal of CPU10I becomes a constant H level or a constant L level, and the watchdog timer 2 outputs an L level signal. Ru. As a result, A
The output level of the ND circuit 3 becomes L level, and the CPUl0I
A reset signal is applied to the program to restart the program and proceed to step 5. In the event of such a runaway, the storage contents of the RAM 103 are generally not destroyed, so the judgment data remains. Therefore, since the judgment data in the ROM 102 and the judgment data in the RAM 103 match, the process can be moved to the processing program without performing new initial settings (Stage 2 Pro).
A processing program is started according to the accumulated data before the runaway.

In addition, in the event of a runaway, the judgment data in the ROM 102 and R
If there is a discrepancy with the judgment data in AM103,
The same operation as when the power is turned on is performed, and corrupted stored data will not be used.

FIG. 3 is a flowchart showing another embodiment of the method of the present invention, the feature of which is that it is configured to count the number of times the program runs out of control and to warn the outside when runaway occurs frequently. .

Upon input of a reset signal upon power-on, a match between the determination data in the ROM 102 and the determination data in the RAM 103 is determined as in the previous embodiment. When the power is turned on, they will not match as mentioned above, so the RAM10
After writing the judgment data for No. 3 and clearing and initializing the variable X (step 8), the process moves to the processing program.

The variable X is the judgment data in the ROM 102 and the RAM 103.
It represents the number of inputs of a reset signal that matches the judgment data in the table, or in other words, represents the number of times the program runs out of control.

When a program runaway as described above occurs in the processing program, the process proceeds to step 9 via step 5 due to the reset, and the variable X is incremented by +1 (0) Next, it is determined whether the variable A judgment is made (step 10). If the variable
The process moves to the processing program via step 11). This warning display informs the outside that the program is frequently running out of control.

Note that the configuration for implementing the method of this example can be easily configured by adding a display means to the configuration shown in FIG. 1 according to well-known technology.

FIG. 4 is another configuration diagram for implementing the method of the present invention, and its characteristics are as follows: CPU 121. ROM122 and RAM1
The purpose of the present invention is to use an internal timer of the microcomputer 12 having 23 to give a reset signal at predetermined time intervals regardless of whether the program runs out of control. That is, in the flowchart of FIG. 2, a reset signal is supplied at predetermined time intervals.

ROM at predetermined intervals regardless of whether the program runs out of control.
122 and the judgment data in the RAM 123.

In this way, there is no need to provide a watchdog timer, so the configuration can be simplified. This example can be applied to, for example, control of an air conditioner, which may be controlled relatively slowly.

[Effects of the Invention] As explained above, according to the present invention, the accumulated data before the program runaway is not initialized based on the coincidence judgment between the judgment data in the ROM and the judgment data in the RAM. Therefore, previously accumulated data can be used effectively, and there is no time delay associated with initialization, and control operations can be accelerated. In addition, we have decided to count the number of program runaways and issue a warning when the number of runaways exceeds a predetermined number, making it possible to recognize from the outside the situation where program runaways are occurring frequently, and to respond quickly. becomes possible.

[Brief explanation of drawings]

FIG. 1 is a block diagram for carrying out the method of the present invention, FIG. 2 is a flow chart showing one embodiment of the method of the present invention, FIG. 3 is a flow chart showing another embodiment of the method of the present invention, and FIG. 4 is a flow chart showing another embodiment of the method of the present invention. FIG. 3 is another block diagram for implementing the method of the present invention. 1.12: Microcomputer 2: Watchdog timer 3: AND circuit 4: Power switch 101.121: CPU 102.122: ROM 103.123: RAM

Claims (2)

[Claims] (1) When initializing the judgment data stored in the ROM of the microcomputer,
AM, and when a reset signal is input to the microcomputer, the judgment data in the ROM and the judgment data in the RAM are compared before the initial setting, and if the two match, a new one is written. A method for controlling a microcomputer, characterized in that the processing program is executed without performing initial settings, and in the case of a mismatch, the processing program is executed after writing the judgment data and performing the initial settings. (2) The scope of the claim is that the number of inputs of a reset signal in which the judgment data of the ROM and the judgment data of the RAM match is counted, and when the count reaches a predetermined number, a program runaway warning is given. The method for controlling a microcomputer according to item 1.