JPS61121107A - Programmable controller - Google Patents

Abstract

PURPOSE:To secure the accurate and stable control of positioning, etc. by performing the interruption processing when the coincidence is secured between the set target value and the count value of a counter. CONSTITUTION:A CPU11 reads a sequence program set by a user out of a RAM13 and executes it. A pulse P1 is supplied to a counter 15a of a counting part 15 in response to the shift amount of an object, and a reset pulse P2 is supplied at an end point, etc. of the course of the traveling object. A comparator 15b compares the set target value with the count value of the counter 15a and sends a signal D1 to an interruption terminal 11a of the CPU11 when the coincidence of comparison is obtained. Then the CPU11 executes an interruption processing program, and the control output is delivered from an interface 14. At the same time, the next target value is written to the comparator 15b.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a programmable controller, and proposes a programmable controller that can control the stop position of a moving object with high precision, for example.

[Prior art]

When controlling the positioning of the stop position of a moving object using a programmable controller, a value corresponding to the moving distance is set in a counter in the controller, and a count input generated as the moving object moves is given to the counter,
The stop control output was directly or indirectly obtained by outputting a coincidence signal from the counter obtained when the counted value coincided with the set value.

FIG. 2 is a block diagram of a programmable controller that performs positioning control using the method described above. CPU
(Central processing unit) 21 is ROM (memory for continuous use) 2
It operates according to the system program written in the system program 2, reads the sequence program set by the user to the RAM (random read/write memory) 23, and calculates the count preset value via the interface 24 to the counter 25a of the counting section 25. and set the target value to comparator 2 as well.
Set to 5b. For example, the count preset value is position information at the time of setting the moving object, and the target value is information on the position at which the moving object should be stopped. The counter 25a receives a pulse P1 corresponding to the movement of the object a certain distance as a counting input, and the comparator 25b compares the counted value of the counter 25a, which changes depending on the input of the pulse Pi, with a target value. If the results match, signal port 1 of a predetermined level is emitted. This signal 01 is read by the CPII 21 via the interface 24. The CPt 121 receives this signal Dl and outputs a control output such as an opening signal via the interface 24.

In the above programmable controller (:
Since the PU 21 operates cyclically according to the system program, reading the output of the comparator 25b of the CPt 121 is periodic. Therefore, in order for the CPt 121 to reliably read the output signal Di of the comparison result of the counting section 25, at least one cycle of the scan time is required. In other words, the output timing of the signal D1 and the CPU 21
The timing of reading this or the timing of control output differs each time, and therefore the positioning accuracy cannot be said to be good.

FIG. 3 shows another conventional example with improved positioning accuracy. Components similar to those in FIG. 2 are given the same numbers. The comparison result memory 27 stores the comparison result at the time when the count preset value and the target value are set in the counting section 25, that is, the output of the comparator 25b. As the pulse Pi continues to be input, the output of the comparator 25b changes to large-coincidence, small or small-coincidence, and large, but at this time, the comparison result memory 27
is configured to act directly on the control output controller 28 to cause it to issue a control output. Therefore, the on/off of the control output is not affected by the cyclic operation of the CPII 21, and the delay between the comparison result match signal 01 and the control output is eliminated.

By the way, even with the configuration shown in Figure $3, there are the following disadvantages when positioning is performed at two or more force points (when two or more target values are set). That is, counter 2
Each time the count value of 5a reaches each target value, it is necessary to set the next target value in the comparator 25b, but in the case of FIG. Memory 2 for comparison results of comparator 25b
Writing to 7 is performed by the cyclic operation of the 02 port 21. In other words, the next target value is written in accordance with the comparison result read with a scan time delay.

Therefore, if two target values are close to each other, the count value of the counter 25a will exceed the next target value before writing the next target value, and as a result, control will be performed at the corresponding position. The problem is that it is not possible.

Figure 4 shows one example, where the count precent value is 10.
00, deceleration control at first target value 2000, second target value 2
This is a case of motor start/stop control where the stop control is to be performed at 100 kHz, and the frequency of the count pulse is 1 kHz.
and the scan time of CPU21 is 100111s
It shall be equal to or higher than ec. When 1000 is set, a motor drive output is generated, and when the count value of the counter 25a reaches 2000, the control output count roller 28 immediately generates a deceleration output due to the function of the memory 27. The window where the count value goes from 2000 to 2100 requires 100m5e+:, but it takes 10m5e+: from the time the count value reaches 2000 until the CPU 21 detects it.
0m5ec or more may be required. Then, when the second target value is set in the comparator 25b, the count value is 21.
00, and the comparator 25b does not output a coincidence signal for this target value. FIG. 4 shows an example in which a stop output is issued for safety when the four-digit counter 25a reaches a full count value of 9999.

As described above, conventional programmable controllers have limitations due to the scan time of the CPU.

[Means for solving problems]

The present invention was made to solve this problem, and when the comparator of the counting section detects a match, the CP
As a configuration that interrupts U, it has high-speed response,
Another object of the present invention is to provide a programmable controller that can handle multi-stage settings.

The programmable controller according to the present invention includes a counter, a comparator that compares the count value of the counter with a set value and issues a match signal when the two match, and a plurality of target values to be sequentially set in the comparator. a memory for storing the same, and when the coincidence signal is input, executes an interrupt processing routine and issues a control output corresponding to the input coincidence signal;
and a processor that updates the set value of the comparator.

〔Example〕

FIG. 1 is a block diagram showing the basic configuration of the product of the present invention.

The CPU 11 reads out a sequence program set by the user in the RAM 13 and executes it according to the system program written in the ROM 12. A count preset value and a target value are respectively set in the counter 15a and comparator 15b of the counting section 15 by the CPU 11 as in the conventional device.

The counter 15a has a pulse P1 corresponding to the amount of movement of the moving object.
is input as the object to be counted, and a reset pulse P2 is input at the end point of the moving object's travel. Comparator 1
5b compares the set target value with the counted value of the counter 15a, and when the comparison results match, outputs a signal Dl, which is applied to the interrupt terminal 11a of the CPU it.

The CPU 11 performs a certain cyclic operation according to the program in the ROM 12 until a signal is input to the interrupt terminal, and when the signal is input, the CPU 11 of the present invention performs interrupt processing. and run the program. This interrupt processing program is executed at a sufficiently high speed compared to the cycle time or scan time, and as a result of this execution, a control output is issued from the interface 14 very quickly, and the next target value is written to the comparator 15b. will be held.

FIG. 5 shows another embodiment of the invention. In this embodiment, the reset pulse P2 is sent to another interrupt terminal 1 of the CPU 11.
1b, and when this is given, a reset interrupt process is performed and the counter L5a is reset etc.
Different from the one shown.

Next, the configuration and operation of the product of the present invention will be explained in more detail based on a flowchart showing the processing contents of the CPIJ 11 or the contents of the program in the ROM 12.

Figure 6 shows the main routine, when the power is turned on,
The commands in the RAM 13 are searched and a high-speed force/kundo program including high-speed counting processing such as positioning control as described above is confirmed. Next, the target values of the high-speed counting program are stored in a predetermined area (working area) of the RAM 13 or a register of the CPU 11 in descending order. Then, the smallest first target value is set in the comparator 15b.

Next, the human output is transferred, and the contents of the sequence program in the RAM 13 are read and executed.

Thereafter, this transfer and execution of the sequence program are repeated.

During such repeated execution, when a signal indicating coincidence between the target value and the counted value of the counter 15a is input from the comparator i5b to the interrupt terminal 11a, the CPU 11 executes the coincidence interrupt processing routine shown in FIG. to go into. This program first performs input processing such as reading various input signals, and then executes a high-speed counting program.

Then, when a comparison is made, a control signal to be output is output to a predetermined area (input/output canister) of the RAM 13,
Next, output processing is performed to output this to the outside. Then, the next target value is set in the comparator 15b.

And the ratio between the counted value of the counter 15a and the new target value! Check the results and return to the main routine. The coincidence interrupt processing described above is performed in an extremely short time, but if the next target value is extremely close to the previous target value and a situation occurs during which the counted value exceeds the next target value, this coincidence occurs. The interrupt handling routine will be executed again.

FIG. 8 shows the reset pulse P in the embodiment shown in FIG.
This is a reset interrupt processing routine that is executed when 2 is input to the interrupt terminal 11b, and resets the count value of the counter 15a, sets the target value to the smallest value, and performs input/output processing. Return to main routine.

Next, the above processing will be explained based on a specific example.

FIG. 9 is a ladder diagram showing part of the contents of the sequence control to be performed by the product of the present invention, and the relevant contents are written in IIAM 13. This program includes a high-speed counting program including a 4-digit high-speed counter 15a, and according to the counted value, the moving object moves forward with a control output of 30 cents (target value is ioo >, control output 31
Setting the control output 32 causes deceleration (target value is 250), and setting the control output 32 causes stopping (target value 300).

When the power is turned on, instructions in the RAM 13 are searched, the high-speed count program is confirmed, and the target values of 100, 250.300 are set in the working area in this order, and then "0000" is set in the counter 15a. , and the first target "0100" is sent to the comparator 15b. The CPU 11 repeats input/output transfer and execution of the contents of the RAM 13. During this time, the counter 15a
When the count enable signal 2 is applied to the counter 15a, the counter 15a starts counting. The 1011th iU shows each value before the start of counting.

When the count value reaches 100, the comparator 15b issues a match signal, which enters the match interrupt processing routine and outputs the control output 3.
0 is output and the iIJ hex control output is set. Further, a second target value "0250" is set in the comparator. At the end of this set, the count 416 is "0100+α", which is slightly larger than 100, as shown in FIG. Here, α is the value counted by the counter 15a during the time from when the count value becomes 1oo and a coincidence interrupt is applied until the second target value 250 is written to the comparator 15b.

If 100+α<250 at the time when the second target value is written, the program returns to the original main routine and executes cyclic processing, waiting for the input of the next interrupt signal P1 or P2.

When the count value reaches 250, the control output 31 is output in the same manner as described above, the deceleration output is set, and the third target value "0300" is written into the comparator 15b.

The count value of counter L5a at the time of writing is 250+β
(Fig. 12), if 250+β<300, the process returns to the main routine, but if 300≦250+β, the coincidence interrupt process is executed again, the control output 32 is output, and the stop output is set. That will happen. When returning to the main routine, the control output 32 is similarly output when the count value reaches 300.

In FIG. 9, reference numeral 33 is an input that detects that the moving object is located at the forward object, and the control output 30 in iiJ base is reset. Further, 1 is an emergency stop input, which sends the control output 32 to the center. Further, 3 is a reset input of the counter 15a.

Further, the normal program includes an output 34 that displays automatic operation when there is an input 10 that instructs automatic operation of a moving object to be controlled, and an output 35 that activates an internal relay for automatic operation.
Indicates the contents to be set.

〔effect〕

In the case of the product of the present invention as described above, the interrupt processing is executed when a match between the set target value and the count value of the counter is detected, so it is not affected by the scan time, and therefore the control of positioning etc. Accuracy becomes accurate;
It also stabilizes. In addition, when setting multiple target values sequentially, the time from detecting the match between the first target value and the count value to setting the next target value is extremely short, so the required No inconveniences such as lack of control occur. In particular, as in the above embodiment, after setting a new target value, it is immediately compared with the counted value, and if the counted value already exceeds the target value, the interrupt process is executed again without returning to the main routine. In this case, there will be no problem in control even when the previous and subsequent target values are very close to each other.

[Brief explanation of drawings]

Fig. 1 is a block diagram showing one embodiment of the present invention, Fig. 2 and 3 are block diagrams showing one embodiment of the present invention.
The figure is a block diagram of a conventional example, FIG. 4 is a timing chart for explaining the problem of the one in FIG. 3, FIG. 5 is a block diagram showing another embodiment of the present invention, and FIGS. A flowchart showing the control details of the product of the present invention, FIG. 9 is RA
A ladder diagram showing the contents of M, and FIGS. 10 to 12 are explanatory diagrams showing changes in the count value and target value when performing the control shown in FIG. 9. Ll...CPU 12...RO and 13...R
A? I 14...Interface 15...t
tG section L5a... Counter 15b... Comparator patent Applicant: Koyo Electronics Industry Co., Ltd. Agent Patent attorney: Noboru Kono No. 7 (21 Toki 9 Figure IQ Figure ++ [21 Figure 12 Vi correction) (Spontaneous) December 14, 1980 Patent Application No. 244784 2, Name of the invention Programmable Controller 3, Relationship with the person making the amendment Patent applicant Address: 1-171 Tenjin-cho, Kodaira-shi, Tokyo Name
Koyo Electronics Co., Ltd. Representative: Toshio Morita 4, Agent Address ■543 1-14-22 Shitennoji, Tennoji-ku, Osaka Nisshin Building No. 207 "Detailed description of the invention" column and drawing 6-1 1. Detailed explanation of the invention in the specification" column (1) "Signal D" in the 1st and 3rd lines of page 8 of the specification is corrected to "Signal D+J. "Signal D" on page 9, line 12 is corrected to "signal DIJ." (3) On page 9, lines 14-15 of the specification, "input processing such as reading various input signals is performed, "Then," should be deleted. (4) Delete "Perform input processing" on page 10, line 13 of the specification. 6-2 Figures 8 and 9 will be corrected as shown in the attached corrected drawings. 7. List of attached documents (1) Corrected drawings 1 copy Figure 8 Figure 9

Claims (1)

[Claims] 1. A counter, a comparator that compares the count value of the counter with a set value and issues a match signal when the two match, and a memory that stores a plurality of target values to be sequentially set in the comparator. , a processor that executes an interrupt processing routine when the coincidence signal is input, issues a control output corresponding to the input coincidence signal, and updates the set value of the comparator. controller.