JPS6148178B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a timer device, and more particularly, to a timer device for a data processing device that generates a timer interrupt signal.

In conventional timer interrupt control systems in data processing devices, when a timer interrupt occurs, the processor must respond quickly to the interrupt from the viewpoint of timer accuracy, resulting in an increase in system overhead.

On the other hand, if the priority of timer interrupts is kept low and the processing order is lowered, there is a drawback that timer processing is not performed at the required time, causing serious trouble to the system.

SUMMARY OF THE INVENTION An object of the present invention is to eliminate the above drawbacks, provide a timer device that is highly accurate, has little time dependence on the system, and does not miss the processing timing.

In order to achieve the above object, a timer device according to the present invention is provided in a timer device of an information processing device that generates a timer interrupt signal. an interval timer that operates to count up for a period of time; a comparison circuit that compares the values of the preset register and the interval timer and generates the match signal to clear the interval timer when they match; and a comparison circuit that generates the match signal and clears the interval timer; A rollover counter that counts the number of times and generates an interrupt that increases the priority of the interrupt every time the match signal is counted until the program reads this count value and issues a clear instruction by interrupt processing. It is configured.

According to the above configuration, the object of the present invention can be completely achieved.

Hereinafter, the present invention will be explained in more detail with reference to the drawings.

FIG. 1 is a circuit diagram showing an embodiment of a timer device according to the present invention.

In the figure, 100 is preset data input 1
When "a110" is applied to 10 and the match signal 310 indicates a match, preset data is loaded, and when it indicates a mismatch, an interval timer that performs a counting operation; 200 is a preset register that can be set by a program; 400 is a comparison circuit which inputs the output 120 of the interval timer and the output 210 of the preset register, compares the two, and outputs a match signal 310 when the comparison matches.
inputs the clear instruction signal 410 from the program and the match signal 310, and outputs the clear instruction signal 410.
AND outputs an output signal 420 when a clear instruction is not indicated and the match signal 310 indicates a match.
The circuit 500 loads the preset data by the clear instruction signal 410 when "a110" is applied to the preset data input 510, and outputs the AND circuit output 4.
Counting operation is performed by applying 20, and output 52
A rollover counter 600 outputs a count value to 0, and outputs a timer interrupt signal 610 using the rollover counter output 520 as input.
Each shows an OR circuit.

In this embodiment, first, a timer interrupt interval value is set in the preset register 200 from the program. This timer interrupt interval value is output to the output 210 of the preset register 200, and is output to the comparator circuit 30.
0 is the output 12 of the interval timer 100.
Compare with 0. As a result of the comparison, if there is a mismatch, the interval timer 100 is prompted to count up, and if a match is detected, a match signal 310 is sent.
The count-up operation of the interval timer 100 is prohibited and the data of "a110" is loaded into the interval timer 100.

By loading this "a110" data, the comparison result of the comparator circuit 300 again becomes inconsistent, and the interval timer 100 restarts counting from "0".

On the other hand, the match signal 310 is supplied to the AND circuit 400 when the comparison circuit 300 detects a match, and if there is no clear instruction signal 410, that is, if the clear instruction signal 410 is "1", the match signal 310 is sent to the rollover counter via the AND circuit 400. Added to the 500 count up terminal. rollover counter 5
00 until there is an instruction from the clear instruction signal 410.
That is, the number of times the comparison circuit 400 detects a match is accumulated until the clear instruction signal 410 becomes "0".

When the rollover counter 500 is integrated, the count value of the rollover counter 500 is output from the output 520 of the rollover counter 500, and if the count value is not "0", the OR circuit 60
A timer interrupt signal 610 is generated from 0.

The output 520 of the rollover counter 500 and the timer interrupt signal 610 are further connected to a processor control unit (not shown), and become an interrupt having the level indicated by the output 520 of the rollover counter 500, and the program is interrupted.

After notifying the program of the interrupt, the timer processing routine of the program is activated and until the program issues the clear instruction signal 410,
A comparison circuit 300 is included in the rollover counter 500.
The number of matching detections is stored. Further, if the program does not respond to an interrupt, the interrupt level of the output 520 of the rollover counter 500 increases as time passes.

Although not shown in this embodiment, the rollover counter 500 is a program-visible counter, and the interrupt level that changes with the value of the rollover counter 500 is set to a higher value by giving an appropriate weight to the value of the rollover counter 500. It is also possible to make various configurations.

As explained above, according to the present invention, a program can know the elapsed time while waiting for an interrupt by reading the rollover counter during timer interrupt processing.
Moreover, by configuring the interrupt level to increase according to the number of matches of the interval timer, the timer interrupt request will not be waited for an unreasonably long time.
It is possible to perform timer processing with high precision and in a timely manner.

[Brief explanation of the drawing]

FIG. 1 is a diagram showing an embodiment of a timer device according to the present invention. 100...Interval timer, 110...Interval timer preset data input, 120
...Interval timer output, 200...Preset register, 210...Preset register output, 300...Comparison circuit, 310... Match signal, 400AND circuit, 410...Clear instruction signal, 420...AND circuit output, 500...rollover counter, 510...rollover counter preset data input, 520...rollover counter output, 600...OR circuit,
610...Timer interrupt signal.

Claims (1)

[Claims] 1. A timer device of an information processing device that generates a timer interrupt signal includes a preset register in which a timer interrupt interval value is set by a program, an interval timer that performs a count-up operation until a match signal is detected, and the preset register. A comparator circuit that compares the values in the set register and the interval timer, and when they match, generates the match signal and clears the interval timer; and a comparator circuit that counts the number of times the match signal is generated, and the program reads this count value. A timer device comprising a rollover counter that generates an interrupt that increases the priority of the interrupt every time the coincidence signal is counted until a clear instruction is given by interrupt processing.