JPS61200580A - Bit map display control system - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION Technical Field The present invention relates to a bitmap display control system, and particularly to a CR
The present invention relates to a bitmap display control method suitable for speeding up bitmap display processing using a T-display.

BACKGROUND OF THE INVENTION A schematic block diagram of a conventional bitmap display control system is shown in FIG. At this time, the character pattern is.

The data is sequentially read out from the character generator 7 in accordance with the character code, and expanded into the bitmap memory 3 via the system bus 8. The expanded data in the bitmap memory 3 is sequentially read out as parallel data by the CRT controller 4.

It is converted into serial data by a parallel-to-serial converter 5 and supplied to a CRT display 6 as a VIDEO signal. Further, the CRT controller 4 outputs a horizontal synchronization signal (HSYNC signal) and a vertical synchronization signal (VS'YNC signal) to synchronize characters displayed on the CRT display 6.

In this way, in the conventional bitmap display control method, one character pattern is written from the character generator 7 to the bitmap memory 3 via the system bus 8, which reduces the usage efficiency of the system bus 8 and makes it difficult for the character generator 7 to The problem was that it required 200 yen of memory.

Purpose The purpose of the present invention is to solve such conventional problems, simplify the system configuration in a bitmap display control system, improve system bus usage efficiency, and improve the processing speed of the entire system. An object of the present invention is to provide a bitmap display control method that reduces costs.

Structure In order to achieve the above object, the present invention is characterized in that, in a bitmap display control system, an empty area of a memory implemented as a frame buffer memory for p1-map display is used as a character generator. .

Hereinafter, the configuration of the present invention will be explained using examples.

Generally, in high-resolution bitmap display, display data is read out sequentially as multiple bits of parallel data. For example, 1536 dots in the horizontal direction and 204 dots in the vertical direction.
When displaying 8 dots on a CRT display using the interlaced scan method, 1 display data is 64
The bits are read out sequentially in parallel. At this time, the required bitmap memory capacity is 393,216 bytes, but the memory elements actually implemented are 64 dynamic memories of 64K x 1 bit, and the installed memory capacity is 524 bytes.
This will be 288 bytes. Of this, the capacity used for actual display is <393216 bytes as mentioned above, so 1310
72 bytes will be a free area. The present invention uses this empty area as a character generator (CG).

FIG. 1 is a schematic block diagram of a bitmap display control system showing an embodiment of the present invention.

This converts the character generator 7 of the conventional bitmap control system shown in FIG.
It is different from the conventional method in that it is provided in an empty area within the area (herein referred to as 3'). Since the other configurations are the same as those of the prior art, please refer to the above-mentioned prior art for the points for which explanations are omitted.

This bitmap display control system converts the CPU 1, system memory 21, and empty areas, which are the main parts of the present invention, into a CG image.
Bitmap memory 3' used as CRT
Controller 4, parallel-serial converter 5, CRT
It consists of a display 6 and a system bus 8.

The CPU develops characters, graphs, images, etc. to be displayed in the bitmap memory 3'' according to the program stored in the system memory 2. At this time, the character code information is given to the CRT controller 4. 4, the corresponding character pattern from the character generator (CG) stored in the free area of the bitmap memory 3' is expanded onto the bitmap memory 3'.In the case of the above bitmap display example, the character pattern is 16 x 16 dots. In the case of a character pattern of 32×32 dots, 1024 characters can be stored in the free area of the bitmap memory 3', so the free area has sufficient storage capacity for a character generator (CG).

In this manner, according to the present embodiment, there is no need to sequentially write character patterns from the character generator (CG) 7 to the bitmap memory 3' via the system bus 8 as in the conventional case, so the display processing details Yoshi's engraving (no changes in content) Speed and overall system processing speed are improved, and since no memory is required for the character generator CG, costs can be reduced.

Effects As explained above, according to the present invention, in a bitmap display control system, the system configuration can be simplified, the system bus usage efficiency can be improved, and the processing speed of the entire system can be improved and costs can be reduced.

[Brief explanation of drawings]

FIG. 1 is a schematic block diagram of a bitmap display control system showing an embodiment of the present invention, and FIG. 2 is a diagram for explaining a conventional bitmap display control system. 1: C: PU, 2 system memory, 3.3': Bitmap memory, 4: CRT controller, 5: Parallel-serial converter, 6: CRT display, 7:
Character generator, 8 system bus.

Claims (1)

[Claims] (1) In a bitmap display control system, a bitmap display control method is characterized in that an empty area of a memory implemented as a frame buffer memory for bitmap display is used as a character generator.