JPS6120000B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a driving device for a liquid crystal matrix panel, and more particularly to an improvement in a circuit that generates a driving voltage waveform.

Conventionally, it has been known to drive a liquid crystal matrix panel with alternating current using a line sequential scanning method and a voltage averaging method. proposed a liquid crystal matrix panel driving device as shown in (Japanese Patent Application No. 112994/1982).

In FIG. 1, reference numeral 10 denotes a liquid crystal matrix panel, which has a plurality of scanning electrodes X1 to X4 and signal electrodes Y1 to Y4 arranged to intersect each other so as to define a large number of matrix intersection points to become pixels. When the voltage applied to the liquid crystal interposed between the opposing electrodes at each matrix intersection point exceeds a certain value (referred to as threshold voltage V _th ), the orientation state of the liquid crystal molecules changes and the light transmittance increases. changes. When displaying images on this type of panel, the scanning electrodes
It is designed to supply image signals to the Y4 side,
As a driving method in this case, an alternating current driving method called a voltage averaging method is preferably used in order to prevent unevenness in the excited state of the liquid crystal.

In the drive device shown in FIG. 1 which employs such a line sequential scanning method and voltage averaging method, 12 is a scanning circuit that generates a line sequential scanning signal, and 16 and 18 are selection voltages V _S1 as shown in FIG. , non-selection voltage V _NS
1 , 20 is a first electronic switch circuit that combines voltages V _S1 and V _NS1 in accordance with the line sequential scanning signal to synthesize a driving voltage waveform to be supplied to each scanning electrode, and 22 is an image generating circuit. A serial-parallel conversion circuit having a signal input terminal 22a, 24 is 1
a line memory for storing image signals for rows, 28;
30 is a voltage generation circuit that generates a selection voltage V _S2 and a non-selection voltage V _NS2 as shown in FIG. 2;
32 is a second electronic switch circuit that combines the voltages V _S2 and V _NS2 in accordance with the state of each bit of the image signal from the line memory 24 to synthesize a driving voltage waveform to be supplied to each signal electrode. The electronic switch circuit 20 has a pair of electronic switches 20a and 20b connected to each scanning electrode, and a positive-phase scanning signal is applied to the control terminal of each electronic switch 20a, and the electronic switch 20b is connected to each scanning electrode. A scanning signal of opposite phase is applied to the control terminal of the switch 20b via the inverter 14. The electronic switch pair alternately opens and closes so that when one switch is on, the other switch is off, and a selection voltage V _S1 is applied to the common output side as shown in Figure 2.
and _a non-selection voltage V _NS1 . The electronic switch circuit 32 is also configured in the same manner as the circuit 20 described above, and has a pair of electronic switches 32a and 32b connected to each signal electrode, and the control terminal of each electronic switch 32a has a positive phase signal. An image signal of opposite phase is applied to the control terminal of each other electronic switch 20b via an inverter 26. electronic switch 32
The pair a, 32b is the electronic switch 20a,
20b, and generates at its common output terminal a voltage waveform V _Y for driving the signal electrode consisting of a combination of a selection voltage V _S2 and a non-selection voltage V _NS2 as shown in FIG. When driving voltages V _X and V _Y are applied to the liquid crystal matrix panel 10, the voltage actually applied to the liquid crystal becomes an AC waveform of V _X -V _Y as shown in FIG. Half-selected state, D becomes non-selected state.

In order to obtain the drive voltage waveform shown in Figure 2, a signal with two potential levels, VO and O, is used as the selection voltage V _S1 , and a signal with two potential levels, _VO and O, is used as the non-selection voltage V _NS1 , 1/aV _O and (1 -1/a) If a signal with two levels of V _O is selected as the selection voltage V _S2 , the two levels of O and V _O
For the non-selection voltage V _NS2 , signals with two levels of 2/aV _O and (1-2/a)V _O are required, respectively, and the voltage generation circuits 16, 18, 28 , 30 are composed of pulse oscillators that generate respective signals. Note that a is a constant determined according to the optimum driving conditions, and as shown in Japanese Patent Laid-Open No. 50-68419, when the duty ratio is 1/N, it is expressed as a=√+1.

In the circuit shown in Fig. 1, depending on the case _, driving voltage waveforms V _X and _{V Y} as shown in Fig. 3 are generated, and the AC waveform V You can also add In this case, V _S1 is 2 of +(1-1/a)V _O and -(1-1/a)V _O
level signal, V _NS1 as O level signal, V _S
2 and V _NS2 have opposite phases of ±1/aV _O
AC signals are generated respectively.

However, the above-mentioned conventional devices have two drawbacks: (1) The internal configuration of the voltage generating circuits 16, 18, 28, and 30 is complicated, so that changes in device specifications cannot be accommodated, and (2) those voltage generating circuits are (3) It is difficult to standardize the circuit.

Furthermore, as such a drive device, Japanese Patent Application Laid-open No. 52
It is known to use a resistive voltage divider circuit as described in Japanese Patent No. -55832. In this known technology, the number of resistors is 4, and the value of each resistor is 1:1:1:1 from one potential terminal side to the other potential terminal side, or the division ratio can be arbitrarily set. In order to take the ratio, the resistors are arranged so as to satisfy the ratio relationship of (√-1):1:1:(√-1) (n: duty ratio).

However, in this resistive voltage divider circuit, (1) only five potential levels can be generated; therefore, six potential levels suitable for the optimal voltage averaging method as shown in FIG. 2 cannot be generated;

(2) When taking the partial pressure ratio arbitrarily, (√−1) and (√
-1) It is necessary to adjust the values of two resistances in total.

There are problems such as:

SUMMARY OF THE INVENTION An object of the present invention is to solve this kind of problem and provide a liquid crystal matrix panel driving device with a simple configuration in which optimum driving conditions can be easily set and circuits can be standardized.

To summarize the features of the present invention,
The circuit that generates the drive voltage waveform to be supplied to the scanning electrodes and/or the drive voltage waveform to be supplied to the signal electrodes is configured as a single circuit by combining a resistive voltage divider circuit and a group of electronic switch circuits. .
A resistive voltage divider circuit has a plurality of resistors connected in series between a pair of potential terminals, and extracts all the potential levels necessary to configure the drive voltage waveform from these potential terminals or the connection point between the resistors. configured. Further describing preferred embodiments of the present invention,
One of the electronic switch circuit groups has a plurality of electronic switch pairs for opening and closing pairs of the potential levels in opposite phases in response to a synchronization signal, and the electronic switch pairs select the potential levels. - configured to generate a non-selection voltage.

These features not only simplify the circuit configuration and enable circuit standardization, but also make it extremely easy to deal with changes in device specifications, and in particular, make it easy to set or change optimal drive conditions. There are advantages.

The present invention will now be described in detail with reference to embodiments shown in the accompanying drawings.

Referring to FIG. 4, a circuit configuration of a liquid crystal matrix panel driving device according to an embodiment of the present invention is shown. In the circuit shown in FIG. 1, the same parts as in FIG. For the sake of simplicity, in this example, a case where a 3×3 liquid crystal matrix panel 10 is driven will be taken up, and the configuration and operation of the voltage generating circuit 40, which is a feature of the present invention, will be described in detail. In Figure 4, e ₁₁ , e ₁₂
...... _e33 indicates the liquid crystal body or pixel located at the matrix intersection point, and _VX1 to _VX3 are the scanning electrodes X1 to X
The voltage that drives signal electrodes _Y1 to V _Y3 is the voltage that drives signal electrodes Y1 to V Y3.
The voltage for driving Y3 is shown. Also, S1~
S3 indicates a sequential scanning signal, and L1 to L3 indicate each bit of an image signal for one row.

Selection voltage V _S1 and non-selection voltage V _NS1 on the scanning side and selection voltage V _S2 and non-selection voltage V _NS2 on the signal side
The voltage generating circuit 40 that generates the voltage has a configuration as shown in FIG. 5, and includes a resistive voltage dividing circuit 43 and an electronic switch circuit 50. The resistor voltage divider circuit 43 includes resistors 43A, 43B, 43C, and 43 connected in series between a pair of potential points 44A and 44F.
A power supply voltage V _DD is applied to the potential point 44A from the power supply terminal 41 via the variable resistor 42, and the potential point 44F is connected to the O potential or the ground potential. Resistance 43A, 43B, 43C,
The values of 43D and 43E are selected as R, R, (a-4)R, R, and R, respectively, in order to obtain the potential levels constituting the selection and non-selection voltages previously explained with reference to FIG. 2, and their resistance ratios are as follows. 1:1:(a-4):1:1
It is becoming. In this way, each resistor 43A to 43E
By giving weight to the resistance connection point 4
4B, 44C, 44D, 44E have potential points 44
If the potential of A is V _O and that of 44F is O, then (1-1/a) V _O and (1-2/a), respectively.
Potentials of V _O , 2/aV _O , and 1/aV _O can be obtained.

On the other hand, the electronic switch circuit 50 includes electronic switches 51a and 51b, 52a and 52b, 53a and 53b, 54a and 54b constituting four electronic switch pairs 51, 52, 53, and 54, respectively.
It is equipped with The output ends of the electronic switches 51a and 51b are connected to the output terminal 55, and the output ends of the electronic switches 52a and 51b are connected to the output terminal 55.
The output ends of the electronic switches 52b are connected to the output terminal 56, the output ends of the electronic switches 53a and 53b are connected to the output terminal 57, and the output ends of the electronic switches 54a and 54b are connected to the output terminal 58.
are commonly connected to each other. 48 is a terminal for applying the clock signal CP for the same period, and this terminal 48 is connected to the electronic switches 51a, 51
It is connected to each control input terminal of electronic switches 51b, 52a, 53a, and 54a via an inverter 49. As a result, the electronic switches of each electronic switch pair open and close in opposite phases, such that when one closes, the other opens. One of the electronic switches 51a constituting the electronic switch pair 51 has a potential point 44.
The voltage V _O at potential point A is supplied to the other electronic switch 51b, and the voltage O at potential point 44F is supplied to the output terminal 55, as shown in FIG. A voltage V _S1 is generated. One electronic switch 52a of the electronic switch pair 52 is supplied with the voltage (1-1/a)V _O at the connection point 44B, and the other electronic switch 52b is supplied with the voltage 1/aV _O at the connection point 44E. As shown in FIG. 7, the output terminal 56 receives a non-selection voltage V _NS1 on the scan electrode side in response to the clock signal CP.
is generated. One electronic switch 53a of the electronic switch pair 53 receives a voltage V _O from the potential point 44A.
is supplied to the other switch 53b, and the voltage O is supplied from the potential point 44F.
As shown in the figure, the output terminal 57 has a clock signal.
A selection voltage V _S2 on the signal electrode side is generated according to CP. Further, one electronic switch 54a of the electronic switch pair 54 has a voltage at the connection point 44C (1-
2/a) V _O is supplied, and the other electronic switch 54b is supplied with the voltage 2/aV _O at the connection point 44D, and the output terminal 58 outputs the voltage 2/aV O according to the clock signal CP as shown in FIG. A non-selection voltage V _NS2 on the signal electrode side is obtained.

Incidentally, as each of the electronic switches shown in FIGS. 4 and 5, an electronic switch made of a complementary metal oxide semiconductor (CMOS) integrated circuit as shown in FIG. 6 can be used. In Figure 6, IN is the input terminal,
OUT is the output terminal, V _C is the control terminal, and V _SS is the source power supply.

Now, with reference to FIG. 8, the overall operation of the circuit shown in FIG. 4 will be briefly described. As shown in FIG. 8, scanning signals S1, S2, S
3 is generated from the scanning circuit 12. Now, pixels
Assuming that e ₁₃ , e ₂₂ , and e ₃₁ are to be lit, the image signals are transferred from the line memory 24 to L 1 , L 2 , and L in FIG.
3 is generated as shown in FIG. When S1 and L3 are at H level, the driving voltages V _X1 and V _Y3 are the selection voltage V
Since they are formed by _S1 and V _S2 , pixel e ₁₃ is displayed, and similarly, pixel e ₂₂ is displayed when S2 and L2 are at H level, and pixel e ₃₁ is displayed when S3 and L1 are at H level. For scanning electrodes and signal electrodes related to pixels that are not lit or not displayed, for example, the electrode
Voltages similar to the voltages V _X1 and V Y1 applied to Y1 and _Y1 , respectively, are applied, and the pixel is in a half-selected state or a non-selected state.

As described above in detail, this embodiment is advantageous because the selection/non-selection voltage generation circuit has a simple configuration and the electronic switch circuit section 50 and the like can be easily standardized. In addition, the resistor voltage divider circuit 4
3, one of the reference potentials V _O can be easily changed by directly changing the magnitude of the power supply voltage V _DD or by changing the value of the resistor 42 . By changing the reference voltage V _O , the brightness and contrast of the liquid crystal can be adjusted. Particularly in this case, it is advantageous to use the variable resistor 42 because it can easily accommodate changes in device specifications regarding V _O.
Furthermore, setting or changing the optimum driving conditions can be easily carried out by simply adjusting one resistor 43C, and in this respect as well, there is high flexibility for various device specifications.

The present invention is not limited to the embodiments described above, and can be implemented in various modified forms. For example, instead of or in addition to the variable resistor 42 in the circuit of FIG.
A, and in that case, use a temperature-sensitive resistor whose resistance-temperature characteristics correspond to the temperature change in the threshold voltage _Vth of the liquid crystal as shown in Figure 9. This is extremely advantageous since temperature changes in the threshold voltage can be automatically compensated for.

As described above, according to the present invention, it is possible to obtain a liquid crystal matrix panel driving device with a simple configuration in which optimum driving conditions can be easily set and circuits can be standardized.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram of a liquid crystal matrix panel driving device according to the prior art, and FIGS.
A waveform diagram showing drive voltage waveforms when the device shown in the figure is AC driven according to the voltage averaging method, FIG. 4 is a circuit diagram of a liquid crystal matrix panel driving device according to an embodiment of the present invention, and FIG. FIG. 4 is a wiring diagram showing the detailed configuration of the selection/non-selection voltage generation circuit in the device; FIG. 6 is a circuit diagram showing an example of an electronic switch that can be used in the circuit of FIG. 5; FIGS. FIG. 8 is a time chart for explaining the operation of the circuits shown in FIGS. 4 and 5, and FIG. 9 is a graph showing an example of the temperature characteristics of the liquid crystal used in the circuit shown in FIG. 10...Liquid crystal matrix panel, 12...Scanning circuit, 14, 26, 49...Inverter, 16,
18, 28, 30, 40... Selection/non-selection voltage generation circuit, 20, 32, 50... Electronic switch circuit, 22... Series-parallel conversion circuit, 24... Line memory, 42... For determining applied voltage variable resistance, 4
3...Resistance voltage divider circuit, 51-54...Electronic switch pair.

Claims (1)

[Scope of Claims] 1. A liquid crystal matrix panel for driving a liquid crystal matrix panel having a plurality of scanning electrodes and signal electrodes arranged to intersect with each other so as to define a large number of matrix intersection points that are to become pixels. A resistive voltage divider circuit has a plurality of resistors connected between potential terminals and extracts a plurality of potential levels from the potential terminals or the connection point between the resistors, and a resistor voltage divider circuit that extracts a plurality of potential levels from the plurality of potential levels by a control signal. , an electronic switch circuit group that generates a drive voltage waveform to be supplied to the scanning electrode and/or a drive voltage waveform to be supplied to the signal electrode, wherein the number of resistors is 5, and each The resistance value has the following ratio from one potential terminal side to the other potential terminal side: 1:1:(a-4):1:1 (However, a is determined according to the optimum driving conditions. 1. A liquid crystal matrix panel driving device, characterized in that the liquid crystal matrix panel driving device is determined to substantially satisfy the following constant.