JPH0677188B2 - Liquid crystal matrix display device - Google Patents

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a liquid crystal matrix display device, and more particularly to improvement of a circuit for generating a drive voltage waveform thereof.

[Conventional technology]

Conventionally, it is known that a liquid crystal matrix panel is AC-driven by a line-sequential scanning method and a voltage averaging method. However, the applicant of the present application has previously described that the apparatus shown in FIG. A liquid crystal matrix panel display device as shown in JP-A-53-38935 has been proposed.

In FIG. 1, reference numeral 10 denotes a liquid crystal matrix panel having a plurality of scanning electrodes X1 to X4 and signal electrodes Y1 to Y4 which are arranged so as to intersect with each other so as to define a large number of matrix intersecting points to be pixels. The liquid crystal interposed between the counter electrodes at each matrix intersection changes the alignment state of liquid crystal molecules when the voltage applied to the liquid crystal exceeds a certain value (referred to as threshold voltage Vth), resulting in a light transmittance. Change. When displaying images on this type of panel, the scanning electrodes X1 to X4 are scanned by a line-sequential scanning method that matches the characteristics of the liquid crystal, while image signals are supplied to the signal electrodes Y1 to Y4. As a driving method in that case, an AC driving method called a voltage averaging method is preferably used in order to prevent unevenness of the excited state of the liquid crystal.

In the display device of FIG. 1 which employs the line-sequential scanning method and the voltage averaging method, 12 is a scanning circuit for generating a line-sequential scanning signal, and 16 and 18 are selection voltages as shown in FIG.
A voltage generation circuit for generating V _S1 and a non-selection voltage V _NS1 , respectively, and 20 for combining the voltages V _S1 and V _NS1 according to the line-sequential scanning signal to synthesize a driving voltage waveform to be supplied to each scan electrode.
Of the electronic switch circuit, 22 is a serial-parallel conversion circuit having an image signal input terminal 22a, 24 is a line memory for storing one row of image signals, and 28 and 30 are selection voltages V _S2 as shown in FIG. , A voltage generation circuit for respectively generating the non-selection voltage V _NS2 , 32 is a drive voltage waveform to be supplied to each signal electrode by combining the voltages V _S2 , V _NS2 in accordance with each bit state of the image signal from the line memory 24 Is a second electronic switch circuit for synthesizing The electronic switch circuit 20 has a pair of electronic switches 20a, 20b connected to each scanning electrode, a positive-phase scanning signal is applied to the control terminal of each one electronic switch 20a, and the other electronic switch 20a. A reverse-phase scanning signal is applied to the control terminal of the switch 20b via the inverter 14. The electronic switch pair alternately opens and closes so that when one switch is on, the other switch is off, and the common output side has a selection voltage as shown in FIG.
A scan electrode driving voltage waveform V _X consisting of a combination of V _S1 and the non-selection voltage V _NS1 is generated. The electronic switch circuit 32 is also configured similarly to the circuit 20 described above, each has a pair of electronic switches 32a, 32b connected to each signal electrode,
A positive-phase image signal is applied to the control terminal of each one of the electronic switches 32a, and an opposite-phase image signal is applied to the control terminal of each of the other electronic switch 20b via the inverter 26. . The pair of electronic switches 32a and 32b are opened and closed in the same manner as the electronic switches 20a and 20b described above, and a signal composed of a combination of the selection voltage V _S2 and the non-selection voltage V _NS2 as shown in FIG. A voltage waveform V _Y for driving the electrodes is generated. When driving voltages V _X and V _Y are applied to the liquid crystal matrix panel 10, the voltage actually applied to the liquid crystal has an AC waveform of V _X -V _Y as shown in FIG. 2, where A is in the selected state and B and C are The semi-selected state and D become the non-selected state.

In order to obtain the drive voltage waveform as shown in FIG. 2, a signal having two potential levels of V ₀ and 0 as the selection voltage V _S1 and 1 / aV ₀ (1 as the non-selection voltage V _NS1 −1 / a) V ₀ of 2
A signal having two levels is O and V ₀ as the selection voltage V _S2.
Signal having two levels of, as a non-selection voltage V _NS2 is
Signals with two levels of 2 / aV ₀ and (1-2 / a) V ₀ are required respectively, and the voltage generation circuits 16, 18, 28, 30 are composed of pulse oscillators that generate the respective signals. There is. It should be noted that a is a constant determined according to the driving conditions of the liquid crystal. For example, when the duty ratio is 1 / N as shown in Japanese Unexamined Patent Publication No. 50-68419, it is optimal. Is set near.

In the circuit of FIG. 1, in some cases by generating a drive voltage waveform V _X, V _Y, as shown in FIG. 3, the liquid crystal to V _X, V _Y becomes second
An AC waveform similar to that in the figure can be added. In this case, V _S1 is + (1-1 / a) V ₀ and − (1-1 / a) V
2 level signal _0, 0 level signal as V _NS1, respectively to generate an AC signal of ± 1 / aV ₀ of opposite phases as V _S2 and V _NS2.

[Problems to be Solved by the Invention]

However, in the above-described conventional device, (1) the internal configuration of the voltage generating circuits 16, 18, 28, 30 is complicated, so that it is not possible to cope with changes in device specifications, and (2) those voltage generating circuits are individually separated. However, the adjustment work for setting the optimum driving condition is complicated, and (3) it is difficult to standardize the circuit.

Further, as such a display device, Japanese Patent Application Laid-Open No. 52-55832
It is known to use a resistance voltage divider circuit as described in the publication. In this known technique, the number of resistors is 4, and the value of each resistor is from one potential terminal side to the other potential terminal side 1: 1: 1: 1 or the division ratio is arbitrarily set. To take The resistors are arranged so as to satisfy the ratio relationship of (n: duty ratio).

However, since the resistance voltage dividing circuit (1) can generate only five potential levels, six potential levels suitable for the optimum potential averaging method as shown in FIG. 2 cannot be generated.

(2) When arbitrarily setting the partial pressure ratio When It is necessary to adjust the values of the two resistors in total.

There are problems such as.

An object of the present invention is to solve this kind of problem, and to provide a liquid crystal matrix display device having a simple structure in which the driving conditions of the liquid crystal can be easily set and the circuit can be standardized.

[Means for Solving the Problems]

To summarize the features of the present invention, a circuit for generating a drive voltage to be supplied to the scan electrodes and a drive voltage to be supplied to the signal electrodes is configured as a single unit by a resistance voltage dividing circuit, The voltage of each potential level to be output is selected by the scan electrode switch circuit and the signal electrode switch circuit according to the combination of the sync signal and the scan signal and the sync signal and the image signal and applied to each electrode. is there.

And, the resistance voltage divider circuit, from one potential terminal side to the other potential terminal side, has the following ratio relationship 1: 1: (a-4): 1: 1 (However, a depends on the driving conditions. A constant greater than 4), which are connected to each other so that the potential of one potential terminal is the first potential and the potential of the other potential terminal is the second potential. The first potential and the second potential
When the potential difference between the potentials of V ₁ and V 2 is V ₀ (1-1 / a) V ₀ from the potential terminals or the connection points between the resistors, respectively, (1-2 / a)
Six potential levels V ₁ , V ₂ , which are V ₀ , 2 / aV ₀ , 1 / aV ₀ , 0,
_{V 3, V 4, V 5} , a structure for taking out the V _6.

Further, the scan electrode switch circuit receives the predetermined output of the resistance voltage dividing circuit, the synchronizing signal and the scanning signal as input, and when the synchronizing signal is at a predetermined level and the scanning signal is at the selection level V ₁ , the synchronizing signal is at the predetermined level. Select V ₅ when the scanning signal is at the non-selection level, V ₆ when the synchronization signal is at the opposite level and the scanning signal is at the selection level, and V ₂ when the synchronization signal is at the opposite level and the scanning signal is at the non-selection level. The voltage applied to the scan electrodes is output.

The signal electrode switch circuit inputs the predetermined output of the resistance voltage dividing circuit, the synchronizing signal and the image signal output from the line memory, and when the synchronizing signal is at the predetermined level and the image signal is at the selection level. V _6, when the image signal synchronization signal above a predetermined level, non-selection level V _4, when the synchronization signal is an image signal is selected level above opposite level V _1, the synchronization signal is an image signal by the inverse level non-selection level At this time, V ₃ is selected to output the voltage applied to the signal electrode.

[Action]

According to such a feature, since the resistance voltage dividing circuit composed of five resistors having a specific ratio relationship is used and six potential levels necessary for generating the selection / non-selection voltage are taken out, In addition to the standardization of the voltage dividing circuit, it is extremely easy to deal with the change of the device specification, and in particular, there is an advantage that the setting or change of the optimum driving condition is easy.

〔Example〕

Hereinafter, the present invention will be described in detail with reference to the embodiments shown in the accompanying drawings.

Referring to FIG. 4, there is shown a circuit configuration of a liquid crystal matrix display device according to an embodiment of the present invention. In the circuit of the same figure, the same parts as those in FIG. 1 are designated by the same reference numerals, and the operation of these parts is the same as that described above, and therefore will not be described in detail. For the sake of simplicity, in this example, the case of driving the 3 × 3 liquid crystal matrix panel 10 is taken up,
The configuration and operation of the voltage generating circuit 40, which is a feature of the present invention, will be described in detail. In FIG. 4, e ₁₁ , e ₁₂ ... e ₃₃ denote liquid crystal bodies or pixels located at the intersections of the matrix, V _{X1 to} V _X3 are voltages for driving the scan electrodes _{X1 to X3} , and V _{Y1 to} V _Y3 are Signal electrode Y1 ~
Indicates the voltage to drive Y3. Further, S1 to S3 indicate progressive scanning signals, and L1 to L3 indicate each bit of the image signal for one row.

The voltage generating circuit 40 for generating the selection voltage V _S1 and the non-selection voltage V _NS1 on the scanning side and the selection voltage V _S2 and the non-selection voltage V _NS2 on the signal side is configured as shown in FIG. It includes a voltage dividing circuit 43 and an electronic switch circuit 50. The resistance voltage dividing circuit 43 includes resistors 43A, 43B, 43C, 43D, 43E connected in series between the pair of potential points 44A and 44F, and the potential point 44A from the power supply terminal 41 via the variable resistor 42. The power supply voltage V _DD is applied, and the potential point 44F is connected to the O potential or the ground potential. The values of the resistors 43A, 43B, 43C, 43D, 43E are respectively set to R, R, (a-4) R, R, R in order to obtain the potential levels constituting the selection / non-selection voltages described above with reference to FIG. Selected, the resistance ratio is 1: 1: (a-4): 1: 1. In this way, by weighting each of the resistors 43A to 43E, the indirect resistance points 44B, 44C, 44D, and 44E have the potential at the potential point 44A set to V ₀ , 44F.
When it is set to O, (1-1 / a) V ₀ , (1
A potential of −2 / a) V ₀ , 2 / aV ₀ , 1 / aV ₀ can be obtained.

On the other hand, the electronic switch circuit 50 has four electronic switch pairs.
Electronic switches 51a and 51 which respectively constitute 51, 52, 53 and 54
b, 52a and 52b, 53a and 53b, 54a and 54b.
The output terminals of the electronic switches 51a and 51b are connected to the output terminal 55, the output terminals of the electronic switches 52a and 52b are connected to the output terminal 56, and the electronic switch 5 is connected.
The output terminals of 3a and 53b are connected to the output terminal 57 and electronic switches 54a and 54b.
The output terminals of are connected in common to the output terminal 58.
48 is a terminal for applying the clock signal CP during synchronization, and this terminal 48 is on the one hand the electronic switch 51a, 52b, 53b, 54b.
Of the electronic switches 51b, 52a, 53a, 54a via the inverter 49. As a result, the electronic switches of each electronic switch pair perform the opening / closing operation in the opposite phase according to the fact that when one is closed, the other is opened. The voltage V _{0 at the} potential point 44A is applied to one of the electronic switches 51a constituting the electronic switch pair 51, and the potential point is applied to the other electronic switch 51b.
The voltage O of 44F is supplied to each, and the selection voltage V _S1 on the scan electrode side is generated at the output terminal 55 according to the clock signal CP as shown in FIG. The voltage (1-1 / a) V _{0 at the} connection point 44B is applied to one of the electronic switches 52a that form the electronic switch pair 52, and the connection point 44E is applied to the other electronic switch 52b.
Voltage of 1 / aV ₀ is supplied to the output terminal 56
As shown in the figure, the non-selection voltage V _NS1 on the scan electrode side is generated according to the clock signal CP. The voltage V ₀ is supplied from the potential point 44A to one electronic switch 53a of the electronic switch pair 53, and the voltage O from the potential point 44F to the other switch 53b.
Therefore, as shown in FIG. 7, the selection voltage V _S2 on the signal electrode side is generated at the output terminal 57 according to the clock signal CP. Further, one of the electronic switches 54a of the electronic switch pair 54 is supplied with the voltage (1-2 / a) V _{0 at the} connection point 44C and the other electronic switch 54b is supplied with the voltage at the connection point 44D.
2 / aV ₀ is supplied from the output terminal 58, as shown in FIG. 7, in response to the clock signal CP, the non-selection voltage V on the signal electrode side.
_NS2 is obtained.

As each electronic switch shown in FIGS. 4 and 5, an electronic switch composed of a complementary metal oxide semiconductor (CMOS) integrated circuit as shown in FIG. 6 can be used. In FIG. 6, IN is an input terminal, OUT is an output terminal, V _C is a control terminal, and V _S3 is a source power supply.

Here, the overall operation of the liquid crystal matrix display device of FIG. 4 will be described in detail with reference to FIG.

The clock signal CP shown in FIG. 8 is generated from a clock circuit (not shown in FIG. 4) and supplied to the scanning circuit 12, the series-parallel conversion circuit 22, and the electronic switch circuit 50, respectively. The clock signal CP is a pulse signal with a duty ratio of 1/2, and its cycle is set to the scanning time width for one row.

As shown in FIG. 8, a scanning signal is generated according to the clock signal CP.
S1, S2, S3 are generated from the scanning circuit 12. Now pixel e ₁₃ ,
Assuming that lighting a e _22, e _31, the image signal is generated from the line memory 24 as shown in FIG. 8 L1, L2, L3.
When S1 and L3 are at the H level, the drive voltages V _X1 and _Y3 are formed as the selection voltages V _S1 and V _S2 , respectively, so that the pixel e ₁₃ is displayed. Similarly, when S2 and L2 are at the H level, the pixel e ₁₃ is displayed. e ₂₂ is displayed, and pixel e ₃₁ is displayed when S3 and L1 are at the H level.
Voltages similar to the respective applied voltages V _X1 and V _Y1 to the electrodes X1 and Y1 shown as an example in FIG. 8 are applied to the scan electrodes and the signal electrodes related to the pixels that are not illuminated or displayed, The pixel is in a semi-selected state or a non-selected state.

That is, the electronic switch pair 51 and 52 of the electronic switch circuit 50 and the electronic switch circuit 20 of the present embodiment, the scanning electrode
A scan electrode switch circuit for applying a voltage of a predetermined level to X1 to X3 is formed. Further, by the electronic switch pair 53 and 54 of the electronic switch circuit 50 and the electronic switch circuit 32,
A signal electrode switch circuit for applying a voltage of a predetermined level to the signal electrodes Y1 to Y3 is formed. Specifically, the scan electrode switch circuit selects the potential level shown in Table 1 according to the combination of the binary states (H, L levels) of the clock signal CP and the scan signals S1 to S3 to select each scan electrode X1. Apply to ~ X3. On the other hand, the signal electrode switch circuit uses the clock signal CP and the image signal.
The potential levels shown in Table 2 are selected according to the combination of the binary states (H, L levels) of L1 to L3, and the signal electrodes Y1 to Y3 are selected.
Apply to. As a result, each pixel e has image signals L1 to L3.
AC drive is performed by the potential averaging method in accordance with.

The scan electrode switch circuits (51, 52, 20) and the signal electrode switch circuits (53, 54, 53) of this embodiment shown in FIGS.
32) shows that each electrode has a two-stage electronic switch pair.
The point is that a switch circuit that selects a potential level according to the conditions in Table 1 or Table 2 and applies it to various electrodes may be used.
For example, a plurality of electronic switches having the respective potentials shown in Table 1 or 2 as inputs are combined and connected to a scan electrode or a signal electrode, and those electronic switches are connected to a clock CP and a scan signal S or a clock signal CP. It can be realized by turning on and off according to the combination of the image signals L.

As described above in detail, according to this embodiment, the configuration of the selection / non-selection voltage generation circuit is simple.

Further, since the resistance voltage dividing circuit 43 is used, one of the reference potentials V ₀ can be easily changed by directly changing the magnitude of the power supply voltage V _DD or by changing the value of the resistor 42.

By changing the reference voltage V ₀ , the brightness and contrast of the liquid crystal can be adjusted. In this case, in particular, the use of the variable resistor 42 is a good measure because it is possible to easily deal with the change of the device specification regarding V ₀ .

In addition, setting or changing the optimum driving conditions is done with a single resistor.
It can be easily implemented by simply adjusting 43C, and in this respect also it has high flexibility for various device specifications.

The present invention is not limited to the above embodiments and can be implemented in various modified forms. For example, instead of or in addition to the variable resistor 42 in the circuit of FIG. 5, a temperature-sensitive resistor can be connected between the power supply terminal 41 and the potential point 44A,
In such a case, if the temperature-sensitive resistance is specified so that its resistance-temperature characteristic corresponds to the temperature change of the threshold voltage Vth of the liquid crystal shown in FIG. 9, the temperature change of the threshold voltage is automatically detected. It is extremely useful because it can be compensated.

〔The invention's effect〕

As described above, according to the present invention, it is possible to easily set the driving conditions of the liquid crystal, and it is necessary to generate the selection / non-selection voltage.
It is possible to obtain a liquid crystal matrix display device having a simple structure in which a resistance voltage dividing circuit for extracting one potential level can be standardized.

[Brief description of drawings]

FIG. 1 is a circuit diagram of a liquid crystal matrix display device according to the prior art, and FIGS. 2 and 3 are waveform diagrams showing drive voltage waveforms when the device of FIG. 1 is AC-driven according to the voltage averaging method. FIG. 4 is a circuit diagram of a liquid crystal matrix display device according to an embodiment of the present invention, and FIG. 5 is a connection diagram showing a detailed configuration of a selection / non-selection voltage generation circuit in the device of FIG.
FIG. 6 is a circuit diagram showing an example of an electronic switch that can be used in the circuit of FIG. 5, FIGS. 7 and 8 are FIGS.
Time chart for explaining the operation of the circuit shown in FIG.
The figure is a graph showing an example of the temperature characteristics of the liquid crystal used in the circuit of FIG. 10 ... Liquid crystal matrix panel, 12 ... Scanning circuit, 14, 26,
49 …… Inverter, 16,18,28,30,40 …… Selection / non-selection voltage generation circuit, 20,32,50 …… Electronic switch circuit, 22 …… Series-parallel conversion circuit, 24 …… Line memory, 42 …… Variable resistance for determining applied voltage, 43 …… Resistor voltage dividing circuit, 51-54 …… Electronic switch pair.

Claims (1)

[Claims] 1. A liquid crystal matrix panel having a plurality of scanning electrodes and signal electrodes which are arranged so as to intersect with each other so as to define a large number of matrix intersection points to be pixels, and a scanning circuit for generating a scanning signal, 1. A line memory for storing image signals for one row and one from the potential terminal side to the other potential terminal side, the following ratio relationship 1: 1: (a-4): 1: 1 (where a is 5 connected and defined so as to substantially satisfy a constant greater than 4 defined according to the driving conditions.
Has two resistors, the potential of one potential terminal is the first potential,
When the potential of the other potential terminal is the second potential and the potential difference between the first potential and the second potential is V ₀ , from the potential terminal or the connection point between the resistors, the first potential or the first potential Two
Potential difference from the potential of V ₀ , (1-1 / a) V ₀ , (1
-2 / a) 6 potential levels V ₀ , 2 / aV ₀ , 1 / aV ₀ , 0
_1, and a _{V 2, V 3, V 4} , V 5, V 6 and taken out as the the resistor divider, and inputs the predetermined output a synchronization signal and the scanning signal of the resistance voltage dividing circuit, the synchronization signal Is a predetermined level and the scanning signal is at the selection level, V ₁ ; when the synchronization signal is the above-mentioned level and the scanning signal is at the non-selection level, V ₅ ; when the synchronization signal is at the opposite level and the scanning signal is at the selection level, V _{6 is} the synchronization signal. Is the reverse level and the scanning signal is at the non-selection level, select V ₂ respectively,
A scan electrode switch circuit that outputs a voltage applied to the scan electrodes, a predetermined output of the resistance voltage dividing circuit, the synchronization signal, and an image signal output from the line memory are input, and the synchronization signal has the predetermined level. When the image signal is at the selected level with V ₆ ,
When the sync signal is at the above predetermined level and the image signal is at the non-selection level V ₄ , when the sync signal is at the above reverse level and the image signal is at the select level V ₁ , when the sync signal is at the above opposite level and the image signal is at the non-select level A liquid crystal matrix display device, comprising: a signal electrode switch circuit for selecting V ₃ and outputting a voltage applied to the signal electrode.