JP2001013478A - Source driver for liquid crystal display device and liquid crystal display device using the same - Google Patents

Abstract

PROBLEM TO BE SOLVED: To obtain a source driver for a liquid crystal display device which is capable of eliminating the supply of reference voltages for gamma correction from outside and improving image quality by forming the reference voltages for gamma correction by resistance division and selecting a resistor used for resistance division from plural resistors. SOLUTION: When a switch of an external power source turns on and an enable signal E goes to an 'H', a resistor 11 for setting the gamma correction operates and a selector 51 does not operate. The reference voltages V0 to V9 are passed through amplifiers 31 to 49 and are further resistance divided by the divided resistors 53 to 69 for setting the gradation voltages. When the enable signal E goes to an 'L', the resistor 11 for setting the gamma correction does not operate any more and in turn the selector 51 operate. The selector 51 selects the gradation voltages corresponding to display data and outputs the same to prescribed data lines of a liquid crystal display panel. As a result, the liquid crystals in the liquid crystal panel are driven by 64 stages of the gradation voltages formed by the divided resistors 53 to 69 for setting the gradation voltages.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[0001] 1. Field of the Invention [0002] The present invention relates to a source driver for a liquid crystal display device, and more particularly, to generation of a gamma (γ) correction reference voltage in a source driver for a liquid crystal display device.

[0002]

2. Description of the Related Art Liquid crystal display devices, which can save space and power as compared with CRTs, have been used in various applications as computer display devices and the like. In recent years, a liquid crystal display device has been required to have a larger screen and higher image quality according to the application. As a method of improving the image quality of the liquid crystal display device, there is a method of optimizing a gamma correction value. Gamma correction is a method of correcting a liquid crystal driving voltage in accordance with the voltage-transmittance characteristics of the liquid crystal, and a more natural gradation display corresponding to input display data can be performed by the correction.

FIG. 9 shows an outline of a conventional liquid crystal display device.
As shown in FIG. 9, a gate driver 307 is connected to a plurality of gate lines 308 of the liquid crystal display panel 309. The source driver 3 is connected to the plurality of data lines 310.
11 and 313 are connected. FIG. 9 shows one gate driver and two source drivers, but the number is arbitrary. The power supply generation circuit 303 and the control signal generation circuit 301 are connected to the gate driver 307. A predetermined voltage (for example, 20 V and −5 V) is supplied from the power generation circuit 303 to the gate driver 307.
To enter. Further, a predetermined control signal is input from the control signal generation circuit 303 to the gate driver 307.

[0004] Source drivers 311 and 313 include:
The control signal creation circuit 301, the power supply creation circuit 303, and the reference voltage generation circuit 305 are connected. From the control signal generation circuit 301 to the source drivers 311 and 313, 6-bit display data (R0-5, G0-5, B0-5) for each color of red (R), green (G), and blue (B). And a clock signal CK are output. Further, a predetermined voltage (for example, +12 V) is applied from the power supply generation circuit 303 to the source drivers 311 and 313. Further, the source drivers 311 and 31
3, a reference voltage for gamma correction is output. For example, a signal from a computer is input to the control signal creation circuit 301, and power is supplied to the power supply creation circuit 303 from an external power supply.

FIG. 10 shows a configuration example of a reference voltage generation circuit 305 for gamma correction. In the example shown in FIG.
This shows that ten reference voltages 0 to V9 are generated by resistance division between the voltages VDD to 0V. The resistance values of the eleven resistors (indicated by “□” in FIG. 10) are adjusted so that reference voltages V0 to V9 matching the voltage-transmittance characteristics of the liquid crystal used for the liquid crystal display panel 309 are generated. Have been. For example, in FIG. 10, a resistor having a resistance value of 1.5R is connected between the outputs of the reference voltages V0 and V1, a resistor having a resistance value of R is connected between the outputs of the reference voltages V1 and V2. Are connected to each other between the outputs.

Returning to FIG. 9, the operation of the conventional liquid crystal display will be briefly described. Display data of R (red), G (green), and B (blue) is input from an external device such as a computer, and the control signal creation circuit 301 sends the display data (R0-
5: G0-5: B0-5) and the clock signal CK to the source drivers 311 and 313. The control signal generation circuit 301 outputs a predetermined control signal to the gate driver 307, for example, for line-sequential driving. Also,
The power supply generation circuit 303 receives power from an external power supply, generates necessary voltages in the source drivers 311 and 313, the gate driver 307, and the like, and outputs the voltages. The reference voltage generation circuit 305 generates a gamma correction reference voltage with the circuit configuration shown in FIG. 10 and outputs it to the source drivers 311 and 313.

The source drivers 311 and 313 select the gamma correction reference voltage input from the reference voltage generation circuit 305 based on the display data input from the control signal generation circuit 301, and select a gamma correction reference voltage from the liquid crystal display panel 309. Is output to the data line 310. On the other hand, gate driver 3
07 according to the control signal from the control signal generation circuit 301,
A predetermined gate line 308 of the liquid crystal display panel 309 is driven at a predetermined timing. In this manner, one of the gamma correction reference voltages is output to the predetermined data line 310 of the liquid crystal display panel 309, and the liquid crystal of the pixel at the intersection of the predetermined data line 310 and the driven gate line 308 is subjected to the gamma correction. Driven by the correction reference voltage.

Since the reference voltage generation circuit 305 described with reference to FIGS. 9 and 10 generates voltages in ten stages, it is possible to display five gray scales on each of the positive electrode side and the negative electrode side. In order to perform finer gradation display, it is necessary to generate reference voltages in more stages. However, in the configuration in which the reference voltage generation circuit 305 is provided outside the source drivers 311 and 313 as shown in FIG. 9, the number of signal lines for supplying a large number of generated reference voltages to each source driver increases. Problem arises. Also,
Due to the recent reduction in the area of the printed wiring board, the reference voltage wiring and the control signal wiring have to be arranged close to each other. For this reason, the logic noise of the control signal is superimposed on the reference voltage due to the capacitive coupling between the wirings arranged close to each other, and the reference voltage fluctuates when the liquid crystal display panel is driven, thereby deteriorating the display quality. There is a problem that.

Some conventional source drivers include a gamma correction reference voltage generating circuit. When the reference voltage is generated in the source driver, no problem occurs due to an increase in the number of signal wirings. However, the source
If the gamma correction reference voltage generation circuit is incorporated in the driver, it becomes difficult to change the level of the reference voltage, and the work of adjusting the reference voltage based on a desired gamma correction value becomes complicated. Occurs.

[0010]

SUMMARY OF THE INVENTION An object of the present invention is to provide a source driver for a liquid crystal display device which can eliminate the supply of a reference voltage for gamma correction from the outside and improve the image quality. Another object of the present invention is to provide a source driver for a liquid crystal display device which can eliminate the supply of a reference voltage for gamma correction from the outside and can generate a reference voltage more matched with the voltage-transmittance characteristic of the liquid crystal.

[0011]

SUMMARY OF THE INVENTION An object of the present invention is to provide a source driver for a liquid crystal display device, wherein a reference voltage generating circuit for generating a gamma correction reference voltage by resistance division and a plurality of resistors are used for the resistance division. And a resistance setting circuit for selecting a resistance. According to the configuration of the present invention, since a plurality of reference voltages are generated inside the source driver without being supplied from the outside, the number of reference voltages is increased without increasing the number of wirings connected to the source driver. This makes it possible to generate a reference voltage that more closely matches the voltage-transmittance characteristics of the liquid crystal, thereby improving image quality.

In the source driver for a liquid crystal display device according to the present invention, the resistor setting circuit may select the resistor based on an external setting signal. Further, the resistance setting circuit may receive the setting signal in response to the start of power supply to the device.
Furthermore, the plurality of resistors may be configured to be connected in parallel between a plurality of gamma correction reference voltage output lines.

[0013]

DESCRIPTION OF THE PREFERRED EMBODIMENTS A source driver for a liquid crystal display according to an embodiment of the present invention will be described with reference to FIGS. First, a method of setting a reference voltage generated inside the source driver according to a signal from an external source driver according to the present embodiment will be described with reference to FIGS. FIG. 1 shows a schematic configuration of a reference voltage generation circuit and a resistance setting circuit in a source driver for a liquid crystal display device. At the time of image display, display data lines (here, 6 of D0 to D5) from which display data of each color of R, G, and B are output.
Bit) branches off and is connected to the data selector 101. To the display data line at the time of setting the reference voltage, resistance setting data for turning on or off a switch described later is output instead of the display data. Further, a clock signal line CK and an enable signal line E are connected to the data selector 101.

The data selector 101 is connected to latches 103 and 105 for latching the resistance setting data input thereto. In the example shown in FIG. 1, 3-bit latches 103 and 105 are used, and 6-bit resistance value setting data can be used. The enable signal E is input to the latches 103 and 105 via the data selector 101.

The voltage VDD and the voltage 0 V are input to the reference voltage generation circuit of the source driver.
Switches (S0 to S5) 119 to 129 and resistors 107 to 117 are connected between −0V. On the voltage VDD side, three resistors (resistance value R; hereinafter abbreviated as R) 10 in parallel
7, (resistance value 2 × R; hereinafter abbreviated as 2R) 109 and (resistance value 3 × R; hereinafter abbreviated as 3R) 111 are connected.
One end of the switch (S0) 119 is connected to the next stage of the resistor (R) 107, one end of the switch (S1) 121 is connected to the next stage of the resistor (2R) 109, and the resistor (3R) 11
One end of the switch (S2) 123 is connected to the stage next to the first stage. Switches (S0, S1, S2) 119, 12
The other ends of the first and the 123 are connected in common, and 3
Resistor (R) 113, resistor (2R) 115, resistor (3
R) 117 are connected in parallel. Resistance (R) 113
One end of the switch (S3) 125 is connected to the next stage of
One end of the switch (S4) 127 is connected to the next stage of the resistor (2R) 115, and one end of the switch (S5) 129 is connected to the next stage of the resistor (3R) 117. The other ends of the switches (S3, S4, S5) 125, 127, 129 are commonly connected and connected to the voltage 0V side.

The switches (S0, S1, S2) 11
9, 121, 123 and three resistors (R, 2R,
3R) The reference voltage V1 is taken out from a common connection point with 113, 115 and 117. Switches (S0 to S5) 119 to 129 correspond to the bits L0 to L5 held in the latches 103 and 105, respectively, and the switches (S0 to S5) 119 to 129 correspond to the values held in the bits L0 to L5. 129 is turned on or off. In this example, the latches 103 and 105
The switch is turned on when the bit value held in is "1", and turned off when the bit value is "0".
At least the latches 103 and 105 and the switch (S
0 to S5) 119 to 129 constitute a resistance setting circuit.

The operation of the reference voltage generation circuit having the above configuration will be described with reference to FIG. Data selector 1
01 (see FIG. 2A) during the period when the enable signal E input to H.01 is "H" (high).
When K is captured by the data selector 101 (see FIG. 2B), the resistance setting data (D0 to D5) transmitted on the display data line in synchronization with, for example, the rising edge of the clock signal CK. Is latched by the latches 103 and 105 from the data selector 101. In the example of FIG. 2, the data D0 and D3 are "H" and the data D
1, D2, D4, and D5 are in the “L” (low) state (see FIGS. 2C to 2H). Therefore, in the example, the bit values L0 to L5 latched by the latches 103 and 105 are 100100, the switches S0 and S3 are turned on, and the switches S1, S2, S4 and S5 are turned off (FIG. 2 (i) and ( j)). As a result, the output reference voltage V1 (see FIG. 1) is
Thus, the resistance between the voltage VDD-0V is divided.
After the reference voltage V1 is set in this manner, FIG.
As shown in (a), the enable signal E is set to "L", and display data for gradation display is output from the computer side to the display data signal line. When the enable signal E becomes "L", the reference voltage generation circuit shown in FIG. 1 does not operate and maintains the output of the set reference voltage V1.

The switch (S0) provided in the circuit
.About.S2) When all of the switches 119 to 123 are off, or when all of the switches (S3 to S5) 125 to 129 are off, the reference voltage V1 cannot be generated by resistance division, so that the switches (S0 to S2) One of the switches 119 to 123 is turned on, and the switches (S3 to S5) 1
The values of the resistance value setting data (D0 to D5) are selected so that any one of 25 to 129 is turned on. Under such conditions, the resistance setting data (D0 to D5)
Can be used to obtain a multi-stage reference voltage V1.

Next, a liquid crystal display device using a source driver having a built-in reference voltage generating circuit according to the present embodiment described with reference to FIGS. 1 and 2 will be described with reference to FIGS. FIG. 3 shows an outline of the liquid crystal display device according to the present embodiment, corresponding to FIG. 9 showing a conventional example.
The liquid crystal display panel 309 and the gate driver 30 in FIG.
7 is the same as that shown in FIG. A plurality of gate lines 308 of the liquid crystal display panel 309
Is connected to the gate driver 307.

The plurality of data lines 310 are connected to the source drivers 5 and 7 described in this embodiment. The power supply generation circuit 3 and the control signal generation circuit 1 are connected to the gate driver 307. Power supply creation circuit 3
, A predetermined voltage signal is input to the gate driver 307, and a predetermined control signal is input to the gate driver 307 from the control signal generation circuit 1. Source driver 5
And 7 are connected to a control signal generation circuit 1 and a power supply generation circuit 3, and a predetermined voltage signal (V
DD), display data (R0-5, G0-5, B0-5), an enable signal E, and a clock signal CK are input from the control signal generation circuit 1. A predetermined voltage from an external power supply (not shown) is supplied to the power supply generation circuit 3, and an external signal including display data from a computer is input to the control signal generation circuit 1, for example. As shown in FIG. 3, in the liquid crystal display device according to the present embodiment, the reference voltage generation circuit for gamma correction is not provided outside the source drivers 5 and 7. Further, an enable signal E is output from the control signal generation circuit 1.

FIG. 4 is a signal waveform diagram showing the operation of the liquid crystal display device shown in FIG. When the switch of the external power supply is turned on (see FIG. 4A), the control signal generation circuit 1 sets the enable signal E to "H" for a predetermined period (see FIG. 4B). When the enable signal E is in the “H” state,
The clock signal CK functions as a resistance value setting data capturing clock for the source drivers 5 and 7 (see FIG. 4C). For example, in synchronization with the rising edge of the clock signal CK, the control signal generation circuit 1 outputs resistance setting data on the display data lines (R0-5, G0-5, B0-5) (FIG. d)). As a result, the source drivers 5 and 7 set the resistance values in the resistance dividing circuit described with reference to FIG. Then, after the enable signal E becomes "L", the clock signal CK functions as a display data capture clock for the source drivers 5 and 7 (see FIG. 4C), and the display data is displayed on the display data line. This is output (see FIG. 4D). The source after the enable signal E becomes "L"
The operations of the drivers 5 and 7 and the gate driver 307 are the same as the operation of the normal driver, and the description is omitted.

Next, a more specific configuration example of the source driver 5 shown in FIG. 3 will be described with reference to FIG. The signal (voltage) input to the source driver 5 is the display data (RG
B data), a clock signal CK, an enable signal E, a voltage VDD, and a voltage 0V. On the other hand, the data lines 1 to 300 of the liquid crystal display panel 309 are transmitted from the source driver 5.
The gray scale display data is output to the CPU. In this example, it is assumed that one source driver 5 drives 300 data lines, but the number of data line drives can be changed to any number.

The source driver 5 shown in FIG. 5 outputs, for example, a voltage capable of driving the liquid crystal of the liquid crystal display panel 309 at 64 gradations. In this embodiment, the voltage applied to the common electrode on the opposing substrate is kept constant, and the voltage of the pixel electrode on the array substrate on which the switching element is formed is constant, because the liquid crystal is AC driven by inverting the voltage applied to the liquid crystal. With respect to the common potential in a predetermined cycle (for example,
AC drive is performed in which the inversion is performed in units of a horizontal scanning period or a frame cycle. The display data, the clock signal CK, and the enable signal E are input to the gamma correction setting register 11 and the selector 51 in the source driver 5. On the other hand, the voltage VDD and the voltage 0V are resistance-divided by the resistor functioning as the reference voltage generation circuit and the switches 13 to 29 in the present embodiment, and generate 10 types of reference voltages V0 to V9. The gamma correction setting register 11 in FIG. 5 corresponds to the data selector 101 in FIG.
And latches 103 and 105. The resistors and switches 13 to 29 correspond to the arrangement of the resistors and switches provided in parallel in FIG. For example, as shown in FIG. 6, the inside of the resistor and the switch 13 is connected to a voltage line V0-V1.
Resistors R1, R2, and R connected in parallel between
3 and a switch S at the next stage of each of the resistors R1, R2 and R3.
In the case where W1, SW2 and SW3 are connected, the data selector 101 and the latch 1 shown in FIG.
Reference numerals 03 and 105 specifically have a configuration as shown in FIG. The switches SW1, SW2, SW3 shown in FIG.
And the latch shown in FIG. 7 constitute at least a resistance setting circuit.

Each of the reference voltages V0 to V9 is
To 49. Outputs of the amplifiers 31 to 49 are input to gradation voltage setting division resistors 53 to 69. The gradation voltage setting dividing resistors 53 to 69 are V0, V1, and V1.
And V2, V2 and V3, V6 and V7, V7 and V8, and V8 and V9, respectively, are divided by, for example, 16 resistors as shown in FIG. 8 (FIG. 8 shows V0-V1). ,
The area between V3 and V4 and between V5 and V6 are divided by 15 resistors in the same manner as shown in FIG. 8 to generate a total of 64 gradation voltages. That is, between V0 and V1, appropriately selected resistors 53a to 53p, between V1 and V2, properly selected resistors 55a to 55p, and between V2 and V3, properly selected resistors 57a. ５７57p, between V3 and V4 are appropriately selected resistors 59a〜59o, V5 and V6
Are properly selected resistors 63a to 63o, and between V6 and V7 are properly selected resistors 65a to 65p, V
7 and V8 between appropriately selected resistors 67a-67
p, between V8 and V9 are appropriately selected resistors 69a-69.
69p are provided. There is no resistance division between V4 and V5. By setting the common potential to an intermediate potential between V4 and V5, for example, the reference voltage V0 to V4 and the positive polarity 6
Four gradations and 64 gradations of negative polarity can be obtained with reference voltages V5 to V9. The 64 levels of gradation voltages are supplied to the selector 5
1, the selector 51 selects one of the 64 levels based on the display data and outputs it to one data line (one of Out1 to 300). It should be noted that the block 71 is conventionally the source driver 5
The components that existed within.

Next, the operation of the source driver 5 shown in FIG. 5 will be described. When the switch of the external power supply is turned on, the enable signal E becomes “H” for a predetermined period. When the enable signal E becomes “H”, the gamma correction setting register 11 operates, and the selector 51 does not operate. When the enable signal E becomes “H”, resistance setting data appearing on the display data line is input to the gamma correction setting register 11 in accordance with the clock signal CK. For example, in the case where a circuit including three resistors and three switches as shown in FIG. 6 is present in each of the resistors and the switches 13 to 29, a 27-bit resistance value for a total of 27 switches The setting data is input. The resistance and the switch 1 serving as the reference voltage generation circuit in the present embodiment correspond to the bit value of the input resistance value setting data.
Turn on or off each of the switches 3 to 29. When the resistances and the resistances of the switches 13 to 29 are set in this way, reference voltages V0 to V9 defined based on the resistances are determined. The reference voltages V0 to V9 are supplied to the amplifiers 31 to 4
9, the divided resistors 53-6 for gradation voltage setting
At 9, resistance division is performed.

When the enable signal E becomes "L", the gamma correction setting register 11 does not operate, and the selector 51 operates instead. Display data lines include R, G, B
Is output, and according to the clock signal CK,
Display data is input to the selector 51. Selector 5
1 selects a gradation voltage corresponding to the display data and outputs it to a predetermined data line 308 of the liquid crystal display panel 309. As a result, the liquid crystal in the liquid crystal display panel 309 is driven by the 64 steps of gradation voltages generated by the gradation voltage setting division resistors 53 to 69.

The present invention is not limited to the above embodiment, but can be variously modified. For example, in the above-described embodiment, each of the resistors and the switches 13 to 29 will be described as an example in which three resistor selection circuits of a resistor R1 and a switch SW1, a resistor R2 and a switch SW2, and a resistor R3 and a switch SW3 are provided in parallel. However, the number of resistance selection circuits is not limited to three. After the reference voltages V0 to V9 are set, the resistance is further divided by a fixed resistance ratio in the gradation voltage setting division resistors 53 to 69. For example, the gamma correction setting register 11 and the resistors and You may make it set with the switches 13-29. The number of gradation levels is not limited to 64, but may be smaller or larger. Although the description has been given using the enable signal E, for example, a predetermined period after the external power supply is turned on is set in advance as a setting period of the gamma correction reference voltage, and the setting is performed without using the enable signal E. It is also possible.
However, if the enable signal E is provided, it can be set at an arbitrary time.

In the above-described embodiment, the liquid crystal is AC-driven by inverting the potential on the display electrode side while keeping the common potential constant. However, the present invention is not limited to this. Of course, the present invention can also be applied to AC driving by so-called common inversion in which the inversion is performed in a period unit or a frame cycle. In this case, for example, each of the gradation voltage setting divided resistors 53 to 69 shown in FIG. 5 is divided by seven resistors a to g, and the seven resistors 6 are also provided between V4 and V5.
1a to 61g, the reference voltages V0 to V
In step 9, a voltage of 64 steps may be obtained. In this way, when the common potential is, for example, 0 V, a positive gradation of 64 can be obtained, and when the common potential is VDD, a negative 64 gradation can be obtained.

[0029]

As described above, according to the present invention, the supply of a reference voltage for gamma correction from the outside to the source driver for a liquid crystal display device is eliminated, and a reference voltage that is more matched to the voltage-transmittance characteristic of the liquid crystal is eliminated. Since it can be set, the image quality can be improved.

[Brief description of the drawings]

FIG. 1 is a block diagram illustrating an internal structure of a source driver according to an embodiment of the present invention.

FIG. 2 is a signal waveform diagram for explaining the operation of FIG. (A) shows the enable signal E, (b) shows the clock signal CK, (d) to (h) show the data on the display data line, and (i) shows the on / off state of the switches S0 and S3 (the on state is High) and (j) are switches S1, S2,
Change the ON / OFF state of S4 and S5 (ON becomes high)
Are respectively shown.

FIG. 3 is a block diagram of the entire liquid crystal display device according to one embodiment of the present invention.

FIG. 4 is a signal waveform diagram for explaining the operation of FIG. 3;
(A) shows the on / off state of the external power supply, (b) shows the enable signal E, (c) shows the clock signal, and (d) shows the data output state on the display data line.

FIG. 5 is a block diagram of a source driver according to an embodiment of the present invention.

FIG. 6 is a diagram illustrating an example of a resistor and a switch 13 in FIG. 5;

FIG. 7 is a diagram illustrating an example of a gamma correction setting register 11 in FIG. 5;

8 is a diagram showing in detail a part of a gradation voltage setting divisional resistor in FIG. 5;

FIG. 9 is a diagram showing an outline of a liquid crystal display device according to the related art.

10 is a diagram showing a configuration of a reference voltage generation circuit 305 in FIG.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 Control signal creation circuit 3 Power supply creation circuit 5, 7 Source driver 11 Gamma correction setting register 13, 15, 17, 19, 21, 23, 25, 27, 2
9 Resistance and switch 31, 33, 35, 37, 39, 41, 43, 45, 4
9 Amplifier 51 Selector 53a-g, 55a-g, 57a-g, 59a-g, 6
1a-g, 63a-g, 65a-g, 67a-g, 69
a-g Tone voltage setting division resistor 101 Data selector 103, 105 Latch 107, 109, 111, 113, 115, 117 Resistance 119, 121, 123, 125, 127, 129 Switch 307 Gate driver 308 Gate line 309 LCD panel 310 data line

 ──────────────────────────────────────────────────続 き Continued on the front page F term (reference) 2H093 NA16 NA32 NA33 NA43 NA53 NC04 NC11 NC26 NC62 ND06 ND49 ND58 5C006 AA01 AA16 AA22 AC27 AC28 AF42 AF44 AF46 AF51 BF24 BF43 FA18 FA21 5C080 AA10 BB05 CC03 DD03 EJ29 JJ03 JJ03

Claims (5)

[Claims] 1. A source driver for a liquid crystal display device, comprising: a reference voltage generation circuit for generating a gamma correction reference voltage by resistance division; and a resistance setting circuit for selecting a resistance used for the resistance division from a plurality of resistors. A source driver for a liquid crystal display device, comprising: 2. The source driver for a liquid crystal display device according to claim 1, wherein the resistance setting circuit selects the resistance based on an external setting signal. ·driver. 3. The liquid crystal display device according to claim 2, wherein the resistance setting circuit receives the setting signal in response to a start of power supply to the device. Source driver for 4. A source driver for a liquid crystal display device according to claim 1, wherein said plurality of resistors are connected in parallel between a plurality of gamma correction reference voltage output lines. A source driver for a liquid crystal display device. 5. A liquid crystal display device comprising the source driver for a liquid crystal display device according to claim 1.