JP2009216813A - Display - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a display can reduce a difference in luminance between images occurring when alternating current driving is carried out by using a multi-output source driver. <P>SOLUTION: When a scanning signal in an active state is switched to that in an inactive state and a TFT 112 in an on-state is changed to that in an off-state, a polarity switch control signal REV is reversed from a high level to a low level. Therefore, a period required for changing the on-state of the TFT 112 to the off-state can be delayed, and during the period, a rise of the voltage of a video signal AV for driving is applied to a pixel electrode Ep. Consequently, a voltage applied to a pixel capacity Clc can be brought close to a target voltage, and a luminance difference between images displayed on a liquid crystal panel 110 can be reduced. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to an active matrix display device, and more particularly, to an AC drive active matrix display device including a multi-output source driver.

  Conventionally, frame rate control (hereinafter referred to as “FRC”) is known as a technique for artificially generating intermediate gradations. FRC is a technique that utilizes rewriting of the screen for each frame and the afterimage effect of the retina. For example, by alternately displaying an L0 gradation screen and an L1 gradation screen for each frame, the FRC is applied to the human eye. An intermediate gradation between the gradation and the L1 gradation can be seen.

  FIG. 20 is a diagram showing a method of displaying a vertical gradation on the liquid crystal panel 510 by artificially creating an intermediate gradation between the L24 gradation and the L25 gradation by FRC. Referring to FIG. 20, by using the pattern of the L24 gradation and the pattern of the L25 gradation, the L24 gradation, the L24.25 gradation, the L24.5 gradation, the L24.75 gradation, and the L25 gradation are used. A method for displaying each pattern on the liquid crystal panel 510 by vertical gradation will be described.

  The liquid crystal panel 510 is divided into six regions in the horizontal direction, and each region is driven by six source drivers 521 to 526, respectively. Further, since each area is composed of two areas divided into left and right, the liquid crystal panel 510 is divided into 12 areas in the horizontal direction.

  When the liquid crystal panel 510 is driven line-sequentially, the pattern in the first row is displayed in L24 gradation because all 12 areas have L24 gradation in order from the top. The pattern in the second row is displayed in L24.25 gradation because 9 out of 12 areas have L24 gradation and 3 have L25 gradation. The pattern in the third row is displayed in L24.5 gradation because 6 of the 12 areas are L24 gradation and 6 are L25 gradation. Similarly, the pattern on the fourth line is displayed with a gradation of L24.75, and the pattern on the fifth line is displayed with a gradation of L25. As a result, a vertical gradation composed of a pattern that changes from the L24 gradation to the L25 gradation by L0.5 gradation for each row is displayed.

  In addition, the liquid crystal has a property of deteriorating when a DC voltage is continuously applied. For this reason, in the liquid crystal display device, an AC voltage is applied to the liquid crystal layer. The application of the AC voltage to the liquid crystal layer is performed by inverting the polarity of the voltage of the pixel electrode of each pixel formation portion with respect to the voltage of the counter electrode, that is, the voltage of the driving video signal written to the pixel electrode. Is called. Therefore, in order to apply an AC voltage to the liquid crystal layer of the liquid crystal display device driven line-sequentially, a driving method (hereinafter referred to as “opposing AC”) in which the voltage of the common electrode and the voltage of the video signal for driving are inverted every horizontal scanning period. And a driving method in which the voltage of the video signal for driving is inverted every horizontal scanning period (hereinafter referred to as “opposite DC driving”).

The liquid crystal display device described in Patent Document 1 includes a gradation palette in which an arbitrary gradation level can be set by programmable intermediate gradation levels displayed by conventional FRC.
JP-A-8-129366

  However, when a vertical gradation is displayed by FRC in a low-temperature environment (for example, −30 ° C.) using a multi-output source driver such as 642 outputs, white is raised every four gradations as shown in FIG. There is a problem that a visible “streaks” (hereinafter referred to as “brightness-reversed streaks”) occurs. FIG. 22 is a graph showing a change in luminance when a vertical gradation is displayed by FRC. As can be seen from FIG. 22, in the vertical gradation display that is changed every L0.25 gradation from the L12 gradation to the L16 gradation by FRC, the luminances of the L13 gradation, the L14 gradation, and the L15 gradation are before and after that. The brightness is higher than expected from the brightness of the intermediate gradation. Such a high-brightness gradation pattern appears as a streak in which the luminance is inverted on the liquid crystal panel 510.

  Further, FIG. 23 is a view when a window pattern is displayed on the liquid crystal panel 510 of the liquid crystal display device described above. As shown in FIG. 23, when a window pattern is displayed in a plurality of areas at the center of the liquid crystal panel 510 with gradations different from the background, the background pattern is displayed in an area outside the window pattern where both ends of the window pattern are displayed. There is a problem that an area having luminance different from the gradation (hereinafter referred to as “block separation”) appears. Such a brightness-reversed streak and block separation are remarkably exhibited when the liquid crystal display device is driven in a low temperature environment.

  The liquid crystal display device described in Patent Document 1 displays the intermediate gradations by using the gradation palette, and thus eliminates the above-described problem, but has a problem that the manufacturing cost is higher than the case of displaying by FRC.

  Therefore, an object of the present invention is to provide a display device that can reduce a difference in luminance of an image that occurs when a display device including a multi-output source driver is AC driven.

The first invention is an active matrix type display device for displaying gradation of an image,
A plurality of scanning signal lines, a plurality of video signal lines intersecting with the plurality of scanning signal lines, and a plurality of scanning signal lines and the intersections of the plurality of video signal lines are arranged in a matrix and correspond to each other. A display portion including a pixel formation portion including a switching element that is turned on or off in accordance with a scanning signal applied to the scanning signal line to be
A scanning signal line driving circuit for selectively activating the plurality of scanning signal lines;
A video signal line driving circuit for applying a video signal representing a video to be displayed to the plurality of video signal lines;
A common electrode driving circuit for driving a common electrode disposed to face the pixel forming portion;
A display control circuit that generates a timing signal necessary to control the scanning signal line drive circuit, the video signal line drive circuit, and the common electrode drive circuit;
The display control circuit includes a timing control circuit that generates a polarity switching control signal that inverts the polarity of the voltage of the video signal and outputs the polarity switching control signal to the video signal line driving circuit in order to drive the display unit with AC.
The timing control circuit turns off the switching element at a timing for inverting the polarity switching control signal in accordance with the appearance frequency of gradation data included in the video signal in at least one horizontal scanning period for each gradation. It adjusts so that it may approximate to the timing to perform.

According to a second invention, in the first invention,
The polarity switching control signal inverts the voltage of the video signal and simultaneously inverts the voltage of the common electrode driving signal for driving the common electrode,
The timing control circuit outputs the polarity switching control signal to the video signal line driving circuit and the common electrode driving circuit.

In a third aspect based on the first aspect, the display control circuit counts the gradation data included in the video signal for each gradation, and sets the counted number of gradation data for each gradation. A counter for outputting to the timing control circuit;
The timing control circuit adjusts the timing at which the polarity switching control signal is inverted to be close to the timing at which the switching element is turned off in accordance with the appearance frequency obtained based on the count number given from the counter. It is characterized by doing.

According to a fourth invention, in the first invention,
The timing control circuit is characterized in that the polarity switching control signal is inverted simultaneously with turning off the switching element.

According to a fifth invention, in the first invention,
The timing control circuit includes a first register that stores an inversion timing of the polarity switching control signal according to the appearance frequency.

According to a sixth invention, in the first invention,
The display control circuit includes:
A memory for storing a video signal of at least one horizontal scanning period;
A polarity switching control circuit to which the video signal stored in the memory is transferred after elapse of the at least one horizontal scanning period;
The polarity switching control circuit obtains the appearance frequency by counting the gradation data included in the video signal transferred from the memory for each gradation, and the maximum appearance frequency of the appearance frequencies is greater than a predetermined value. Is larger, the timing setting signal for outputting the timing for inverting the polarity switching control signal to the timing for turning off the switching element is output to the timing control circuit.

A seventh invention is the sixth invention, wherein
The polarity switching control circuit includes a second register for storing the predetermined value.

In an eighth aspect based on the sixth aspect,
The memory includes two line memories;
When the video signal in which one of the two line memories is stored is transferred to the polarity switching control circuit, the other line memory receives the video signal in the next at least one horizontal scanning period. It is characterized by starting to store.

  According to the first invention, the timing control circuit sets the timing for inverting the polarity switching control signal according to the appearance frequency for each gradation of the gradation data included in the video signal, and the timing for turning the switching element off. Therefore, it is possible to reduce the luminance difference of the video that occurs when AC driving is performed using a multi-output source driver.

  According to the second invention, even in a liquid crystal display device driven by opposed AC driving, it is possible to reduce a luminance difference of an image that occurs when AC driving is performed using a multi-output source driver.

  According to the third invention, the timing control circuit obtains the appearance frequency based on the count number of the gradation data for each gradation counted by the counter, and inverts the polarity switching control signal according to the obtained appearance frequency. The timing is brought close to the timing at which the switching element is turned off. For this reason, it is possible to finely adjust the luminance difference of an image generated when AC driving is performed using a multi-output source driver.

  According to the fourth aspect of the invention, the timing control circuit inverts the polarity switching control signal at the same time as turning off the switching element, so that sufficient time can be secured for bringing the voltage of the video signal close to the target voltage.

  According to the fifth aspect, by providing the first register in the timing control circuit, the timing for inverting the polarity switching control signal corresponding to the appearance frequency can be changed as appropriate.

  According to the sixth invention, the polarity switching control circuit is configured to bring the timing for inverting the polarity switching control signal closer to the timing for turning off the switching element if the appearance frequency of the obtained video signal is greater than a predetermined value. A timing setting signal is output to the timing control circuit. For this reason, it is possible to adjust the timing at which the polarity switching control signal is inverted only when the luminance difference of the video occurs so that the luminance difference does not occur.

  According to the seventh aspect, by providing the second register in the polarity switching control circuit, the timing for inverting the polarity switching control signal is adjusted according to the number of gradation data counts for each gradation included in the video signal can do.

  According to the eighth aspect, the luminance of the video signal can be continuously adjusted by alternately storing the video signal for at least one horizontal scanning period in the two line memories.

<1. Basic study>
In developing the liquid crystal display device according to the embodiment of the present invention, the cause of the occurrence of the brightness-reversed streaks and block separation, which are the conventional problems, was clarified, and a basic study for finding the improvement measures was performed.

<1.1 Overall configuration of liquid crystal display device>
FIG. 1 is a block diagram showing the configuration of the liquid crystal display device 100 used for the basic study. The configuration of the liquid crystal display device 100 will be described with reference to FIG. The liquid crystal display device 100 includes a liquid crystal panel (display unit) 110, six source drivers (video signal line driving circuits) 121 to 126 having 642 outputs, a gate driver (scanning signal line driving circuit) 130, and a display control circuit. 140 and a common electrode driving circuit 150.

  In the liquid crystal panel 110, (642 × 6) source bus lines (video signal lines) S and n (n is an integer of 1 or more) gate bus lines (scanning signal lines) G are arranged in a grid pattern. In addition, a pixel forming unit 111 is provided in the vicinity of the intersection of the source bus line S and the gate bus line G. Each pixel forming unit 111 has a TFT (Thin Film) as a switching element having a gate terminal connected to a gate bus line G passing through a corresponding intersection and a source terminal connected to a source bus line S passing through the intersection. Transistor) 112, a pixel electrode Ep connected to the drain terminal of the TFT 112, and a common electrode Ec provided in common to each pixel formation portion 111, and the pixel capacitance Clc is formed by the pixel electrode Ep and the common electrode Ec. Is formed.

  The display control circuit 140 receives an externally input digital video signal DV, a vertical synchronization signal VSYNC, and a horizontal synchronization signal HSYNC, and receives a digital video signal DA, a source start pulse signal SSP, a source clock signal SCK, and a latch. The strobe signal LS and the polarity switching control signal REV are output to the source drivers 121 to 126. Further, the gate start pulse signal GSP and the gate clock signal GCK are output to the gate driver 130, and the polarity switching control signal REV is output to the common electrode driving circuit 150.

  The six source drivers 121 to 126 respectively drive regions of the liquid crystal panel 110 that are divided into six in the horizontal direction. Each of the source drivers 121 to 126 receives the digital video signal DA, the source start pulse signal SSP, the source clock signal SCK, the latch strobe signal LS, and the polarity switching control signal REV output from the display control circuit 140. The data is sequentially transferred to the source drivers 121 to 126. Each of the source drivers 121 to 126 is converted from a digital video signal DA into a driving video signal AV that is an analog signal by a built-in driving video signal generation circuit to be described later. 1 to n).

  Based on the gate start pulse signal GSP and the gate clock signal GCK output from the display control circuit 140, the gate driver 130 selects an active scanning signal for sequentially selecting each gate bus line Gi by one horizontal scanning period. The data is sequentially output to the gate bus line Gi.

  The common electrode driving circuit 150 receives the polarity switching control signal REV from the display control circuit 140 and applies a voltage having the same polarity as the voltage of the driving video signal AV to the common electrode Ec.

<1.2 Driving Method of Liquid Crystal Display Device>
FIG. 2 is a timing chart when the liquid crystal display device 100 is line-sequentially driven by facing AC driving. With reference to FIG. 2, a method of line-sequentially driving the liquid crystal display device 100 by opposing AC driving will be described.

  The polarity of the voltage of the driving video signal AV and the polarity of the voltage Vcom of the common electrode Ec are simultaneously reversed in the same direction by the polarity switching control signal REV. In the following description, when the polarity switching control signal REV is inverted from the low level to the high level, the voltage of the common electrode Ec becomes higher than the voltage of the driving video signal AV, and the polarity switching control signal REV is changed from the high level to the low level. It is assumed that the voltage of the common electrode Ec becomes lower than the voltage of the driving video signal AV when inverted.

  Further, since the voltage of the driving video signal AV is written to the pixel electrode Ep when the TFT 112 is turned on, the difference voltage between the voltage Vcom of the common electrode Ec and the voltage of the driving video signal AV is the pixel capacitance Clc. To be applied. Therefore, the polarity of the voltage applied to the pixel capacitor Clc when the polarity switching control signal REV is inverted from the low level to the high level, and the pixel capacitance Clc when the polarity switching control signal REV is inverted from the high level to the low level. The pixel forming portion 111 is AC driven in reverse to the polarity of the voltage applied to.

  In the first frame period T1, since the polarity of the polarity switching control signal REV is alternately inverted for each gate bus line Gi, the polarity of the voltage Vcom of the common electrode Ec and the voltage of the driving video signal AV is also different for each gate bus. Inverted alternately for each line Gi. For this reason, the polarity of the voltage applied to the pixel capacitor Clc is reversed for each gate bus line Gi.

  In the second frame period T2, since the polarity inversion of the polarity switching control signal REV for each gate bus line Gi is opposite to that in the first frame period T1, the pixel capacitance Clc for each gate bus line Gi. The polarity of the voltage applied to is also opposite to that of the first frame period T1.

  Hereinafter, in the odd-numbered frame period, the polarity of the voltage applied to the pixel capacitor Clc is reversed in the even-numbered frame period, as in the second frame period T2, as in the first frame period T1. For this reason, when paying attention to the pixel capacitance Clc connected to the same gate bus line Gi, the polarity of the applied voltage is reversed every frame period, and the pixel formation unit 111 is AC driven.

<1.3 Driving video signal generation circuit>
FIG. 3 is a circuit diagram of the driving video signal generation circuit 120 included in each of the source drivers 121 to 126 for generating the 64-gradation driving video signal AV. This driving video signal generation circuit 120 generates a driving video signal AV based on the gradation reference voltage of 64 gradations, and outputs it to 642 source bus lines S1 to S642. In the driving video signal generation circuit 120, the polarity of the gradation reference voltage is inverted every horizontal scanning period by the polarity switching control signal REV, so that the polarity of the driving video signal AV is also inverted every horizontal scanning period.

  As shown in FIG. 3, the driving video signal generation circuit 120 includes two ladder resistors R1 and R2 for driving the pixel forming unit 111 with alternating current, 64 gradation voltage lines L0 to L63, and 642 pieces. Switches SW1 to SW642 and 642 operational amplifiers OP1 to OP642.

  A voltage of 5.3 V is applied to one end of the ladder resistors R1 and R2, and the other end is grounded. Analog switches ASW1 to ASW4 are provided at both ends of the ladder resistors R1 and R2, respectively. The polarity switch control signal REV is applied to the analog switches ASW1 and ASW2, and the inverted signal / REV signal ("/" indicates the inverted signal) of the polarity switch control signal REV is applied to the analog switches ASW3 and ASW4. The analog switches ASW1 to ASW4 are turned on when the polarity switching control signals REV and / REV are at the high level, and are turned off when the polarity switching control signals REV and / REV are at the low level. Therefore, when the analog switches ASW1 and ASW2 are turned on, the analog switches ASW3 and ASW4 are turned off. Conversely, when the analog switches ASW1 and ASW2 are turned off, the analog switches ASW3 and ASW4 are turned on.

  The ladder resistors R1 and R2 generate 64 reference gradation voltages VH1 to VH64 and VL1 to VL64, respectively, by resistance division. Of the generated gradation reference voltages VH1 to VH64 and VL1 to VL64, the output terminals of the gradation reference voltages VH1 and VL1 are connected to the gradation voltage wiring L1, and the output terminals of the gradation reference voltages VH2 and VL2. Are connected to the gradation voltage wiring L2, and similarly, the output terminals of the gradation reference voltages are connected to the corresponding gradation voltage wirings, and the gradation reference voltages VH64 and VL64 are connected to the gradation voltage wiring L64. It is connected to the. In order not to make the figure difficult to see, FIG. 3 shows only the components necessary for outputting the gradation reference voltages VH23, VH24, VL23, and VL24 of the L23 gradation and the L24 gradation, and other levels. Description of components necessary for outputting the adjustment reference voltage is omitted.

  When the polarity switching control signal REV is at a high level, the gradation reference voltage VH23 for the L23 gradation is output from the ladder resistor R1 to the gradation voltage wiring L23, and the gradation reference voltage VH24 for the L24 gradation is output to the gradation voltage wiring L24. Is output. On the other hand, when the polarity switching control signal REV is at the low level, the polarity switching control signal / REV is at the high level, so that the gradation reference voltage VL23 of the L23 gradation is output from the ladder resistor R2 to the gradation voltage wiring L23, The gradation reference voltage VL24 of the L24 gradation is output to the adjustment voltage wiring L24.

  The switches SW1 to SW642 are switched so that one end thereof is connected to any one of the gradation voltage wirings L1 to L64, and the other ends are respectively connected to the source buses via operational amplifiers OP1 to OP642 functioning as voltage followers. It is connected to lines S1 to S642. When the digital video signal DA is supplied to the switches SW1 to SW642, the switches SW1 to SW642 are switched to the gradation reference voltage corresponding to the gradation data included in the digital video signal DA. As a result, the driving video signal AV having any one of the gray levels L1 to L64 is output to the source bus lines S1 to S642.

  Each of the switches SW1 to SW642 has an on-resistance Ron, and each of the source bus lines S1 to S642 has a parasitic capacitance C between each of the switches SW1 to SW642 and the ground terminal. Therefore, when the polarity of the driving video signal AV output to the source bus lines S1 to S642 is inverted by the polarity switching control signal REV, the waveform is dulled by a time constant determined by the on-resistance Ron and the parasitic capacitance C. In particular, the greater the number of source bus lines that output the driving video signal AV of the same gradation, the greater the number of on-resistances Ron and parasitic capacitances C of the switches connected to the source bus lines. For this reason, since the time constant increases, the waveform becomes dull when the polarity of the drive video signal AV is inverted.

<1.4 Examination of causes of luminance difference>
In the drive video signal generation circuit 120 shown in FIG. 3, the source bus lines S1 to S642 are all connected to the gradation voltage wiring L24 by 642 switches SW1 to SW642. In this case, when the polarity switching control signal REV is inverted from the low level to the high level, the voltage applied to the gradation voltage wiring L24 is the gradation reference obtained by dividing the ladder resistor R1 from the gradation reference voltage VL24 obtained by dividing the ladder resistor R2. The voltage is switched to VH24.

  Specifically, for example, as shown in FIG. 5, the voltage is switched from 2.0V to 3.0V. At this time, since there are 642 on-resistances Ron and parasitic capacitances C when viewed from the gradation voltage wiring L24 side, the waveform of the driving video signal AV output to each source bus line S1 to S642 is shown in FIG. As shown in FIG. For this reason, even if the polarity switching control signal REV is inverted to a high level, it takes time until the polarity switching control signal REV rises to 3 V, which is the target voltage, and the TFT 112 is turned off until then.

  Therefore, since the voltage written in the pixel formation unit 111 is lower than the target voltage, the voltage applied to the pixel capacitor Clc is higher than the gradation reference voltage VH24 required for displaying the original L24 gradation. Become. As a result, when the liquid crystal panel 110 is a normally black type, the luminance of the L24 gradation image displayed on the liquid crystal panel 110 is displayed higher than the original L24 gradation image luminance. Lines and block separation occur.

  FIG. 4 is a circuit diagram in the case where the connections of the switches SW1 to S642 are changed in the driving video signal generation circuit 120 of FIG. In the drive video signal generation circuit 120 shown in FIG. 4, 321 switches SW1 to SW321 out of 642 switches SW1 to SW642 are connected to the gradation voltage wiring L24, and the remaining 321 switches SW322 to SW642 are connected to the gradation voltage. Each is connected to the wiring L23.

  When the polarity switching control signal REV is inverted from the low level to the high level, the voltage applied to the gradation voltage wiring L24 is changed from the gradation reference voltage VL24 obtained by dividing the ladder resistor R2 to the gradation reference voltage VH24 obtained by dividing the ladder resistor R1. Switch. Specifically, for example, the voltage is switched from 2.0 V to 3.0 V as shown in FIG. However, when viewed from the L24 gradation voltage wiring L24 side, there are only 321 ON resistances Ron and parasitic capacitances C, which are half of the case of FIG. Therefore, since the time constant is smaller than in the case of FIG. 3, the waveform of the driving video signal AV output to each source bus line S1 to S321 is steeper than that of FIG. 5, as shown in FIG. Rises to a voltage close to the target voltage of 3V in a short time. For this reason, the voltage of the driving video signal AV written to the pixel electrode Ep is substantially equal to the gradation reference voltage VH24 necessary for displaying the original L24 gradation. As a result, when the liquid crystal panel 110 is of a normally black type, the luminance of the LH24 gradation image displayed on the liquid crystal panel 110 is lower than in the case of FIG.

  FIG. 7 shows the appearance frequency of source bus lines connected to the same gradation voltage wiring among the 642 source bus lines S1 to S642 (the driving video signal AV having the same gradation occupied in the source bus lines S1 to S642). 5 is a diagram showing a waveform of the drive video signal AV until the voltage of the drive video signal AV reaches the target voltage for each source bus line ratio). As shown in FIG. 7, when the polarity switching control signal REV is inverted to a high level, the voltage of the driving video signal AV rises to almost the target voltage if there is sufficient time.

  However, as the frequency of appearance of the same gradation increases as 20%, 50%, and 100%, the time required to increase to the target voltage becomes longer. Therefore, when the TFT 112 is turned off, when the appearance frequency is 20%, the voltage of the drive video signal AV has already increased to the target voltage, whereas the appearance frequency is 50%. In the case of, it is lower than the target voltage, and when the appearance frequency is 100%, it is found to be lower.

  For these reasons, when the number of the on-resistance Ron and the parasitic capacitance C viewed from the gradation voltage wiring side is large, when the pixel forming unit 111 is AC-driven, the waveform when the polarity of the driving video signal AV is inverted is obtained. The rise is dull. Therefore, the TFT 112 is turned off before the voltage of the driving video signal AV rises to the target voltage. Therefore, it was found that the luminance of the image displayed on the liquid crystal panel 110 is higher than the luminance that should be originally displayed.

  The stripes and block separation with the luminance reversed appear remarkably when the liquid crystal display device 100 is operated in a low temperature environment. This is because the resistance value between the source terminal and the drain terminal of the TFT 112 becomes higher with respect to the driving video signal AV having a dull waveform at a low temperature, so that the voltage of the pixel electrode Ep hardly reaches the target voltage. Is considered to be the cause.

<1.5 Improvement method of luminance difference>
Based on the above examination results, a method of improving the brightness-reversed lines and block separation displayed on the liquid crystal panel 110 will be described. FIG. 8 is a signal waveform diagram showing the relationship between the timing of inverting the polarity switching control signal REV in one horizontal scanning period and the scanning signal applied to the gate terminal of the TFT 112, and FIG. 9 shows the polarity switching in one horizontal scanning period. FIG. 10 is a signal waveform diagram showing another relationship between the timing at which the control signal REV is inverted and the scanning signal applied to the gate terminal of the TFT 112.

  As shown in FIG. 8, when the polarity switching control signal REV is inverted from the low level to the high level, the voltage of the driving video signal AV and the polarity of the voltage Vcom of the common electrode Ec are inverted, and the voltage Vcom of the common electrode Ec is inverted. Becomes higher than the voltage of the driving video signal AV. At this time, the voltage Vcom of the common electrode Ec immediately rises. However, if the number of source bus lines to which driving video signals AV of the same gradation are output is large, the time constant determined by the number of on-resistances Ron of the switches and the number of parasitic capacitances C of the source bus lines increases. For this reason, even if the polarity of the drive video signal AV is inverted, the waveform is dull and the rise is delayed, and the time required for the voltage of the drive video signal AV to reach the target voltage is increased.

  On the other hand, the TFT 112 is turned on when the scanning signal applied to the gate bus line Gi becomes active, and turned off when the scanning signal becomes inactive. In FIG. 8, the scanning signal becomes inactive after the polarity switching control signal REV signal is inverted to the high level and before the voltage of the driving video signal AV rises to the target potential. Therefore, the voltage difference between the voltage Vcom of the common electrode Ec and the voltage of the driving video signal AV when the TFT 112 is turned off is larger than the target voltage difference of 1.5 V, for example, 1.7 V. Become. Therefore, the luminance of the video displayed by the driving video signal AV is higher than the original luminance. In this case, the voltage of the driving video signal AV further increases until the polarity switching control signal REV is inverted to the low level even after the scanning signal becomes inactive. However, since the TFT 112 is in an OFF state at this time, the increased voltage during this time cannot be written to the pixel electrode Ep.

  Therefore, as shown in FIG. 9, the polarity switching control signal REV is also switched from the high level to the low level when the scanning signal changes from active to inactive and the TFT 112 changes from the on state to the off state. Adjust the timing of REV. As a result, the time until the TFT 112 changes from the on state to the off state can be delayed as compared with the case of FIG. 8, so that the voltage of the driving video signal AV rises during that time and can approach the target voltage. For this reason, the brightness | luminance difference of the image | video displayed on a screen can be reduced. In this way, unlike the case of FIG. 8, the voltage of the drive video signal AV also increases until the polarity switching control signal REV is inverted to the low level, and therefore the increased voltage of the drive video signal AV during that time is equal to the pixel electrode Ep. Can be written on.

<1.6 Opposing DC drive>
Next, a case where the liquid crystal display device is line-sequentially driven by opposed DC driving will be described. FIG. 10 is a block diagram showing a configuration of a liquid crystal display device 200 that is line-sequentially driven by opposed DC driving. In the liquid crystal display device 200, the source drivers 121 to 126 in FIG. 1 are replaced with source drivers 221 to 226, the display control circuit 140 is replaced with a display control circuit 240, and the common electrode drive circuit 150 is replaced with a common electrode drive circuit 250, respectively. The signal given from the circuit 240 to the common electrode drive circuit 250 has the same configuration as the liquid crystal display device 100 of FIG. 1 except that the polarity switching control signal REV is changed to the common electrode control signal VC. Therefore, the same components as those of the liquid crystal display device 100 are denoted by the same reference numerals, and the description thereof is omitted.

  FIG. 11 is a timing chart showing a method for driving the liquid crystal display device 200. In the timing chart shown in FIG. 11, unlike the timing chart of FIG. 2, the potential Vcom of the common electrode is constant. Therefore, when the polarity switching control signal REV is inverted, only the polarity of the driving video signal AD is inverted.

  FIG. 12 is a circuit diagram of a driving video signal generation circuit 220 included in each of the source drivers 221 to 226 for generating a 64-gradation driving video signal AV. Unlike the driving video signal generation circuit 120, the driving video signal generation circuit 220 includes only one ladder resistor R3, and the voltage of the common electrode Ec among the 64 gray scale reference voltages generated by resistance division. The gradation reference voltages higher than Vcom are VH1 to VH64, respectively, and the gradation reference voltages lower than the voltage Vcom of the common electrode Ec are VL1 to VL64, respectively. Terminals for outputting the respective gradation reference voltages VH1 to VH64 and VL1 to VL64 are connected to one end of the reference voltage changeover switches SWV1 to SWV64, and the other end of the reference voltage changeover switch SWV is connected to each corresponding gradation voltage wiring. Has been. Specifically, one end of the reference voltage changeover switch SWV23 for switching the gradation reference voltages VH23 and VL23 for the L23 gradation is connected to a terminal for outputting the gradation reference voltages VH23 and VL23, and the other end is connected to the gradation voltage wiring. L23 is connected. One end of the reference voltage changeover switch SWV24 for switching the gradation reference voltages VH24 and VL24 for the L24 gradation is connected to a terminal for outputting the gradation reference voltages VH23 and VL23, and the other end is connected to the gradation voltage wiring L24. ing. The reference voltage changeover switches SWV1 to SWV64 are simultaneously switched to the gradation reference voltages VH1 to VH64 or switched to the gradation reference voltages VL1 to VL64 according to the polarity switching control signal provided from the display control circuit 240. Therefore, by inverting the polarity switching control signal REV every horizontal scanning period, the voltage of the driving video signal AV can also be inverted every horizontal scanning period. Note that the switches SW1 to SW642, the operational amplifiers OP1 to OP642, and the parasitic capacitance C are all the same as those of the driving video signal generation circuit 120, and therefore, the same reference numerals are given and description thereof is omitted.

  FIG. 13 is a signal waveform diagram showing the relationship between the timing of inverting the polarity switching control signal REV in one horizontal scanning period and the waveform of the scanning signal applied to the gate terminal of the TFT 112 when line sequential driving is performed by opposed DC driving. FIG. 14 is a signal waveform diagram showing another relationship between the timing of inverting the polarity switching control signal REV in one horizontal scanning period in the case of opposed DC driving and the waveform of the scanning signal applied to the gate terminal of the TFT 112.

  As shown in FIG. 13, when the polarity switching control signal REV is inverted from the low level to the high level, the polarity of the voltage of the driving video signal AV applied to the source bus line is inverted. At this time, if the number of source bus lines to which driving video signals AV of the same gradation are output is large, the time constant becomes large, and the waveform becomes dull as in the case of FIG. Therefore, the TFT 112 is turned off until the voltage of the driving video signal AV reaches the target voltage. In this case, the voltage of the driving video signal AV further decreases until the polarity switching control signal REV is inverted to the low level even after the scanning signal becomes inactive. However, since the TFT 112 is in an OFF state at this time, the voltage drop during this time cannot be written to the pixel electrode Ep. Therefore, the voltage difference between the voltage Vcom of the common electrode Ec and the voltage applied to the pixel capacitor Clc is 1.7 V, which is larger than the target voltage difference of 1.5 V, and the normally black type display panel 110 can be used. For example, an image having a higher luminance than the original luminance is displayed.

  Therefore, as shown in FIG. 14, when the scanning signal changes from active to inactive and the TFT 112 changes from the on state to the off state, the polarity switching control signal REV is also inverted from the high level to the low level. In this case, since the timing at which the TFT 112 is turned from the on state to the off state can be delayed as compared with the case of FIG. 13, the voltage of the driving video signal AV drops during that time, and the voltage Vcom of the common electrode Ec It can be closer to the target voltage difference of 1.5V. For this reason, the brightness | luminance difference of the image | video displayed on a screen can be reduced. Thus, unlike the case of FIG. 13, the voltage of the driving video signal AV drops until the polarity switching control signal REV is inverted to a low level, and therefore the voltage drop of the driving video signal AV during that period is equal to the pixel electrode. Ep can be written.

  Even in the same line sequential drive, the opposed DC drive has a larger difference from the target voltage when the voltage of the driving video signal AV is inverted than the opposed AC drive. For this reason, the opposed DC drive is more susceptible to the time constant due to the on-resistance Ron and the parasitic capacitance C than the opposed AC drive, and the luminance difference of the image is likely to occur.

  If line-sequential driving by counter AC driving or counter DC driving is performed according to the above basic study, in either case, the polarity of the polarity switching control signal REV is reversed when the TFT 112 is turned off. It was found that the brightness difference between the images displayed on the screen can be reduced.

  Note that the polarity of the polarity switching control signal REV may be reversed at the same time as when the TFT is turned off or may be slightly delayed. In this case, the luminance difference of the image can be most reduced when the polarity of the polarity switching control signal REV is reversed at the same time when the TFT is turned off, and the polarity of the polarity switching control signal REV is reversed more than that. The later the timing is, the less the luminance difference of the video is reduced.

<2. First Embodiment>
<2.1 Overall configuration>
FIG. 15 is a block diagram showing a configuration of the liquid crystal display device 300 according to the first embodiment of the present invention. The liquid crystal display device 300 has the same configuration as the liquid crystal display device 100 except that the display control circuit 140 of the liquid crystal display device 100 is replaced with a display control circuit 340. For this reason, the same components as those of the liquid crystal display device 100 are denoted by the same reference numerals, and the description thereof is omitted. Further, since the liquid crystal display device 300 is also line-sequentially driven by facing AC driving, the driving method is the same as the driving method of the liquid crystal display device 100. For this reason, a timing chart is also omitted.

<2.2 Display control circuit>
FIG. 16 is a block diagram illustrating a configuration of the display control circuit 340 according to the first embodiment. As shown in FIG. 16, the display control circuit 340 includes a timing signal generation circuit 341, a data processing circuit 342, a line memory 343, a polarity switching control circuit 344, and a timing control circuit 345.

  When the vertical synchronization signal VSYNC and the horizontal synchronization signal HSYNC are supplied to the timing signal generation circuit 341 from the outside, the timing signal generation circuit 341 generates a gate start pulse signal SSP, a gate clock signal GCK, and a source start pulse signal based on these signals. SSP, source clock signal SCK, and latch strobe signal LS are generated, gate start pulse signal SSP and gate clock signal GCK are supplied to gate driver 130, source start pulse signal SSP, source clock signal SCK, and latch strobe signal LS The polarity switching control signal REV is output to the source drivers 121 to 126, and the polarity switching control signal REV is output to the common electrode driving circuit 150, respectively. In addition, a control signal CT for controlling the operation of the data processing circuit 342 is output to the data processing circuit 342, and a source start pulse signal SSP and a source clock signal SCK are output to a timing control circuit 345 described later.

  The data processing circuit 342 converts the digital video signal DV into a digital video signal DA including gradation data, and outputs it to the source drivers 121 to 126 and the line memory 343. The line memory 343 includes two line memories 343a and 343b, and each of the line memories 343a and 343b can store a digital video signal DA for one horizontal scanning period. One of the two line memories 343a and 343b sequentially stores the digital video signal DA for one horizontal scanning period, and when the digital video signal DA for one horizontal scanning period is stored, the stored digital The video signal DA is transferred to the polarity switching control circuit 344. At the same time, the other line memory starts storing the digital video signal DA in the next one horizontal scanning period. As described above, by alternately storing the digital video signal DA in the two line memories 343a and 343b, the appearance frequency of the gradation data included in the digital video signal DA can be obtained for each horizontal scanning line period.

  The polarity switching control circuit 344 generates gradation data for each gradation of 64 gradations for each of the source drivers 121 to 126 for the digital video signal of one horizontal scanning period output to each of the source drivers 121 to 126, respectively. Find the frequency. As a result, when there is gradation data having an appearance frequency of 50% or more, the polarity switching control circuit 344 outputs a high-level timing setting signal SET to the timing control circuit 345, and the appearance frequency of all gradation data is 50. If it is less than%, a low level timing setting signal SET is output. Note that 50% of the appearance frequency is an example, and a reference appearance frequency is stored in advance in the register 344a built in the polarity switching control circuit 344, and the timing setting signal SET is switched based on the appearance frequency. Good.

  When the given timing setting signal SET is at a high level, the timing control circuit 345 generates a polarity switching control signal REV whose output is inverted to a low level when the TFT 112 is turned off. 126 and the common electrode drive circuit 150. On the other hand, when the timing setting signal SET is at the low level, the polarity switching control signal REV is generated without changing the timing of inversion to the low level, and is output to the source drivers 121 to 126 and the common electrode driving circuit 150. Note that, when a predetermined time has elapsed after the TFT 112 is turned off, a polarity switching control signal REV that is inverted to a low level may be generated and output to the source drivers 121 to 126 and the common electrode driving circuit 150. . Since the timing control circuit 345 includes the register 345a, the predetermined time may be stored in the register 345a in advance, and the stored time may be changed as appropriate.

<2.3 Effects>
FIG. 17 is a graph showing a change in luminance of the drive video signal AV when the timing at which the polarity switching control signal REV is inverted to a low level is changed. As shown in FIG. 17, in a low temperature environment such as −30 ° C., the timing when the polarity switching control signal REV is output by 1.66 μs is earlier than the case where it is advanced by 0.5 μs. , L13 gradation, L14 gradation, and L15 gradation, it can be seen that the occurrence of stripes with inverted luminance is suppressed.

  As described above, when grayscale data having an appearance frequency of 50% or more is included in the grayscale data in one horizontal scanning period, stripes and blocks separated by luminance inversion occur. However, by outputting the polarity switching control signal REV by a predetermined time earlier than the normal timing, it is possible to suppress the occurrence of stripes with inverted luminance and block separation that occur when AC driving is performed with a multi-output source driver. .

<2.4 Modification>
In this embodiment, the polarity of the driving video signal AV is inverted for each gate bus line by the polarity switching control signal REV. However, the polarity of the driving video signal AV is set for every plurality of rows such as every two rows and every three rows. It may be reversed. In this case, the line memories 343a and 343b need to have a large memory capacity so that the digital video signals DA for a plurality of horizontal periods can be stored. Also, the polarity switching control circuit 344 determines whether or not there is gradation data having an appearance frequency of 50% or more for the digital video signal DA for each of the plurality of rows given from the line memories 343a and 343b, and according to the result. As in the case of the present embodiment, the timing setting signal SET is output to the timing control circuit 345. The effect of this modification is the same as the effect of this embodiment.

  Further, in the present embodiment, the case of line-sequential driving by counter AC driving has been described. However, the same effect as that of the present embodiment can be obtained by using the display control circuit 340 even when line sequential driving is performed by counter-DC driving. An effect can be produced.

<3. Second Embodiment>
<3.1 Overall configuration>
FIG. 18 is a block diagram showing a configuration of a liquid crystal display device 400 according to the second embodiment of the present invention. The liquid crystal display device 400 has the same configuration as the liquid crystal display device 100 except that the display control circuit 140 of the liquid crystal display device 100 is replaced with a display control circuit 440. For this reason, the same components as those of the liquid crystal display device 100 are denoted by the same reference numerals, and the description thereof is omitted. Further, since the liquid crystal display device 400 is also line-sequentially driven by facing AC driving, the driving method is the same as the driving method of the liquid crystal display device 100. For this reason, a timing chart is also omitted.

<3.2 Display control circuit>
FIG. 19 is a block diagram showing a configuration of the display control circuit 440 according to the present embodiment. In the display control circuit 440, the same components as those of the display control circuit 340 according to the first embodiment are denoted by the same reference numerals, and the description thereof is omitted. As shown in FIG. 19, in the display control circuit 440, the line memories 343a and 343b and the polarity switching control circuit 344 of the display control circuit 340 are replaced with a counter 443, and the timing control circuit 345 is replaced with a timing control circuit 445. ing.

  The digital video signal DA converted by the data processing circuit 342 is output to the source drivers 121 to 126 and the counter 443. The counter 443 sequentially takes in the digital video signal DA of one horizontal scanning period output from the data processing circuit 242 and counts the gray scale data included in the taken digital video signal DA for each gray scale. Then, the count number of gradation data for each gradation is output to the timing control circuit 445.

  The timing control circuit 445 obtains the appearance frequency of the gradation data for each gradation, and selects the time corresponding to the maximum appearance frequency among the obtained appearance frequencies from the plurality of times stored in the register 445a in advance. select. Then, the polarity switching control signal REV that is inverted to the low level earlier than the normal timing by the selected time is generated and output to the source drivers 121 to 126 and the common electrode driving circuit 150. Since the timing control circuit 445 includes the register 445a, a plurality of times corresponding to the maximum appearance frequency may be stored in the register 445a in advance, and may be changed as appropriate to the stored time.

<3.3 Effects>
As in the first embodiment, the polarity switching control signal REV is inverted earlier than the normal timing by a time selected according to the maximum output frequency, and thus occurs when AC driving is performed with a multi-output source driver. It is possible to suppress the occurrence of streaks with inverted luminance and block separation. Further, since the timing at which the polarity switching control signal REV is inverted to the low level can be adjusted according to the appearance frequency, the luminance difference can be adjusted according to the count number of gradation data of the same gradation.

<3.4 Modification>
In the present embodiment, the polarity of the driving video signal AV is inverted for each gate bus line by the polarity switching control signal REV. However, as in the case of the modification of the first embodiment, the polarity of the driving video signal AV may be inverted every plural rows such as every two rows or every three rows. In this case, the counter 443 needs to have a large memory capacity so that it can store digital video signals DA for a plurality of horizontal periods. The effect of this modification is the same as the effect of this embodiment.

  Further, in the present embodiment, the case of line-sequential driving by counter AC driving has been described. However, the same effect as that of the present embodiment can be obtained by using the display control circuit 440 even when line sequential driving is performed by counter-DC driving. An effect can be produced.

It is a block diagram which shows the structure of the liquid crystal display device of a counter AC drive used for the fundamental examination. 3 is a timing chart when the liquid crystal display device shown in FIG. 1 is line-sequentially driven by opposing AC driving. FIG. 2 is a circuit diagram of a driving video signal generation circuit included in a source driver of the liquid crystal display device of FIG. 1. FIG. 4 is a circuit diagram when the connection of switches is changed in the drive video signal generation circuit of FIG. 3. FIG. 4 is a diagram illustrating an increase in voltage of a driving video signal when a polarity switching control signal is inverted in the driving video signal generation circuit of FIG. 3. FIG. 5 is a diagram showing an increase in voltage of a driving video signal when a polarity switching control signal is inverted in the driving video signal generation circuit shown in FIG. 4. It is a figure which shows the waveform of the drive video signal AV until the voltage of the drive video signal becomes a target voltage for every appearance frequency of the source bus line connected to the same gradation voltage wiring. FIG. 4 is a signal waveform diagram showing the relationship between the timing of inverting the polarity switching control signal in one horizontal scanning period of the driving video signal generation circuit of FIG. 3 and the scanning signal applied to the gate terminal of the TFT. FIG. 4 is a signal waveform diagram showing another relationship between the timing of inverting the polarity switching control signal in one horizontal scanning period of the driving video signal generation circuit of FIG. 3 and the waveform of the scanning signal applied to the gate terminal of the TFT. It is a block diagram which shows the structure of the liquid crystal display device of opposing DC drive used for the fundamental examination. 11 is a timing chart when the liquid crystal display device of FIG. 10 is line-sequentially driven by counter DC driving. FIG. 11 is a circuit diagram of a driving video signal generation circuit included in a source driver of the liquid crystal display device of FIG. 10. FIG. 13 is a signal waveform diagram showing the relationship between the timing for inverting the polarity switching control signal in one horizontal scanning period and the scanning signal applied to the gate terminal of the TFT in the driving video signal generation circuit of FIG. 12. FIG. 13 is a signal waveform diagram illustrating another relationship between the timing of inverting the polarity switching control signal in one horizontal scanning period and the scanning signal applied to the gate terminal of the TFT in the driving video signal generation circuit of FIG. 12. 1 is a block diagram illustrating a configuration of a liquid crystal display device according to a first embodiment of the present invention. FIG. 16 is a block diagram illustrating a configuration of a display control circuit according to the present embodiment included in the liquid crystal display device of FIG. 15. It is a graph which shows the change of the brightness | luminance of the video signal for a drive at the time of changing the timing which a polarity switching control signal inverts to a low level. It is a block diagram which shows the structure of the liquid crystal display device which concerns on the 2nd Embodiment of this invention. It is a block diagram which shows the structure of the display control circuit which concerns on this embodiment contained in the liquid crystal display device of FIG. It is a figure which shows the method of producing an intermediate | middle gradation by FRC and displaying a vertical gradation on a liquid crystal panel. It is the figure which displayed the vertical gradation on the liquid crystal panel. It is a graph showing the change of the brightness | luminance of an image | video when carrying out the vertical gradation display by FRC. It is the figure which displayed the window pattern on the liquid crystal panel.

Explanation of symbols

DESCRIPTION OF SYMBOLS 100, 200, 300, 400 ... Liquid crystal display device 110 ... Liquid crystal panel 111 ... Pixel formation part 112 ... TFT
120, 220: Driving video signal generation circuit 121-126, 221-226 ... Source driver 130 ... Gate driver 140, 240, 340, 440 ... Display control circuit 150, 250 ... Common electrode driving circuit 243 ... Line memory 344 ... Polarity Switching control circuit 344a, 345a, 345a ... Register 345, 445 ... Timing control circuit 443 ... Counter

Claims (8)

An active matrix type display device for gradation display of an image,
A plurality of scanning signal lines, a plurality of video signal lines intersecting with the plurality of scanning signal lines, and a plurality of scanning signal lines and the intersections of the plurality of video signal lines are arranged in a matrix and correspond to each other. A display portion including a pixel formation portion including a switching element that is turned on or off in accordance with a scanning signal applied to the scanning signal line to be
A scanning signal line driving circuit for selectively activating the plurality of scanning signal lines;
A video signal line driving circuit for applying a video signal representing a video to be displayed to the plurality of video signal lines;
A common electrode driving circuit for driving a common electrode disposed to face the pixel forming portion;
A display control circuit that generates a timing signal necessary to control the scanning signal line drive circuit, the video signal line drive circuit, and the common electrode drive circuit;
The display control circuit includes a timing control circuit that generates a polarity switching control signal that inverts the polarity of the voltage of the video signal and outputs the polarity switching control signal to the video signal line driving circuit in order to drive the display unit with AC.
The timing control circuit turns off the switching element at a timing to invert the polarity switching control signal in accordance with the appearance frequency of gradation data included in the video signal in at least one horizontal scanning period for each gradation. A display device that is adjusted to approach timing. The polarity switching control signal inverts the voltage of the video signal and simultaneously inverts the voltage of the common electrode driving signal for driving the common electrode,
The display device according to claim 1, wherein the timing control circuit outputs the polarity switching control signal to the video signal line driving circuit and the common electrode driving circuit. The display control circuit further includes a counter that counts the gradation data included in the video signal for each gradation, and outputs a count number of gradation data for each counted gradation to the timing control circuit,
The timing control circuit adjusts the timing at which the polarity switching control signal is inverted to be close to the timing at which the switching element is turned off in accordance with the appearance frequency obtained based on the count number given from the counter. The display device according to claim 1, wherein:   The display device according to claim 1, wherein the timing control circuit inverts the polarity switching control signal simultaneously with turning off the switching element.   The display device according to claim 1, wherein the timing control circuit includes a first register that stores an inversion timing of the polarity switching control signal according to the appearance frequency. The display control circuit includes:
A memory for storing a video signal of at least one horizontal scanning period;
A polarity switching control circuit to which the video signal stored in the memory is transferred after elapse of the at least one horizontal scanning period;
The polarity switching control circuit obtains the appearance frequency by counting the gradation data included in the video signal transferred from the memory for each gradation, and the maximum appearance frequency of the appearance frequencies is greater than a predetermined value. The timing setting signal for making the timing for inverting the polarity switching control signal close to the timing for turning off the switching element is output to the timing control circuit. Display device.   The display device according to claim 6, wherein the polarity switching control circuit includes a second register that stores the predetermined value. The memory includes two line memories;
When the video signal in which one of the two line memories is stored is transferred to the polarity switching control circuit, the other line memory stores the video of at least the next one horizontal scanning period. 7. A display device according to claim 6, characterized in that it begins to store signals.

Images