JP2621161B2 - LCD drive system - Google Patents

Description

Description: TECHNICAL FIELD [0001] The present invention relates to a liquid crystal driving system that performs grayscale display on a liquid crystal display panel by a multiplex system.

[Prior Art and its Problems] Conventionally, a liquid crystal drive circuit for driving a liquid crystal display panel in, for example, a liquid crystal television or the like is generally configured as shown in FIG. 8 or FIG. FIG. 8 shows a circuit configuration example when the common signal and the segment signal are quaternary, and FIG. 9 shows a circuit configuration example when the common signal is ternary and the segment signal is binary.

In FIG. 8, reference numeral 1 denotes a display control circuit, which is a segment-side drive circuit 2, a segment-side analog multiplexer 3, a common-side drive circuit 4, and a common-side analog multiplexer 5.
Is controlled. 6 is an LCD drive voltage generation circuit,
Generates LCD drive voltages V0, V1, V2, V3, V4, V5 from a predetermined power supply voltage, and shares the voltage segment side analog multiplexer 3, V0, V1, V4, V5 of V0, V2, V3, V5. To the side analog multiplexer 5. The segment side drive circuit 2 sequentially reads a plurality of bits, for example, 3 bits of digital display data sent from the display control circuit 1, reads one line of data, and then executes a gradation signal corresponding to the data. And create an analog multiplexer 3
Output to The analog multiplexer 3 selects the voltage V0, V2 or V3, V5 in accordance with the gradation signal from the segment side drive circuit 2 and drives the segment electrodes of the LCD panel (liquid crystal display panel) 7 for display. On the other hand, the common-side drive circuit 4 reads a common signal supplied from the display control circuit 1 for example every one field cycle, sequentially shifts the signal, generates a common drive timing signal, and outputs it to the common-side analog multiplexer 5. The analog multiplexer 5 selects the voltages V0, V1, V4, and V5 according to a common drive timing signal from the common side drive circuit 4, and sequentially drives the common electrodes of the LCD panel 7.

FIG. 10 (A) shows a segment signal waveform and a common signal waveform when the field inversion method of inverting the drive signal for each field is used in the above configuration.
FIG. 10B shows a segment signal and a common signal in the case of using a one-common inversion method in which a drive signal is inverted for each common.

On the other hand, the liquid crystal driver circuit shown in FIG. 9 is, V + by LCD drive voltage generator circuit 6, V-, and generates a driving voltage of _{V H, V M, V L} , V +, V- voltage segment side analog of The voltage of V _H , V _M , and V _L is supplied to the multiplexer 3 and to the common-side analog multiplexer 5, and the other configuration is the same as that of the circuit of FIG. FIG. 10 (C) shows a segment signal waveform and a common signal waveform in the case of using a field inversion method in which a drive signal is inverted every field, and FIG. 10 (D) shows an inversion control of the drive signal every one common. 5 shows a segment signal and a common signal waveform when a 1-common inversion method is used.

If the LDC panel 7 is driven with ideal signal waveforms as shown in FIGS. 10 (A) to 10 (D), a good display image can be obtained. However, in the LCD panel 7, as shown in an equivalent circuit in FIG. 11, input resistances RC and RS are formed on the common side and the segment side, respectively, and a capacitor C is formed between each common electrode and the segment electrode. You. In particular, due to the common-side input resistance RC and the capacitor C between the electrodes, the signal waveform at the time of non-selection of the common electrode is related to the gradation data at the time of gradation switching of the segment-side drive circuit. (A) to (D). FIGS. 12 (A) to 12 (D) correspond to FIGS.
Only the non-selection voltage is shown in FIGS. That is, the segment signal is “V5 → V3” or “V0 → V” in the case of (A) or (B) when switching the gradation.
2 ", and in the case of (C) and (D)," V + → V- "or" V- → V + ", and the potential is constantly changing.
For this reason, the high frequency component is output as a spike to the common electrode side when not selected via the capacitor C formed between the electrodes. FIG. 12A shows a common signal waveform at the time of one field inversion, in which the selection voltage is omitted. FIG. 3B shows an example of a common signal waveform at the time of one common inversion, which is an example of 7 gradations (3 bits per pixel of display data).
Has been split. As shown in FIG. 13, the signal waveforms of the seven gradations have different time widths from "001" to "111". Therefore, there is a possibility that six edges occur in one common period as shown in (1) of FIG. 13, which corresponds to the spike (1) in FIG.
In one common period, each segment electrode is
, And the magnitude of the spike is determined depending on which gray level is larger. In the example of FIG. 12 (B), it can be seen that the spike at the position is large, and the number of segment electrodes driven at the gray scale (010) is the largest.

For the above-mentioned reason, a spike occurs in the common electrode at the time of non-selection, so that the effective value actually applied to the liquid crystal is different from the accurate effective value of the non-selection voltage, and a tailing phenomenon occurs.

[Object of the Invention] The present invention has been made in view of the above circumstances, and can eliminate the effect of spikes generated on a common electrode, prevent the occurrence of a tailing phenomenon, and display a good image on a liquid crystal display panel. It is an object to provide a liquid crystal driving method.

SUMMARY OF THE INVENTION According to the present invention, display data is classified into a plurality of levels for each common electrode scanning period, counted for each classification, and a pull selection voltage value supplied to the common electrode is corrected according to a count value for each classification. By doing so, the effect of spikes is eliminated.

Hereinafter, an embodiment of the present invention will be described with reference to the drawings.
FIG. 1 is an example of a liquid crystal drive circuit in which both the common signal and the segment signal are quaternary, and corresponds to the conventional circuit shown in FIG. The embodiment shown in FIG. 1 includes an LCD drive voltage generating circuit 6 and a common side analog multiplexer 5.
And a common-side non-selection voltage control circuit 11 is provided between them, and the other configuration is the same as that of the circuit shown in FIG. The LCD drive voltage generation circuit 6 supplies the voltages V0 to V5 to the non-selection voltage control circuit 11, and supplies the selection voltages V0 and V5 directly to the common side analog multiplexer 5. The non-selection voltage control circuit 11 is supplied with display data and a control signal from the display control circuit 1. The non-selection voltage control circuit 11 corrects the LCD drive voltages V1 and V4 according to the display data and the control signal from the display control circuit 1.
The signals are converted into V1 'and V4' and supplied to the analog multiplexer 5.

FIG. 2 shows an example of a liquid crystal drive circuit when the common signal is ternary and the segment signal is binary, and corresponds to the conventional circuit shown in FIG. The embodiment shown in FIG.
A common-side non-selection voltage control circuit 11A is provided between the LCD drive voltage generation circuit 6A and the common-side analog multiplexer 5, and the other configuration is the same as that of the circuit shown in FIG. The LCD drive voltage generation circuit 6A includes V _M , V +,
While supplying the voltage of V− to the non-selection voltage control circuit 11A,
The voltages V _H and V _L are supplied directly to the common side analog multiplexer 5. Further, display data and a control signal are given from the display control circuit 1 to the non-selection voltage control circuit 11A. The non-selection voltage control circuit 11A controls the LCD drive voltage V in accordance with the display data and the control signal from the display control circuit 1.
_M is corrected and converted into V _M ′ and supplied to the analog multiplexer 5.

The non-selection voltage control circuit 11 corrects the common-side non-selection voltages V1 and V4 to V1 'and V4' in accordance with the segment data as shown in FIGS. 3A and 3B. The non-selection voltage control circuit 11A is shown in FIG.
Correcting the voltage V _M 'together common side non-selection voltage V _M as shown in (D) in the segment data. Common non-selective voltage is varied in accordance with the segment data as described above V1 ', V4', by using the V _M ', the OFF signal of the common side shown in FIG. 4 (A) ~ (D) As a result, the influence of the spike is eliminated. In this case, instead of canceling the spike, the voltage level is increased by that amount and the spike is corrected effectively.

Next, details of the non-selection voltage control circuits 11 and 11A will be described with reference to FIG. In the figure, reference numeral 21 denotes a decoder, which is n-bit display data D1 sent from the display control circuit 1.
To Dn and the chip enable CE are input. The decoder 21 classifies the data sent from the display control circuit 1 and, for example, “001” in the case of 3-bit data D1 to D3
The data is classified into six types of data of ~ 110 and the counters 22a to 22f provided for each data are counted up. And
The count outputs of the counters 22a to 22f are
a to 23f. The latch circuits 23a to 23f respectively latch the count outputs of the counters 22a to 22f in synchronization with a timing signal _N supplied from the display control circuit 1 every 1H (H is a horizontal cycle) and output the latched count outputs to the data selector 24. . Counter 22 by this time the timing signal _N
a to 22f are reset. The data selector 24
Is supplied with a pulse _C for generating a gradation signal and a timing signal _N from the display control circuit 1. The data selector 24 sequentially reads out the data latched by the latch circuits 23a to 23f in synchronization with the gradation signal generating pulse _C, and outputs the data to the analog multiplexer 25.
The analog multiplexer 25 is supplied with various voltages obtained by dividing the voltages from the LCD drive voltage generation circuits 6 and 6A by the resistance division circuit 26. The analog multiplexer 25 selects various voltages divided by the resistance dividing circuit 26 according to the voltage supplied from the data selector 24, and outputs the selected voltages as V1 'and V4' via a buffer circuit 27.

The analog multiplexer 25, the resistance division circuit 26,
The portion of the buffer circuit 27 will be described in further detail with reference to FIGS. FIG. 6 shows a circuit configuration when used for the non-selection voltage control circuit 11 in FIG. 1, and FIG. 7 shows a circuit configuration when used for the non-selection voltage control circuit 11A in FIG. Things.

First, a circuit configuration when used in the non-selection voltage control circuit 11 will be described with reference to FIG. Resistance divider circuit 26
Comprises first and second division circuits 26a and 26b. First
In the dividing circuit 26a, 2n resistors r are connected in series, the voltages V5 and V3 from the LCD drive voltage generating circuit 6 are supplied to both ends thereof via the resistors R, and the voltage V4 is supplied to the middle point. You. In this case, the resistance R is set to a larger value than the resistance r, and a voltage “V4 ± nΔV” that slightly changes around the voltage V4 from the division point of each resistance r is obtained. The second division circuit 26b has 2n resistors r connected in series, both ends of which are supplied with the voltages V0 and V2 from the LCD drive voltage generation circuit 6 via the resistor R, and the middle point of the voltage V1
Is supplied. From the second dividing circuit 26b, a voltage "V1 ± n.DELTA.V" that slightly changes around the voltage of V1 from the dividing point of each resistor r is obtained. And
The voltage divided by the resistance dividing circuit 26 is sent to the analog multiplexer 25. The analog multiplexer 25 includes first and second multiplexers 25a and 25b.
The first multiplexer 25a is supplied with the voltage “V4 ± nΔV” divided by the first division circuit 26a, and the second multiplexer 25b is supplied with the voltage divided by the second division circuit 26b. “V1 ± nΔV” is given. The first multiplexer 25a is connected to the data selector 2
The divided voltage of the first divided circuit 26a is selected according to the data given from 4, and is output as the voltage V4 'via the buffer circuit 27a. Further, the second multiplexer 25b
Selects the divided voltage of the second divided circuit 26b according to the data supplied from the data selector 24, and
As a voltage V1 '.

Next, referring to FIG. 7, the analog multiplexer 25 and the resistance dividing circuit 2 when used in the non-selection voltage control circuit 11A
6, The circuit configuration of the buffer circuit 27 will be described. The resistor dividing circuit 26 includes n resistors r connected in series, and has a LCD driving voltage V−, V−V from the LCD driving voltage generating circuit 6A at both ends.
+ Is is supplied through the resistors R, the voltage V _M applied to its midpoint. The resistance division circuit 26, a voltage that changes slightly "V _M ± EnuderutaV" is taken around the V _M voltage from the dividing point of the resistors r, analog multiplexer
Sent to 25. The analog multiplexer 25, a voltage divided by the resistance division circuit 26 "V _M ± nΔV" selected according to the data from the data selector 24, and outputs it as V _M 'via a buffer circuit 27.

Next, the non-selection voltage control circuit 11, 1 configured as described above
The operation of 1A will be described. In FIG.
The display control circuit 1 supplies the display control circuit 21 with, for example, 3-bit digital display data D1 to D3. The decoder 21 operates according to a chip enable signal CE provided from the display control circuit 1, classifies the display data D1 to D3 into data 1 to data 6, and counts up counters 22a to 22f.
That is, for example, if the display data D1 to D3 are data 1 (001), the decoder 21 sets the content of the counter 22a to “+1”.
If it is data 2 (002), the content of the counter 22b is changed to “+
1 ". As described above, during 1H, the display data D1 to D3 sent from the display control circuit 1 are classified, and the number is counted by the counters 22a to 22f. Then, when the classification and counting operation is completed for the 1H data,
A timing signal _N is provided from the display control circuit 1, and the count values of the counters 22a to 22f are
Latched at 3f, then reset. The data latched by the latch circuits 23a to 23f is a data selector.
The data is sequentially read out by the synchronizing with the gradation signal generating pulse _C by the reference numeral 24, and is sent to the analog multiplexer 25 shown in detail in FIGS.

In the circuit shown in FIG. 6, multiplexers 25a and 25b operate based on data from data selector 24,
The voltage “V4 ± nΔ” divided by the first division circuit 26a
V ", the voltage" V1 ±
nΔV ”, and V4 ′,
Output as V1 '. In this case, the count values of the counters 22a to 22f in FIG. 5 may be counted up to 160 if the LCD panel 7 has, for example, 160 segment electrodes. Therefore, the resistor divider circuit
26, a first divided circuit 26a and a second divided circuit 26b
In this case, it is ideal to prepare 160 kinds of voltages, but the circuit configuration becomes very complicated and the voltage value which is hardly used becomes very large. Therefore, the first divided circuit
In the case where the counters 22a to 22f each have an 8-bit configuration, the counters 26a and 26b divide the data into five types of "000" to "100" by looking at the three bits. That is, in the first division circuit 26a in FIG. 6, “V4 ± Δ
V ”,“ V4 ± 2ΔV ”,“ V4 ± 3ΔV ”,“ V4 ± 4Δ ”
V ”and“ V4 ± 5ΔV ”. Also,
Similarly, in the second division circuit 26b, “V1 ± ΔV” and “V1 ±
2ΔV ”,“ V1 ± 3ΔV ”,“ V1 ± 4ΔV ”,“ V1 ± 5 ”
ΔV ”are generated. The multiplexers 25a and 25b select the five types of voltages generated by the first and second divisional circuits 26a and 26b, respectively, according to the data from the data selector 24.
Output as V4 'and V1' via 27b. As a result, the voltages V4 'and V1' output from the buffer circuits 27a and 27b change according to the display data as shown in FIGS. 3A and 3B. Then, the buffer circuit 27a,
The voltages V4 'and V1' output from 27b are sent to the common side analog multiplexer 5 in FIG. The analog multiplexer 5 includes the non-selection voltage control circuit
The voltages V1 'and V4' supplied from 11 and the voltages V0 and V5 supplied from the LCD drive voltage generation circuit 6 are selected according to the output signal of the common side drive circuit 4 to drive the common electrode of the LCD panel 7. . As a result, the non-selection signal waveform of the common electrode is
As shown in FIGS. 4 (A) and 4 (B), the voltage level of the portion corresponding to the spike increases, and the effective value is corrected.

On the other hand, the analog multiplexer 25, shown in FIG.
In the resistance dividing circuit 26 and the buffer circuit 27, the same processing as that of the circuit of FIG. 6 is performed, and as shown in FIGS. 3A and 3B, the voltage V _M ′ that changes according to the display data. Is created. Then, the voltage V _M 'is sent to the common-side analog multiplexer 5 in FIG. 2, FIG. 4 (A), the spike portion effective value in the non-selection signal waveform of the common electrode as shown in (B) Is corrected.

[Effects of the Invention] As described above in detail, according to the present invention, the non-selection voltage value supplied to the common electrode of the liquid crystal display panel is changed by a small amount according to the display data for each modulation period for controlling the gradation. Therefore, it is possible to eliminate the influence of spikes generated on the common electrode at the time of non-selection, and to reliably prevent the tailing phenomenon.

[Brief description of the drawings]

FIGS. 1 to 7 show an embodiment of the present invention. FIG. 1 is a block diagram showing a circuit configuration when both common signals and segment signals are quaternary, and FIG.
FIG. 3 is a block diagram showing a circuit configuration when the segment signal is binary in value, FIG. 3 and FIG. 4 are common signal waveform diagrams for explaining the operation of correcting the pull-selection voltage with respect to the common electrode, and FIG. 5 and 6 are block diagrams showing details of the non-selection voltage control circuit, FIGS. 6 and 7 are circuit diagrams showing details of main parts in FIG. 5, and FIG. 8 is a common circuit in a conventional liquid crystal driving system. FIG. 9 is a block diagram showing a circuit configuration when both the signal and the segment signal are quaternary. FIG. 9 shows a conventional liquid crystal drive system in which the common signal is ternary and the segment signal is 2
10 is a block diagram showing a circuit configuration in the case of values, FIG. 10 is a diagram showing ideal liquid crystal driving signal waveforms in the liquid crystal driving method of FIGS. 8 and 9, and FIG. 11 is an equivalent circuit of a liquid crystal display panel. FIG. 12 is a diagram showing a non-selection voltage waveform of the common electrode in the liquid crystal driving method shown in FIGS. 8 and 9, and FIG. 13 is a diagram showing a gradation signal waveform when the display data is 3 bits. . 1 ... display control circuit, 2 ... segment side drive circuit, 3
………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………? Control circuit, 21 ... decoder,
22a to 22f: Counter, 23f to 23f: Latch circuit, 24:
... Data selector, 25 ... Analog multiplexer,
26: resistor division circuit, 27: buffer circuit.

Claims (1)

(57) [Claims] 1. A liquid crystal display panel having a plurality of common electrodes and segment electrodes arranged in a matrix, segment electrode driving means for driving segment electrodes of the liquid crystal display panel in accordance with display data, and the liquid crystal display panel. Common electrode driving means for sequentially selecting and driving the common electrodes, and the display data is classified into a plurality of levels for each common electrode scanning period, counted for each classification, and the common electrode driving means is counted according to the count value for each classification. A non-selection voltage control means for correcting a common electrode non-selection voltage value supplied to the liquid crystal display.