JPH0968951A - Liquid crystal display device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a liquid crystal display device having good display quality by providing an initialization circuit for holding a display active signal supplied as a display control signal in the inactive potential until a bias voltage reaches a prescribed voltage. SOLUTION: A display signal receiving circuit 5 for receiving a display signal (including a display control signal and a picture signal) outputted from an information processor performing a prescribed processing and outputting it comprises a buffer circuit complied with the respective signals and an AC coupling capacitor C used for potential conversion of the display control signal supplying to an initialization circuit 6 and a scanning circuit 2. By using a delay circuit composed of a shift register and an AND circuit, the initialization circuit 6 holds a display active (DISP-OFF) signal as the display control signal on an inactive level for a fixed time being previously set after an initial pulse of a frame(FLM) signal is sent. Consequently, the appearance of a moire-like display on a display screen is prevented and the problem of display quality such that the screen becomes gradually bright is canceled.

Description

Detailed Description of the Invention

[0001]

[0001] The present invention relates to a liquid crystal display device.

[0002]

2. Description of the Related Art Conventionally, in driving a liquid crystal panel having mutually orthogonal electrode groups, that is, in so-called simple matrix driving, a high voltage level voltage is sequentially applied to the electrodes of one electrode group and the high voltage level voltage is applied. Line-sequential scanning is performed in which a voltage according to an image signal is applied to the other electrode group while being applied, and polarity is reversed as disclosed in Japanese Patent Publication No. 57-57718 in order to prevent direct current from being applied to the liquid crystal. I was doing.

That is, for example, it is assumed that there are voltages VL and VH and intermediate voltages Vb1 to Vb4. Then, alternating polarity driving is performed by inverting the polarity for each frame. By applying VL to the Yn electrode and Vb1 to the other Y electrodes at a specific time in the first frame, Y
n is scanned, and when it is desired to display on the X electrode group (selected pixel) in accordance with the image signal for one row corresponding to Yn, VH,
When it is not desired to display (non-selected pixel), Vb2 is given. Then, in the next frame, YH is scanned by applying VH to the electrode of Yn and Vb4 to the other Y electrode at a specific time, and on the other hand, the X electrode according to the image signal for one row corresponding to Yn. The group is given VL when it is desired to be displayed and Vb3 when it is not desired to be displayed. In this way, the VL-VH voltage is applied to the pixel to be displayed, but the voltage of VH or VL is applied to the scanning side electrode, and the voltage of VL or VH is applied to the signal electrode, thereby selecting the pixel and converting it into an alternating current. I went.

Such a method is sufficient as long as scan side and signal side drive circuits (integrated circuits) capable of handling a relatively large voltage are prepared. For example, the number of scan electrodes is 3 to 4.
In the case of a book, a low voltage of several volts is sufficient, but if the number of scan electrodes increases and the number of time divisions increases accordingly, the voltage between VL and VH increases in order to secure an effective value. Then +20 to +35 volts are required. As a result, a large capacitive load current due to the liquid crystal flows when the AC signal is switched, and power consumption increases. In addition, recent liquid crystal display devices have 640 × 480 pixels (VGA) to 1024 RGB × 768 pixels (color X
GA) (the number of pixels on one line on the signal side is 3072), which requires a high-speed and high-voltage integrated circuit because the data transfer time and other operations are speeded up. However, for an integrated circuit, high speed and high withstand voltage are conflicting specifications, making it difficult to realize.

[0005]

Therefore, the applicant of the present application is
A liquid crystal display device satisfying such conflicting specifications was proposed by Japanese Patent Application No. 6-279223. However,
It has been found that this liquid crystal display device has the following new problems. That is, depending on the type of equipment connected to the liquid crystal display device, there is a device that outputs a display active (DISP-OFF) signal as a display control signal almost simultaneously with a frame (FLM) signal and a clock signal. When the device is used by connecting to a device that outputs the DISP-OFF signal early, the DISP-OFF signal is output before the bias voltage for driving the liquid crystal output from the DC-DC converter or the like after the power is turned on reaches the specified voltage. Is active (H
Level). In such a case, a screen-like display is likely to appear on the display screen, and since the voltage supplied to the liquid crystal rises to a specified value after the display is activated, the screen does not become bright at once but gradually. Be brighter,
There is a problem that the display quality is degraded. Then, this invention makes it a subject to solve such a newly generated problem.

[0006]

According to the present invention, there is provided a liquid crystal panel having electrode groups which are orthogonal to each other, and a scanning circuit which selects one of positive and negative selection voltages and supplies it as a scanning voltage to one electrode group of the liquid crystal panel. And a signal circuit for applying to the other electrode group of the liquid crystal panel a difference voltage in the vicinity of an intermediate value between the positive selection voltage and the negative selection voltage of the scanning circuit according to an image signal, and to the scanning circuit and the signal circuit. In a liquid crystal display device including a power supply circuit that supplies a voltage of a predetermined bias value,
Display active supplied as a display control signal (DISP-O
An FF) signal is held at an inactive potential until the bias voltage reaches a specified voltage.

Further, the initialization circuit is provided with a holding time adjusting means for the non-active potential.

[0008]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a block diagram of a liquid crystal display device according to an embodiment of the present invention. Reference numeral 1 is a liquid crystal panel having mutually orthogonal electrode groups, for example, a field effect liquid crystal such as a super twist nematic liquid crystal display can be used. The electrodes of these liquid crystal panels 1 form a so-called simple matrix and do not have active elements at pixel intersections. Reference numeral 2 denotes a scanning circuit for applying a scanning voltage to one electrode group of the liquid crystal panel 1, which has positive and negative voltages VH (+30 to +20 volts) and VL (-25 to -15 volts) and an intermediate voltage VM.
One of (about +2.5 V) is selected and supplied to a predetermined electrode, of which VH and VL are selection voltages. Reference numeral 3 is a signal circuit for applying a voltage according to an image signal to the other electrode group of the liquid crystal panel 1, and two types of difference voltage V1 (near the intermediate value between the positive selection voltage VH and the negative selection voltage VL of the scanning circuit 2). + 4V), V0 (+ 1V)
Is selectively supplied to the electrodes according to the image signal.

A power supply circuit 4 supplies a voltage of a predetermined bias value to the scanning circuit 2 and the signal circuit 3, and includes a DC-DC converter 41 for stepping up / down a DC voltage and a resistance dividing circuit for dividing a predetermined output voltage thereof. And outputs at least positive and negative selection voltages VH and VL, difference voltages V1 and V0, and intermediate voltage VM, and more preferably, drive voltage Vic of scanning circuit 2
Vlog (-20 to -1) for supplying (+5 V)
0 volt) or the drive voltage Vis (VSS-VD) of the signal circuit 3
D: +5 V) is also supplied.

The above voltage relationship is shown in FIG. This figure shows the DC voltage supplied (VSS: 0 volt, VDD: +5).
It shows the case where each voltage value is generated based on
The supplied voltage level is used as it is as the drive voltage Vis of the signal circuit 3, and the difference voltage V1, V
Get 0. On the other hand, the DC-DC converter 41 causes 0
Positive and negative selection voltages VH and VL from the volt line (VSS)
And a power supply VAH (+7.
5V) and VAL (about -2.5V) are generated, and Vlog for the drive voltage Vic of the scanning circuit 2 is generated from the + 5V line (VDD). These selection voltages V
An intermediate voltage VM is obtained by positioning the potentials of H and VL and the difference voltages V1 and V0 relative to each other. As described above, when only one DC power supply is applied, it is efficient and preferable to generate the selection voltage from one of the voltages, with the center of the voltage being the intermediate voltage VM. The magnitudes of the selection voltage and the differential voltage are obtained according to the voltage averaging method, and for example, 1
In case of / 240 duty driving, the optimum bias value is 1:
It is 16.5, and the differential voltage is 4.3 V and 0.7 V for the selected voltage of 30 V.

A display signal receiving circuit 5 receives a display signal (including a display control signal and an image signal) output from an information processing device such as a personal computer, performs a predetermined process and outputs the display signal. In addition to the buffer circuit corresponding to each signal, is provided with an initialization circuit 6 as shown in FIG. 2, an AC coupling capacitor C used for potential conversion of a display control signal supplied to the scanning circuit 2, and the like. The main part of the potential conversion circuit is built in the drive LSI forming the scanning circuit 2.

The initialization circuit 6 is, as shown in FIG. 2, a shift register 6 including a plurality of flip-flops (F / F).
1, a voltage detection circuit 62 for detecting that the supply voltage VDD has risen to a predetermined value (about +3.5 volts) and outputting a signal (DT), and two AND gates 63, 64. First stage F / F which is input to shift register 61
The output (DT) of the voltage detection circuit 62 is input to the data (D) terminal and the clear (CLR) terminal of each F / F, and each F / F is input.
A frame (FLM) signal as a display control signal is input to the F clock (CK) terminal. And DC
The output (S1) of the first stage F / F and the output (DT) of the voltage detection circuit 62 to the AND circuit 63 in order to generate an ON / OFF signal for instructing the start and stop of the operation of the DC converter 41. The DC-DC converter 41 is started to operate based on the initial pulse of the FLM signal after the power is turned on.

Further, the display active (DISP-OFF) signal as the display control signal is the DC-DC converter 4.
In order to cope with the case where the output of No. 1 is sent before it is stabilized, in order to ensure a time longer than the time T1 (for example, 40 ms) required for the output of the DC-DC converter 41 to be stable, the pulse of the FLM signal is secured. The F / F output (S2) of a predetermined stage (for example, the seventh stage) set based on the interval (for example, 8 ms) and the DISP-OFF signal are input to the AND gate 64, and the initial pulse of the FLM signal is sent. Until the time T2 (for example, 56 ms) longer than the time T1 has elapsed, the DISP-OFF signal is forcibly held at the L level which is the inactive state, and after the 7th pulse of the FLM signal, the DIS
The P-OFF signal is output as it is. The scanning circuit 2 and the signal circuit 3 are in the active state without applying the voltage to the liquid crystal panel 1 while the DISP-OFF signal output from the AND circuit 64 is at the L level which is the inactive state. When the H level is reached, a predetermined bias voltage is applied to the liquid crystal panel 1.

Scan circuit 2 including DISP-OFF signal
Since the display control signal sent to the scanning circuit 2 has a potential level different from that of the driving voltage of the scanning circuit 2, the display control signal is sent to the scanning circuit 2 via the AC coupling capacitor C, and the potential conversion circuit built in the scanning circuit 2 converts the potential. To be done. The above voltages and signal timings are shown in FIG.

The liquid crystal display device scans / drives with a voltage waveform as shown in FIG. 5a, and the voltage applied to the liquid crystal is as shown in FIG. still,
In these drawings, the scanning voltage shows a state in which a positive or negative selection voltage is selected at a constant cycle, but the differential voltage output from the signal circuit 3 has two values depending on the image signal and the polarity inversion. Since which of the two is selected is changed, both of the two differential voltages are expressed by expressing them on a piece of abacus, and both differential voltages are selected as shown in the figure. Neither is the voltage waveform changing gently.

Due to this driving, the output stage of the integrated circuit of the scanning circuit 2 requires a withstand voltage approximately double that of the conventional one, but it is a low-speed process corresponding to the number of scanning lines and one of the three potentials at the output stage. Since one of them is selected, a large current does not occur at the time of switching the AC signal, and the waveform collapse that is the basis of the crosstalk generation, which is often seen in the past, is extremely unlikely to occur. On the other hand, the signal circuit 3 is driven at a low voltage of only 5 V in the above example, and not only is it suitable for high-speed driving, but also the area of the integrated circuit can be made small. However, it is preferable that the driving element having a narrow width can be used / arranged even if it is cut off.

Even if the DISP-OFF signal as a display control signal is sent simultaneously with the FLM signal or with a very short time delay immediately after the power is turned on, the DISP-O is sent.
The scanning circuit 2 holds the FF signal forcibly at the deactivation level until the bias voltage for driving the liquid crystal stabilizes at the specified voltage.
The voltage application to the liquid crystal by the signal circuit 3 is prohibited, and the FLM
The DISP-OFF signal is output after observing the time required for the liquid crystal driving bias voltage to stabilize at the specified voltage based on the count of pulse signals such as signals, and based on this, the liquid crystal by the scanning circuit 2 and the signal circuit 3 is output. Since a voltage is applied to the display screen, it is possible to prevent the interdigital display from appearing on the display screen and solve the problem of display quality such as the screen gradually becoming brighter.

Further, in the scanning circuit 2 having different potential levels, when a constant voltage such as a DISP-OFF signal is received by AC coupling, the voltage is unstable when the power is turned on. Although the erroneous setting may continue, since the DISP-OFF signal is initialized once when the power is turned on, the erroneous setting can be prevented in advance.

In the above example, the DISP-OFF signal is delayed by using a delay means including a shift register 61 and an AND circuit 64, and a fixed time set in advance after the initial pulse of the FLM signal is sent. Although the deactivation level is held, the initialization circuit 6 may be provided with an adjusting means for adjusting the holding time of the deactivation level so that the adjustment can be easily performed at the time of manufacturing or inspection and repair. For example, as shown in FIG. 6, the outputs of the F / Fs of the plurality of stages of the shift register 61 are input to a selection means including, for example, a rotary switch 65 or other digital selection circuits, among which, It is also possible to arbitrarily select one output of the above and input it to the AND gate 64. In this way, the time until the bias voltage for driving the liquid crystal is stably maintained at the specified voltage is D
Even when it fluctuates due to the C-DC converter 41 and its peripheral circuits, the activation timing of the DISP-OFF signal can be easily adjusted, and the display quality can be easily improved.

[0020]

As described above, according to the present invention, it is possible to provide a liquid crystal display device having a good display quality.

[Brief description of drawings]

FIG. 1 is a block diagram of a liquid crystal display device according to an embodiment of the present invention.

FIG. 2 is a partial circuit diagram relating to an initialization circuit of a receiving circuit according to an embodiment of the present invention.

FIG. 3 is a time chart of voltages and signals according to the embodiment of the present invention.

FIG. 4 is a time chart of voltage according to the embodiment of the present invention.

FIG. 5 is a drive waveform diagram according to the embodiment of the present invention, in which a indicates an output voltage of the scanning circuit and the signal circuit, and b indicates a voltage applied to the liquid crystal.

FIG. 6 is a partial circuit diagram of an initialization circuit according to an embodiment of the present invention.

[Explanation of symbols]

 1 liquid crystal panel 2 scanning circuit 3 signal circuit 4 power supply circuit 5 receiving circuit 6 initialization circuit

Claims (2)

[Claims] 1. A liquid crystal panel having mutually orthogonal electrode groups, and a scanning circuit for selecting one of positive and negative selection voltages and applying as a scanning voltage to one electrode group of the liquid crystal panel,
A signal circuit for applying to the other electrode group of the liquid crystal panel a difference voltage in the vicinity of an intermediate value between the positive selection voltage and the negative selection voltage of the scanning circuit according to an image signal, and a predetermined voltage for the scanning circuit and the signal circuit. In a liquid crystal display device including a power supply circuit that supplies a bias voltage, a display active (DISP-OFF) signal supplied as a display control signal is held at a non-active potential until the bias voltage reaches a specified voltage. A liquid crystal display device having an initialization circuit. 2. A liquid crystal panel having electrode groups which are orthogonal to each other, and a scanning circuit which selects one of positive and negative selection voltages and supplies it as a scanning voltage to one electrode group of the liquid crystal panel.
A signal circuit for applying to the other electrode group of the liquid crystal panel a difference voltage in the vicinity of an intermediate value between the positive selection voltage and the negative selection voltage of the scanning circuit according to an image signal, and a predetermined voltage for the scanning circuit and the signal circuit. In a liquid crystal display device including a power supply circuit that supplies a bias voltage, a display active (DISP-OFF) signal supplied as a display control signal is held at a non-active potential until the bias voltage reaches a specified voltage. A liquid crystal display device, wherein an initialization circuit is provided, and the retention time adjusting means for the non-active potential is provided in the initialization circuit.