JP3213530B2 - Liquid crystal display - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[0001] The present invention relates to a liquid crystal display device.

[0002]

2. Description of the Related Art Conventionally, in driving a liquid crystal panel having electrode groups orthogonal to each other with a liquid crystal layer interposed therebetween, that is, so-called simple matrix driving, a voltage of a higher voltage level is sequentially applied to the electrodes of one of the electrode groups. Line-sequential scanning is performed in which a voltage corresponding to an image signal is applied to the other electrode group while a high-level voltage is being applied. Further, since a direct current is not applied to the liquid crystal, it is disclosed in Japanese Patent Publication No. 57-57718. Polarity inversion so that

That is, for example, it is assumed that there are voltages VL and VH and intermediate voltages Vb1 to Vb4. Then, the AC driving is performed by inverting the polarity for each frame as an example. By applying VL to the Yn electrode at a specific time in the first frame and applying Vb1 to the other Y electrodes, Y
n is scanned, and VH is displayed on the X electrode group according to the image signal for one row corresponding to Yn (selection pixel).
When display is not desired (non-selected pixel), Vb2 is given. Then, in the next frame, VH is applied to the Yn electrode at a specific time, and Vb4 is applied to the other Y electrodes to scan Yn. On the other hand, the X electrode is applied according to the image signal for one row corresponding to Yn. VL is given to the group when it is desired to display it, and Vb3 is given when it is not desired to display it. In this manner, the VL-VH voltage is applied to the pixel to be displayed, but the VH or VL voltage is applied to the scanning electrode, and the VL or VH voltage is applied to the signal electrode, thereby selecting and alternating the pixel. I went.

Such a method is only required if a scanning circuit and a signal side driving circuit (integrated circuit) capable of handling a relatively large voltage are prepared. For example, the number of scanning electrodes is three to four.
In the case of a book, a low voltage of several volts is sufficient, but when the number of scanning electrodes increases and the number of time divisions increases, the voltage between VL and VH increases to secure an effective value. Requires +20 to +35 volts. As a result, a large capacitive load current due to the liquid crystal flows when the AC signal is switched, and the power consumption increases. In addition, recent liquid crystal display devices have 640 × 480 pixels (VGA) to 1024 RGB × 768 pixels (color X).
GA) (the number of pixels per line on the signal side is 3072), which requires a high-speed and high-withstand-voltage integrated circuit because the data transfer time and other operations become faster. However, for an integrated circuit, high speed and high withstand voltage are conflicting specifications, making it difficult to realize.

[0005]

SUMMARY OF THE INVENTION Accordingly, the applicant of the present application
A liquid crystal display device satisfying such conflicting specifications has been proposed in Japanese Patent Application No. Hei 6-279223. However,
It has been found that this liquid crystal display device has the following new problem. That is, some types of devices connected to the liquid crystal display device output a display enable (DISP-OFF) signal as a display control signal almost simultaneously with a frame (FLM) signal or a clock signal. When the device is used by connecting to a device that outputs the DISP-OFF signal early, the DC
Before the bias voltage for driving the liquid crystal output from the DC converter or the like reaches the specified voltage, the DISP-OFF signal supplied to the scanning circuit or the signal circuit may be in an active state (H level). In such a case, an interdigital display is likely to appear on the display screen, and the voltage supplied to the liquid crystal rises to a specified value after the DISP-OFF signal becomes active, so that the screen becomes bright at once. However, there is a problem that the display quality is deteriorated, for example, the brightness is gradually increased.

Further, the control of the DC-DC converter for generating the liquid crystal driving bias voltage is performed based on the voltage value of the power supply voltage VDD regardless of the state of the DISP-OFF signal. The power supply voltage has been reduced (changed from 5 volts to 3 volts)
If the fall time of the power supply voltage VDD in the display-off sequence is shortened, the DC voltage is reduced before the power supply voltage VDD falls.
-There is no time margin for lowering the output voltage of the DC converter.

Accordingly, the present invention has as its main object to solve such a newly generated problem.

[0008]

According to the present invention, there is provided a liquid crystal panel having electrode groups orthogonal to each other, a scanning circuit for applying a scanning voltage to one electrode group of the liquid crystal panel, and a scanning circuit for applying the scanning voltage to the other electrode group of the liquid crystal panel. A liquid crystal display device comprising: a signal circuit that supplies a signal voltage corresponding to an image signal; and a power supply circuit that converts a supplied power supply voltage to supply a voltage having a predetermined bias value to the scanning circuit and the signal circuit. A conversion circuit for supplying an external display activation signal externally supplied as a display control signal, and supplying an internal display activation signal to the scanning circuit and the signal circuit; A voltage detection circuit for detecting whether the voltage is equal to or greater than a value, and a detection signal of the detection circuit being delayed by a time longer than a time required until an output voltage of the power supply circuit rises to a specified voltage. A delay circuit that outputs the signal as a display activation signal; and an initialization circuit that generates an initialization signal for initializing the delay circuit, wherein the initialization circuit has a power supply voltage having reached a predetermined value. When there is no external display activation signal, or when the external display activation signal is in a deactivated state, the delay circuit is held in an initialized state, and the internal display activation signal output from the delay circuit is deactivated by this initialization. It is characterized in that it is configured to be held in a state.

Further, the delay circuit may be constituted by a shift register, and may be configured to supply an output of a preceding stage thereof as a control signal of a circuit for performing the voltage conversion.

[0010]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a block diagram of a liquid crystal display device according to an embodiment of the present invention. Reference numeral 1 denotes a liquid crystal panel having electrode groups orthogonal to each other with a liquid crystal layer interposed therebetween, for example, using a field effect liquid crystal such as a super twisted nematic liquid crystal display. it can. These electrodes of the liquid crystal panel 1 constitute a so-called simple matrix and have no active elements at pixel intersections. Numeral 2 denotes a scanning circuit for applying a scanning voltage to one electrode group of the liquid crystal panel 1, and a positive / negative voltage VH (+3
0 to +20 volts), VL (-25 to -15 volts), and an intermediate voltage VM (around +2.5 volts) to be supplied to a predetermined electrode.
VL is a selection voltage. Reference numeral 3 denotes a signal circuit for applying a voltage corresponding to an image signal to the other electrode group of the liquid crystal panel 1, and two kinds of difference voltages V1 (near the intermediate value between the positive selection voltage VH and the negative selection voltage VL of the scanning circuit 2). +2 to +4.5 volts), V0
(+0.5 to +2 volts) is selectively supplied to the electrodes according to the image signal. The scanning circuit 2 and the signal circuit 3
It is constituted by an integrated circuit element operable at a power supply voltage VDD of +3 to +5 volts.

Reference numeral 4 denotes a supply of a power supply voltage VDD (VSS: 0 volts, VDD: +3 to +5 volts) as a DC power supply from an external device, and supplies a voltage having a predetermined bias value to the scanning circuit 2 and the signal circuit 3. The power supply circuit includes a DC-DC converter 41 that steps up and down a DC power supply voltage supplied from an external device, a resistance dividing circuit that divides a predetermined output voltage thereof, and the like, and includes at least positive and negative selection voltages VH, VL and a difference voltage V1, V0 and the intermediate voltage VM, and more preferably, the power supply voltage VDD for logic of the scanning circuit 2 and the signal circuit 3.
(+3 to +5 volts) and a bias voltage VEE of the signal circuit 3 (around +5 volts).

FIG. 4 shows the above voltage relationship. This figure shows the supplied power supply voltage (VSS: 0 volts, VDD:
+3 volts), and the supplied voltage level is used as it is as the logic voltage VDD of the scanning circuit 2 and the signal circuit 3. On the other hand, the positive / negative selection voltages VH and VL starting from the 0 volt line (VSS) by the DC-DC converter 41,
A power supply VAH (approximately +7 volts) and VAL (approximately -2 volts) and a bias voltage VEE (approximately +5 volts) for a circuit (element) such as an operational amplifier are generated. The intermediate voltage VM is obtained by positioning the potentials of the selection voltages VH, VL and the difference voltages V1, V0 with each other. The magnitudes of the selection voltage and the difference voltage are obtained according to the voltage averaging method. For example, in the case of driving at 1/240 duty, the optimum bias value is 1: 16.5, The difference voltage is 4.3 volts and 0.7 volts.

A display signal receiving circuit 5 receives a display signal (including a display control signal and an image signal) output from an external device such as a personal computer, performs predetermined processing, and outputs the processed signal. In addition to a buffer circuit (not shown) corresponding to each signal, a conversion circuit 6 as shown in FIG. 2 is provided.

As shown in FIG. 2, the conversion circuit 6 includes a delay circuit 61 composed of a shift register constituted by a plurality (for example, eight) of flip-flops (FF1 to 8);
In order to supply a shift clock pulse to the shift register, a pulse signal, preferably a frame (FLM), supplied from an external device as one of display control signals
A clock constituted by a flip-flop (FF0) in which a frame (FLM) signal is connected to a clock terminal (CK) and an inverted output is connected to a data terminal (D) so as to divide and output the signal (60H _Z ). A circuit 62, a voltage detection circuit 63 for detecting that the power supply voltage VDD has risen to a predetermined value (about +2.5 volts) and outputting a detection signal (DT), and a circuit for initializing the delay circuit 61 An initialization circuit 64 and the like constituted by an AND gate for generating a signal are provided. The input terminals of the initialization circuit 64 include:
An output (DT) of the voltage detection circuit 63 and a display activation (external DISP-OFF) signal supplied for controlling display on / off as one of display control signals from an external device are supplied. The output of the initialization circuit 64 is
Is connected to the clear (CLR) terminal of each of the FFs 1 to 8 when the power supply voltage VDD does not reach the predetermined value or when the external DISP-OFF is in the inactive (L level) state. , The delay circuit 61 is maintained in the initial state.

The input terminal of the delay circuit 61, ie, the first stage F
The output (DT) of the voltage detection circuit 63 is input to the data (D) terminal of F1. The output of a predetermined stage of the delay circuit 61, preferably the output terminal (Q) of the first stage FF1, is D
ON / OFF for controlling the C-DC converter 41
Connected to OFF terminal. The delay circuit 61 has a DC-D
The number of FFs constituting the delay circuit 61 and the pulse of the clock circuit 62 are set so as to obtain a delay time T2 longer than the time T1 (for example, 40 to 50 ms) required for each output voltage of the C converter 41 to rise to the specified voltage. The delay time T2 (for example, 112 ms) is set based on the cycle.

The operation of the above configuration will be described with reference to FIGS. When the supply of the power supply voltage VDD and the display signal from the external device is started in accordance with the display ON sequence of the external device, the power supply voltage VDD rises to a predetermined voltage, and the detection signal (DT) of the power supply voltage VDD by the voltage detection circuit 63. )
Is supplied to the delay circuit 61 and the clock circuit 6
2 receives the supply of the FLM signal and starts generating a predetermined clock pulse. Here, the detection signal (DT) of the power supply voltage VDD by the voltage detection circuit 63 and the external DISP-OFF
During the period until both become H level, the delay circuit 61 is held in the initialized state by the output of the initialization circuit 64, so that the internal DISP-OFF output from the delay circuit 61 is output.
Are kept in an inactive (L level) state. Internal DIS
While P-OFF is kept in the inactive (L level) state, the scanning circuit 2 and the signal circuit 3 are kept in the inactive state.

When the output of the initialization circuit 64 goes to the H level, the delay circuit 61 starts operating, and at the same time, the FF 1 supplies an ON signal to the DC-DC converter 41 to output a signal D.
When the C-DC converter 41 starts operating and the time T1 elapses, the rising of various bias voltages ends. When the time T2 elapses following the elapse of the time T1, the internal DISP-OFF output from the delay circuit 61 is activated (H
Level) state. When this internal DISP-OFF is given to the scanning circuit 2 and the signal circuit 3, each circuit is activated and starts the liquid crystal driving operation. At this point, since the prescribed bias voltage has already been supplied to the scanning circuit 2 and the signal circuit 3, the display on the liquid crystal panel can be performed immediately.

If the external device holds the external DISP-OFF signal at the L level for a short time in a normal state after the display ON sequence is completed, for example, when checking the VRAM, the external DISP-OFF signal is output. In response, the initialization circuit 64 initializes the delay circuit 61.
By this initialization, the DC-DC converter 41 has an OF
Since the F-signal is given for a short time and the DC-DC converter 41 temporarily stops operating and restarts operation, it takes a predetermined time for each output voltage to rise to a predetermined voltage again. For a longer time T2,
Since the scanning circuit 2 and the signal circuit 3 are held in an inactive state by holding the internal DISP-OFF in an inactive (L level) state, the scanning circuit 2 and the signal circuit are held before the bias voltage rises to a specified value. 3 can be operated to reduce the inconvenience of deteriorating display quality.

Further, since the stop of the DC-DC converter 41 can be controlled by the external DISP-OFF, it is possible to prevent the liquid crystal panel 1 from being deteriorated by residual charges. That is, in the display off sequence, any time desired on the external device side,
For example, before the power supply voltage VDD falls, the external DISP-
When OFF is inactivated (L level), the delay circuit 61 is in the initial state and the output terminal of the first stage FF1 is at L level.
Level, which turns on the DC-DC converter 41
/ OFF terminal, the operation of the DC-DC converter 41 stops, and the bias voltage for driving the liquid crystal is changed to the power supply voltage V
It is possible to prevent the liquid crystal panel 1 from being deteriorated due to residual charges by falling before the falling of the DD.

Note that the external DISP-OFF is deactivated (L
If the supply of the power supply voltage VDD is stopped before the state is switched to the (level) state, the voltage detection circuit 63 detects a drop in the power supply voltage VDD and initializes the initialization circuit 6 based on the output.
4 initializes the delay circuit 61, so that the DC-DC converter 41 can be stopped by this initialization, and the scanning circuit 2 and the signal circuit 3 can be switched to the non-operating state. Here, between the input power supply terminals of the DC-DC converter 41, a power storage capacitor C is preferably provided in order to prolong the fall time of the power supply voltage VDD in a display off sequence or the like.

The liquid crystal display device scans and drives with a voltage waveform as shown in FIG. 5A due to the above configuration and voltage relationship, and the voltage applied to the liquid crystal is as shown in FIG. still,
In these figures, the scanning voltage shows that either the positive or negative selection voltage is selected in a fixed cycle, but the difference voltage output from the signal circuit 3 has two values according to the image signal and the polarity inversion. Which of the two differential voltages is selected changes, so that both of the two differential voltages are described in the form of an abacus piece, and both differential voltages are selected as shown in the figure. Otherwise, the voltage waveform does not change slowly.

[0022]

As described above, according to the present invention, in the display ON sequence or the normal display state, the scanning circuit and the signal circuit are kept inactive until the liquid crystal driving bias voltage rises to the specified voltage. Accordingly, it is possible to prevent the display screen from intermittent display, and to solve the problem of display quality such as the screen gradually becoming brighter.

Further, the fall of the bias voltage for driving the liquid crystal can be controlled by a display enable signal supplied from the outside. It is possible to provide a liquid crystal display device capable of dropping a liquid crystal driving bias voltage before the voltage falls.

[Brief description of the drawings]

FIG. 1 is a block diagram of a liquid crystal display device according to an embodiment of the present invention.

FIG. 2 is a circuit diagram of a conversion circuit according to an embodiment of the present invention.

FIG. 3 is a time chart of voltages and signals according to the embodiment of the present invention.

FIG. 4 is a time chart of a voltage according to the embodiment of the present invention.

FIG. 5 is a driving waveform diagram according to the embodiment of the present invention, wherein a indicates the output voltage of the scanning circuit and the signal circuit, and b indicates the voltage applied to the liquid crystal.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Liquid crystal panel 2 Scanning circuit 3 Signal circuit 4 Power supply circuit 5 Display signal receiving circuit 6 Conversion circuit

──────────────────────────────────────────────────続 き Continuation of front page (72) Inventor Akinori Matsushita 3-201 Minamiyoshikata, Tottori City, Tottori Prefecture Tottori Sanyo Electric Co., Ltd. Field surveyed (Int.Cl. ⁷ , DB name) G02F 1/133 520 G02F 1/133 545 G09G 3/36

Claims (2)

(57) [Claims] 1. A liquid crystal panel having electrode groups orthogonal to each other, a scanning circuit for applying a scanning voltage to one electrode group of the liquid crystal panel, and a signal voltage applied to the other electrode group of the liquid crystal panel in accordance with an image signal. And a power supply circuit for converting the supplied power supply voltage to supply a voltage having a predetermined bias value to the scanning circuit and the signal circuit. External display enable signal is supplied and the internal display
The conversion circuit for supplying a signal to the signal circuit and the scanning circuit is provided, the conversion circuit includes a voltage detection circuit for the power supply voltage detect whether more than a predetermined value, the power detection signal of the detection circuit Until the output voltage of the circuit rises to the specified voltage
Comprising a delay circuit for outputting as said internal display activation signal in the required delayed longer than the time, the initialization circuit for generating an initialization signal for first <br/> initialized this delay circuits The initialization circuit is configured to set the power supply voltage to a predetermined value.
Not reached, or the external display enable signal is
Holds the delay circuit in the initialized state when in the inactive state
Before the output from the delay circuit due to this initialization.
A liquid crystal display device wherein the internal display activation signal is held in a non-activated state . 2. The liquid crystal display device according to claim 1, wherein said delay circuit is constituted by a shift register and supplies an output of a preceding stage thereof as a control signal of a circuit for performing said voltage conversion. .