JPS61199979U - - Google Patents
Info
- Publication number
- JPS61199979U JPS61199979U JP8177885U JP8177885U JPS61199979U JP S61199979 U JPS61199979 U JP S61199979U JP 8177885 U JP8177885 U JP 8177885U JP 8177885 U JP8177885 U JP 8177885U JP S61199979 U JPS61199979 U JP S61199979U
- Authority
- JP
- Japan
- Prior art keywords
- signal
- mixed
- delayed
- mixed signal
- pixel
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 230000003111 delayed effect Effects 0.000 claims 5
- 238000010586 diagram Methods 0.000 description 3
- 239000002131 composite material Substances 0.000 description 1
- 238000000034 method Methods 0.000 description 1
Landscapes
- Studio Circuits (AREA)
Description
第１図は本考案によるデフオーカス回路の一実
施例を示すブロツク図、第２図ａ〜ｄは第１図に
示すデフオーカス回路の混合過程を示す図、第３
図は遅延混合回路の構成を示す図、第４図は遅延
混合回路の具体例を示すブロツク図である。
１……コンポジツト映像信号、２，４……遅延
混合回路、３，５……メモリ回路、６，７，８，
９，１０……画素、１１，１２……遅延混合部、
１３，２１……減算器、１４，１６，１８，１９
，２０，２２，２４，２６，２７，２８……レジ
スタ、１５，２３……乗算器、１７，２５……加
算器、２９，３０……端子。
FIG. 1 is a block diagram showing an embodiment of the defocus circuit according to the present invention, FIGS. 2a to d are diagrams showing the mixing process of the defocus circuit shown in FIG. 1, and FIG.
This figure shows the configuration of the delay mixing circuit, and FIG. 4 is a block diagram showing a specific example of the delay mixing circuit. 1... Composite video signal, 2, 4... Delay mixing circuit, 3, 5... Memory circuit, 6, 7, 8,
9, 10... pixel, 11, 12... delay mixing section,
13, 21...Subtractor, 14, 16, 18, 19
, 20, 22, 24, 26, 27, 28... register, 15, 23... multiplier, 17, 25... adder, 29, 30... terminal.
Claims (1)
遅延させ、第１の遅延信号を得て、該第１の遅延
信号と前記デイジタル画像信号と混合し、第１の
混合信号を得、該第１の混合信号をｎ走査線と副
搬送波の１周期分遅延させ、第２の遅延信号を得
て、該第２の遅延信号と前記第１の混合信号と混
合して、第２の混合信号を出力する第１及び第２
の遅延混合回路と、前記第２の混合信号が入力さ
れ、該第２の混合信号を１フレーム分蓄積した後
、該蓄積の順と逆方向に読み出すことができる第
１及び第２のメモリ回路とを有し、各画素の情報
が該画素を含む画面に対して、斜め方向に存在す
る画素の情報と混合されるようにしたことを特徴
とするデフオーカス回路。 Digital image signal for n scanning lines (n is odd number)
delaying a first delayed signal, mixing the first delayed signal with the digital image signal to obtain a first mixed signal, and combining the first mixed signal with one of n scan lines and subcarriers. first and second signals that are delayed by a period, obtain a second delayed signal, mix the second delayed signal with the first mixed signal, and output a second mixed signal;
a delay mixing circuit, and first and second memory circuits to which the second mixed signal is input, and after storing the second mixed signal for one frame, can be read out in a direction opposite to the order of the storage. What is claimed is: 1. A defocus circuit, characterized in that information of each pixel is mixed with information of pixels existing diagonally with respect to a screen including the pixel.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1985081778U JPH0413889Y2 (en) | 1985-06-01 | 1985-06-01 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1985081778U JPH0413889Y2 (en) | 1985-06-01 | 1985-06-01 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS61199979U true JPS61199979U (en) | 1986-12-15 |
| JPH0413889Y2 JPH0413889Y2 (en) | 1992-03-30 |
Family
ID=30628883
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1985081778U Expired JPH0413889Y2 (en) | 1985-06-01 | 1985-06-01 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0413889Y2 (en) |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS54152424A (en) * | 1978-05-20 | 1979-11-30 | Nippon Television Ind Corp | Television signal generator |
-
1985
- 1985-06-01 JP JP1985081778U patent/JPH0413889Y2/ja not_active Expired
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS54152424A (en) * | 1978-05-20 | 1979-11-30 | Nippon Television Ind Corp | Television signal generator |
Also Published As
| Publication number | Publication date |
|---|---|
| JPH0413889Y2 (en) | 1992-03-30 |
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