JPS61199664A - Semiconductor device - Google Patents

Abstract

PURPOSE:To enable the surface electrode to perform a positive bias mode drive to the back surface in high sensitivity, and moreover, to enable the gate electrode to perform a positive bias mode drive to the surface electrode in high sensitivity by a method wherein the second surface layer is formed in a state that the end part thereof is elongated a little more to the outside of the semiconductor substrate than the end parts of the first surface layer and the auxiliary emitter layer. CONSTITUTION:A second surface layer 26 is disposed in a state that the end part thereof is coming out being more elongated to the outside of the semiconductor substrate than the end part of a first intermediate layer 23. Therefore holes to be injected in a third intermediate layer 25 all run across the region where a first surface layer 22 and the second surface layer 26 are superposedly disposed. As a result, the injection efficiency of electron from the second surface layer 26 can be made to improve. By this way, the surface electrode can perform a positive bias mode drive to the back electrode in high sensitivity without being affected by the disposition of pattern on the main surface of the element, and moreover, the gate electrode can also perform a positive bias mode drive to the surface electrode in high sensitivity as well.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a bidirectional semiconductor device, particularly an alternating current switching element (
Hereinafter, it will simply be referred to as TRIAC. ) relates to a semiconductor device having the structure t-.

[Technical background of the invention and electric point between them]

Conventionally, it has a five-layer structure with alternating conductivity types and is used in AC switching semiconductors! A bidirectional semiconductor device has, for example, a structure shown in FIG. z in the diagram
tl is a P-type semiconductor layer, and FiN is formed on the P-type semiconductor layer l.
The mold half mold body conductor layer 2 and the mold semiconductor layer 3 are successively folded horizontally.

An N-type emitter layer 4 is formed in a predetermined region on the back surface side of the P-type semiconductor layer 1 at the lowest level. A back electrode 5 is formed on the surface of the P-type semiconductor layer 1 so as to be connected to the N-type emitter layer 4.

A predetermined region of the uppermost P-type semiconductor layer 3 has a predetermined r&!
An N-type emitter layer 6 and an auxiliary emitter layer 7 are arranged with a distance of J.
is formed. A surface electrode 8 is formed on and connected to the emitter layer 6. A gate electrode 9 is formed in the auxiliary emitter layer 2.

The semiconductor device JO configured in this manner has three emitter layers 4, 6.7t-, and a bias direction between the front electrode 8 and the back electrode 5, and a bias direction between the front electrode 8 and the r-meter electrode 9. By combining these, it supports four trigger modes as described below.

(1) The surface electrode 8 is negative with respect to the 'Ik surface electrode 5.
and the gate electrode 9 is in a positive path with respect to the surface electrode 5 (hereinafter referred to as I (9 mode)).

(2) When the surface electrode 8 has a negative bias with respect to the surface electrode 5 and the r-meter electrode 9 has a negative bias with respect to the surface electrode 8 (hereinafter referred to as Ie mode) 0 (3 ) When the front electrode 8 has a positive bias with respect to the back electrode 5 and the gate electrode 9 has a positive bias with respect to the front electrode 8 (hereinafter referred to as Otori e mode).

(4) A case in which the front electrode 8 has a positive bias with respect to the back electrode 5 and the gate electrode 9 has a negative bias with respect to the front electrode 8 (hereinafter referred to as "remode").

Basically, ignition is possible in any combination, but since the ignition mechanism is different for each mode,
All three modes except the Otori mode are unusable. In addition, in the case of the semiconductor device tJtlO having the above structure, the emitter layer 6 and another emitter layer 4 are overlapped 1 as shown by the width in the figure.
Since there is, I ■ mode? It has improved to some extent. That is, conventionally, a current of 50 to 100 mA was required, but the current required was reduced to about 30 mA with a current of 1. However, even if the overlapping width L' is increased unnecessarily, there is a limit to its effectiveness.

That is, this results in an increase in the ineffective region that does not contribute to energization, which in turn results in an increase in the size of the element. Further, even if the stack @L is increased while ignoring these problems, the above-mentioned effect will be saturated.

Here, the ignition mechanism of the 1■ mode will be explained. When a positive bias is applied to the r-meter electrode 9 with respect to the surface electrode 8 while the surface electrode 5 is negatively biased with respect to the surface electrode 8 , the surface electrode 8 is transferred from the gate electrode 9 into the P-type semiconductor layer 3 .
Current flows towards. This current generates a potential distribution in each part of the P-type conductor layer 3, and forms a PN junction between the end of the emitter layer 6 facing the gate electrode 9 or the part in contact with the P-type conductor layer 3 and the P-type semiconductor layer 3. As the gate current increases, the forward bias becomes stronger and stronger, and finally electrons are injected from the end A of the emitter layer 6 into the P-type conductor layer 3. The injected electrons pass through the P-type semiconductor layer 3t and reach the emitter layer 6, lowering the potential of the emitter layer 6 with respect to the P-type conductor layer 3. This potential difference makes the PN junction consisting of the N-type semiconductor layer z and the P-type half-layer 3 biased, and finally holes are injected from the P-type half-layer into the N-type semiconductor layer 2. This hole diffuses through the N- semiconductor layer 2, enters the P-type semiconductor layer 1, and finally heads toward the back titc electrode 5. Here, the first injection of electrons occurs. The area A has a width of the emitter layer 4 on the other side.
and a part of it overlaps, so that the P
The holes injected into the P-type semiconductor layer 1 move laterally through the P-type semiconductor layer 1 avoiding the emitter layer 4, and when the emitter layer 4 disappears, they move through the P-type semiconductor layer J toward the back electrode 5. move on.

□The potential generated by the lateral resistance in the region B above the emitter layer 4 of the P-type semiconductor layer l-
The PN junction formed by the emitter layer 4 is forward biased. Then, when the path is shifted sufficiently strongly, electrons from the emitter layer 4 move toward the P-type semiconductor layer 1,11k and the N-type semiconductor layer 2, and the potential of the N-type semiconductor layer 2 becomes zero.

, thereby promoting the injection of holes from the P-type conductor layer 3. This process is read sequentially and the triac reaches ignition. Here, the trigger current of mode 1 (hereinafter, IGT
It is written as I■. ] To reduce the electron emitter layer 6
By increasing the injection from the emitter layer 4 and the injection from the emitter layer 4, the total injection efficiency can be increased by xi.

Conventionally, from this point of view, a truck 17 having a gate structure as shown in FIGS. 5(A) and 5(C) has been developed. Fifth
The fourth time is corner r-tota 1f 11, same figure (5)
-, 12, 12, 12, 13, 13, 12, 12, 12, 12, 12, 13, 12, 12, 12, 12, 12, 12, 12, 12, 13, 12, 12, 12, 12, 12, 13, 12, 12, 12, 12, 12, 12, 12, 12, 12, 12, 12, 12, 12, 12, 12, 12, 12, 12, 12, 12, 12, 12, 12, 12, 12, 12, 12, 200% of these tigers 1
In all nine turns of the active wiring, the shaded portion is the emitter layer 6, and the area surrounded by the broken line is the emitter layer 4. As is clear from the figure, in order to improve IGTI(E)'t'', both emitter layers 4 and 6fl are arranged so that a part of them overlaps with each other.
The areas near the gate of the attack are enlarged and shown in Figure 6 (Fig. 6).
6 is the flow path and direction of the r-to-current. This f-
) The PN junction between the emitter layer 6 and the P-type semiconductor layer 3 is strongly biased by the current 14° Is, it;
Electron injection occurs in the region indicated by . Injection occurs from the part of the emitter layer opposite to the exit where the gate current flows from the gate electrode G into the P-type semiconductor layer 3. Tora 1 Atsu / J J, Z 2 (DVI
The cross section along IA-VIIA & is the 74th section, and Vl
The cross section taken along the line lB-VllB is shown in Fig. 7). Furthermore, the cross section along the line V-A-V-A of the truck 1 at 13 shown in Figure 3C of VC1 is the 84th section, and VIB
A cross section taken along the line -VIB is shown in FIG. Therefore, in the 74th episode, the plant ivy layer 6 was passed and the injection started.
Figure 5 (2) shows how electrons from the O normal emitter layer 4 and the N-type semiconductor layer 21% reach the P-type semiconductor layer 1.
), their terminal ends are at the same position. Therefore, some of the nine holes injected from the P-type semiconductor layer 3 by the electrons injected into the emitter layer 6 graze the edge of -NE, 1 and back electrode 5. heading to In FIG. 7 (5), the movement of the hole that has reached the P-type medium conductor layer l is seen from the direction rotated by t-90°. This is xl of improvement of e-mode! In other words, the holes that have reached the P-type medium conductor layer 1 flow laterally to the P-type semiconductor layer 1 (width region) 1 on the upper part of the emitter layer 4, and the holes from the emitter layer 4 Contributes to electron injection. However, as shown in Part 74,
Not all of the injected holes contribute, but a portion of them does not pass near the emitter layer 4 and therefore exists. On the other hand, in the 84th case, there is no invalid portion, and the reason is that it is the center gate.
An ivy layer 4 is placed around the VIA-VIA & direction of the implantation area.
This is because there is no terminal end. From this point of view, the center ff-) type 13 is considered to have an ideal structure, but in actual manufacturing, especially during assembly, the wiring with the envelope is complicated, and I didn't get a 47"7 J.

[Object of the Invention] An object of the present invention is to provide a semiconductor device that can perform highly sensitive l-mode driving without being affected by the pattern arrangement on the main surface of the element.

[Overview of the invention]

In the present invention, by forming the end of the second surface layer closer to the outside of the semiconductor substrate than the ends of the first surface layer and the auxiliary emitter layer, injected holes are prevented from reaching the back surface'1 pole ineffectively. First, it is a semiconductor device that can perform highly sensitive 1e mode driving without being influenced by the pattern arrangement on the main surface of the device, by making all components contribute to the forward bias of the second surface layer.

[Embodiments of the invention]

Embodiments of the present invention will be described below with reference to the drawings. FIG.
FIG. 3 is an enlarged plan view showing the main part of the same. 20 in the figure is a semiconductor substrate.

In the semiconductor substrate 20, element regions are formed which are isolated by a P-type ablation region 2. An emitter layer consisting of the first surface layer 22 of N conductivity type is formed on the main surface side of the element region. The first surface layer 22 is a P-conductivity type first layer provided so that a portion thereof is exposed on the main surface side.
This is the intermediate layer 23. A P-type semiconductor layer is provided.

The first intermediate layer 23 is a second intermediate layer 24 of the type N411, which is also partially exposed on the main surface side.
surrounded by a type semiconductor layer. The second intermediate layer 24 is provided with a P-type semiconductor layer consisting of a third intermediate layer 25 of P conductivity type, and constitutes the back side of the semiconductor substrate 20 . Third middle layer 2
An emitter layer 26, which is a second surface layer 26 made of N conductivity, is formed within the emitter layer 5 so that its main surface is exposed on the rear surface side. The second surface layer 26 is provided so that its southern portion extends further toward the alysis layer N21 than the first surface layer 22 and the @1 intermediate layer 23, that is, toward the outside of the semiconductor substrate 20. First surface layer 22 and first intermediate layer 23
On the main surface of
A second main electrode 28 is provided on the second surface layer 26 on which the electrode 7 is formed.

Here, the second surface layer 26 is a third layer when viewed from the surface side.
As shown in (A), (B), and (C) in the figure, it is arranged in a state extending outward from the main emitter layer (first intermediate layer 23) and the auxiliary emitter layer 3. Incidentally, in the conventional semiconductor device, the end of the N emitter I- corresponding to the second surface 1-26 has a contact trc shown by the broken edge X in FIGS. 1 and 2.

According to the semiconductor device 30 configured in this manner, the end portion of the second surface layer 26 is arranged in a state extending outward from the end portion of the first intermediate layer 23, so that As shown,
All the holes injected into the third creamy layer 1 layer 25 are located in the area where the first surface layer 22 and the second surface layer 260 overlap (the third
It flows across the area (indicated by the width in the figure). As a result, the efficiency of electron injection from the second surface layer 26 can be improved. This is because, in the Otsu mode, the improvement in ketone sensitivity depends on the amount of electrons injected from the first surface layer 22, the efficiency of hole injection from the first intermediate layer 23, and the second surface layer 26 due to holes. This is because it depends on the electron injection efficiency from .

Note that the present invention has similar effects in the Ie mode (when the first main electrode 27 is at a positive potential, the second main electrode 28 is at a negative potential, and the gate is at a negative potential with respect to the first main gauntlet electrode 27). In this case, in order to balance the IGT of each mode, the extended arrangement of the second surface layer 26 is as shown in FIG.
It is desirable to set it to a predetermined value in a divided manner as shown in (a).

Furthermore, in the present invention, since the area of the region through which the main current flows is not reduced compared to the conventional one, a highly sensitive hit-on-hit can be obtained with the same bullet size as the conventional one.

Furthermore, in the embodiments, a Brenna type device has been described, but it goes without saying that it can also be applied to a mesa type device.

〔Effect of the invention〕

As explained above, according to the semiconductor device according to the present invention,
Highly sensitive 1-mode driving can be performed regardless of the /4' turn arrangement on the main surface of the element.

[Brief explanation of drawings]

FIG. 1 line is an explanatory diagram showing a schematic configuration of an embodiment of the present invention,
FIG. 2 is a perspective view of the main parts of the same embodiment, FIG. 3 is an enlarged view of the main parts of the same embodiment, FIG. 4 is an explanatory diagram showing the schematic structure of a conventional semiconductor device, and FIG. A) (B) D i-1,
A plan view showing the main parts of a conventional semiconductor device, Part 64)C
) is an explanatory diagram showing the same essential part in an enlarged manner, and Figure 7 (2) and No. 8 Shikoku (2) are explanatory diagrams showing the same essential part as seen from a predetermined cross section. 20... Semiconductor substrate, 21... Isolation region, 22 ms 1 surface layer 1. ? s -・-1st
middle ra'j*, 24... second intermediate layer, 25... third intermediate layer, 26... second surface layer, 27... first main electrode, 28... second main electrode , 30... semiconductor device. Applicant's agent Patent attorney Takehiko Suzue Figure 7
Figure 81. Display of the case Japanese Patent Application No. 60-40520 2, Name of the invention Semiconductor device 3, Person making the amendment Relationship to the case Patent applicant (307) Floor type company Toshiba (and 1 other person) 4. Agent 5, Voluntary amendment 7. Contents of amendment +1) The scope of claims is amended as shown in the attached sheet. (2) Specification, page 5, lines 14 to 15 K: ``Reaching to the emitter layer 6, emitter layer 6'' r, -r Reaching the N-type semiconductor layer 2, ``N-type semiconductor layer 2'' I am corrected. (3) Same, page 8, line 4 K l13 Figures (A) (B) J
Correct it to "Figure 6 (4) (B)". (4) Same, on page 8, line 7, [Figure 3 (C) J is corrected to read ``Figure 6 (C).'' (5) In the same page, page 11, line 18, "second surface layer 26J" is corrected to "the surface of third intermediate layer 250 including second surface layer 26." (6) Same, on page 13, line 7, "Fig. 2 (A) -)" is corrected to "Fig. 3 (A) -)". (7) Figures 4 and 6 of the middle cylinder of the drawing (Bl is attached to Figure 4,
Figure 6 (Each correction is made as per Bl. λ Claims A first surface layer of a first conductivity type constituting a semiconductor substrate having a five-layer structure with alternating conductivity types; and a first surface layer in contact with the first surface layer. a first intermediate layer of a second conductivity type; a first main electrode connected to the exposed portion of the first intermediate layer and the t41 surface layer;
-) an electrode connected to the second intermediate layer via a third intermediate layer, and provided correspondingly so that at least a portion thereof overlaps the first surface layer and the first intermediate layer, and ,
a second surface layer of a first conductivity type, the end of which extends outward from the ends of the first surface layer and the first intermediate layer;
A semiconductor device comprising a surface layer and a second main electrode formed to be connected to the third intermediate layer.

Claims (1)

[Claims] A first surface layer of a first conductivity type constituting a semiconductor substrate having a five-layer structure with alternating conductivity types, a first intermediate layer of a second conductivity type in contact with the first surface layer, and the first intermediate layer. a first main electrode connected to an exposed portion of the first intermediate layer; a second intermediate layer of a first conductivity type in contact with the first intermediate layer; and a first main electrode connected to the exposed surface of the second intermediate layer and the first intermediate layer. a gate electrode provided as a gate electrode connected to the second intermediate layer via a second intermediate layer, and
At least a portion thereof is provided so as to overlap with the first surface layer and the first intermediate layer, and an end thereof is located outside the end of the first surface layer and the first intermediate layer. A semiconductor device comprising: an extended second surface layer of a first conductivity type; and a second main electrode formed so as to be connected to the second surface layer and the third intermediate layer.