JPH0214574A - Bi-directional thyristor - Google Patents

Bi-directional thyristor

Info

Publication number
JPH0214574A
JPH0214574A JP16435788A JP16435788A JPH0214574A JP H0214574 A JPH0214574 A JP H0214574A JP 16435788 A JP16435788 A JP 16435788A JP 16435788 A JP16435788 A JP 16435788A JP H0214574 A JPH0214574 A JP H0214574A
Authority
JP
Japan
Prior art keywords
region
semiconductor
gate
invasion
semiconductor region
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP16435788A
Other languages
Japanese (ja)
Other versions
JPH0671080B2 (en
Inventor
Yutaka Yoshizawa
吉沢 豊
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sanken Electric Co Ltd
Original Assignee
Sanken Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sanken Electric Co Ltd filed Critical Sanken Electric Co Ltd
Priority to JP63164357A priority Critical patent/JPH0671080B2/en
Priority to US07/370,385 priority patent/US4994885A/en
Publication of JPH0214574A publication Critical patent/JPH0214574A/en
Publication of JPH0671080B2 publication Critical patent/JPH0671080B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/70Bipolar devices
    • H01L29/74Thyristor-type devices, e.g. having four-zone regenerative action
    • H01L29/747Bidirectional devices, e.g. triacs

Abstract

PURPOSE:To attain high sensitivity and to improve a temperature characteristic of a gate trigger current by a method wherein the third semiconductor region had an invasion in a state of cutting deep into the fifth semiconductor layer, the invasion part is exposed to the surface of a semiconductor base body and a gate electrode is connected to the third semiconductor region at a recessed part of the invasion part. CONSTITUTION:An n4 region (the fifth semiconductor region) has a cut-into part and here an invasion part 11 of a p2 region (the third semiconductor region) is arranged. The invasion part 11 is the part masked when the n4 region is formed by impurity diffusion vertically dividing the n4 region. A narrow region 2 between an n2 region and the n4 region is utilized as a current path of a reactive current component IGTb of a gate current; further, the invasion part 11 is also utilized as its part so that an inlet of the invasion part 11 is arranged near the right end of the narrow region 2. A recess of the invasion part 11 consisting of the p2 region, that is, a tip part 11a is not coated with an insulating film 3, but the part excepting this is coated with the insulating film 3. A gate electrode G is arranged so as to cover almost the whole of the n4 region and the invasion part 11 while the invasion part 11 is connected only to the tip part 11a.

Description

【発明の詳細な説明】 [産業上の利用分野コ 本発明は一般にトライアックと呼ばれている双方向サイ
リスタに関し、更に詳細には高感度化及び温度特性がと
もに高水準に達成されている双方向サイリスタに関する
DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a bidirectional thyristor generally called a triac, and more specifically to a bidirectional thyristor that has achieved high levels of both high sensitivity and temperature characteristics. Regarding thyristors.

[従来の技術及び発明が解決すべき課題]双方向サイリ
スタ(双方自進阻止3端子サイリスタ)即ちトライアッ
クは交流電流の制御を行うスイッチとしてモーター制御
回路等の電子回路に広く使用されている。第8図〜第1
1図に示す従来の双方向サイリスタは、第1導電型(n
型)の第1の半導体領域n1 (以下、単にn1領域と
呼ぶ)と、このn1領域の一方の側(下側)に接してい
る第2導電型(p型)の第2の半導体領域P1 (以下
、単にP1領域と呼ぶ)と、n1領域の他方の側(上側
)に接している第2導電型(p型)の第3の半導体領域
P2  (以下、単にp2領域と呼ぶ)とから成るシリ
コン半導体基体1を備えている。なお、n1領域は出発
母材であるn型シリコン半導体基板から成る一P1領域
及びP2領域は共に不純物拡散によって形成され、基体
1の上面側に配役されているp2領域はn1領域によっ
て囲まれている。P2領域の中には表面が露出するよう
に第1導電型(n型)の第4の半導体領域n (以下、
単にn2領域と呼ぶ)と第5の半導体領域n (以下、
単にn4領域と呼ぶ)が不純物拡散で形成されている。
[Prior Art and Problems to be Solved by the Invention] Bidirectional thyristors (bidirectional self-progression three-terminal thyristors), or triacs, are widely used in electronic circuits such as motor control circuits as switches for controlling alternating current. Figure 8-1
The conventional bidirectional thyristor shown in Figure 1 is of the first conductivity type (n
a first semiconductor region n1 (hereinafter simply referred to as n1 region) of a type (type) and a second semiconductor region P1 of a second conductivity type (p type) that is in contact with one side (lower side) of this n1 region. (hereinafter simply referred to as the P1 region) and a third semiconductor region P2 of the second conductivity type (p type) that is in contact with the other side (upper side) of the n1 region (hereinafter simply referred to as the p2 region). A silicon semiconductor substrate 1 is provided. Note that the n1 region is made of an n-type silicon semiconductor substrate that is the starting material. Both the P1 region and the P2 region are formed by impurity diffusion, and the p2 region located on the upper surface side of the base 1 is surrounded by the n1 region. There is. Inside the P2 region, a fourth semiconductor region n (hereinafter referred to as
(simply referred to as the n2 region) and the fifth semiconductor region n (hereinafter referred to as
(simply referred to as an n4 region) is formed by impurity diffusion.

91領域の中には第1の導電型(n型)の第6の半導体
領域n3 (以下、単にn3領域と呼ぶ)が不純物拡散
で形成されている。半導体基体1の側面領域には第2導
電型(p型)の第7の半導体領域P3  (以下、単に
23領域と呼ぶ)が不純物拡散によって形成されている
。このP3領域は素子分層前の半導体ウェハの状態にお
ける上面及び下面からの不純物拡散によって21領域に
連続するように形成されたものである 第9図から明らかなようにn 型領域及びP2領域の平
面形状は略四角形であり、n2領域は92領域の約17
3程度の面積となるように形成されている。n 領域は
22領域の約178程度の小面種領域である。第8図〜
第11図の双方向サイリスタではn4領域が22領域の
1つの角に近接配置されたコーナーケ゛−ト構造の双方
向サイリスタとなっている。なお、n 領域とn4領域
との間にp 領域の幅狭領域2が生じるようにn2領域
及びn4領域のパターンが決定されている。
In the region 91, a sixth semiconductor region n3 (hereinafter simply referred to as an n3 region) of the first conductivity type (n type) is formed by impurity diffusion. A seventh semiconductor region P3 (hereinafter simply referred to as region 23) of the second conductivity type (p type) is formed in a side region of the semiconductor substrate 1 by impurity diffusion. This P3 region is formed so as to be continuous with the 21 region by diffusion of impurities from the top and bottom surfaces of the semiconductor wafer before element layering.As is clear from FIG. 9, the n-type region and the P2 region The planar shape is approximately rectangular, and the n2 area is approximately 17 out of 92 areas.
It is formed to have an area of about 3. The n region is about 178 facet seed regions out of 22 regions. Figure 8~
The bidirectional thyristor shown in FIG. 11 has a corner gate structure in which the n4 region is placed close to one corner of the 22 regions. Note that the patterns of the n2 region and the n4 region are determined so that the narrow region 2 of the p region is generated between the n region and the n4 region.

n3領域は第11図から明らかなように21領域の一部
に形成され、且つ平面的に見たときにn4g4域と重な
る部分を有するように配役されている。
As is clear from FIG. 11, the n3 region is formed in a part of the 21 region, and is arranged so as to have a portion that overlaps with the n4g4 region when viewed in plan.

真空蒸着で形成されたアルミニウム電極から成る第1の
主電極T1は第8図及び第10図から明らかなように、
P 領域及びn2領域の大部分に接するように配設され
ている。真空蒸着法等で形成されたTt(チタン)−N
iにッケル)tit!から成る第2の土竜f!T 2は
p1領域とn3領域に接するように配設されている。真
空蒸着によって形成されたアルミニウム電極から成るゲ
ート電極Gはn 領域の大部分と22頭域の一部とに接
するように配設されている。第1の主電極T1とゲート
電極Gとは5102系の絶縁#3の開口を介して各領域
に接している。なお、第1の主電極TはP 領域とn2
領域との一部を短絡させるように形成され、またゲート
電極Gはn4領域とp2領域との一部を短絡させるよう
に形成されている。
As is clear from FIGS. 8 and 10, the first main electrode T1 made of an aluminum electrode formed by vacuum evaporation is as follows.
It is arranged so as to be in contact with most of the P region and the n2 region. Tt (titanium)-N formed by vacuum evaporation method etc.
Tit! The second earth dragon consisting of f! T2 is arranged so as to be in contact with the p1 region and the n3 region. A gate electrode G made of an aluminum electrode formed by vacuum evaporation is arranged so as to be in contact with most of the n region and a part of the 22-head region. The first main electrode T1 and the gate electrode G are in contact with each region through the opening of the 5102-based insulation #3. Note that the first main electrode T is connected to the P region and n2
The gate electrode G is formed so as to partially short-circuit the n4 region and the p2 region.

双方向サイリスタは第1の主電極T1と第2の主電極T
2の正負の極性の変化及びゲート電極Gの第1の主電極
T1に対する電圧、即ち、ゲート電圧V。の正負の極性
の変化に無関係にスイッチング動作させることができる
。第1の主電極T1に対する第2の主電極T2の電位が
正であり、第1の主電極T1に対するゲート電極Gの電
位が正である第1のモードにおいては、第8図に示すp
1領域とn 領域とP 領域とn2領域とから成る第1
のサイリスク部4が導通する。
The bidirectional thyristor has a first main electrode T1 and a second main electrode T.
2 and the voltage of the gate electrode G with respect to the first main electrode T1, that is, the gate voltage V. The switching operation can be performed regardless of the change in the positive or negative polarity of . In the first mode in which the potential of the second main electrode T2 with respect to the first main electrode T1 is positive and the potential of the gate electrode G with respect to the first main electrode T1 is positive, the p
The first region consists of a 1 region, an n region, a P region, and an n2 region.
The cyrisk part 4 of is conductive.

第1の土竜iT1に対する第2の土竜fI!T 2の電
位で正であり、第1の主電極T1に対するゲート電極G
の電位が負である第2のモードにおいては、第1のモー
ドと同様に第1のサイリスク部4が導通する。
The second earth dragon fI for the first earth dragon iT1! positive at the potential of T2 and the gate electrode G relative to the first main electrode T1
In the second mode in which the potential of is negative, the first thyrisk portion 4 is conductive as in the first mode.

第1の主電極T に対する第2の土竜′!!f!T2の
電位が負であり、第1の主電極T1に対するゲート電極
Gの電位が負である第3のモードにおいては、n 領域
とP 領域とn 領域とp2領域とから成る第2のサイ
リスタ部5が導通する。
The second earth dragon' for the first main electrode T! ! f! In the third mode in which the potential of T2 is negative and the potential of the gate electrode G with respect to the first main electrode T1 is negative, the second thyristor section consisting of the n region, the P region, the n region, and the p2 region 5 is conductive.

第1の主電極T1に対する第2の主電極T2の電位が負
であり、第1の主電極T工に対するゲート電極Gの電位
が正である第4のモードにおいては、第3のモードと同
様に第2のサイリスタ部うが導通する。
In the fourth mode in which the potential of the second main electrode T2 with respect to the first main electrode T1 is negative and the potential of the gate electrode G with respect to the first main electrode T is positive, it is similar to the third mode. The second thyristor section becomes conductive.

なお、第8図から明らかなように、第1及び第2のサイ
リスタ部4、うは逆並列接続した2つのサイリスタに等
価である。第8図の右側におけるnfi¥域とp 領域
とn 領域とP1領域とn3領域とから成る部分6は、
第1及び第2のサイリスタ部4.5を導通させるために
利用される部分である。
As is clear from FIG. 8, the first and second thyristor sections 4 are equivalent to two thyristors connected in antiparallel. The part 6 on the right side of FIG. 8 consisting of the nfi\ area, the p area, the n area, the P1 area, and the n3 area is as follows:
This is a portion used to conduct the first and second thyristor portions 4.5.

ところで、双方向サイリスタにおいては高感度化、即ち
いかに小さいゲートトリガ電流10丁によって第1のサ
イリスタ部4又は第2のサイリスク部5を導通させるか
が重要な課題の1つである。
By the way, one of the important issues in bidirectional thyristors is to increase the sensitivity, that is, how to make the first thyristor part 4 or the second thyristor part 5 conductive with a small gate trigger current.

しかし、第8図〜第11図に示す従来の双方向サイリス
クでは、このゲートトリガ電流工。□があまり小さくな
らず、省感度化が難しかった。即ち、ゲートトリガ電流
工 は第1のサイリスタ部4又T は第2のサイリスタ部5の導通、つまりトリガーに寄与
する有効電流成分I  と、トリガーに寄Ta 与しない無効電流成分I。Tbから成り、上記2つの電
流成分の和として表わされる。従って、高感度化するた
めにはトリガーに寄与しない無効電流成分■  を減少
させる必要がある0例えば、第Tb 2のモード及び第3のモードにおける第1のサイリスタ
部4及び第2のサイリスタ部5の導通はn1領域とn4
領域に挾まれたp2領域の抵抗(ベース抵抗)Rとそこ
を流れる電流との積が22B 領域とn4領域とに基ず<pn 接合の拡散電位を越え
ることにより、n 領域からp2領域さらにn1領域番
こ電子が注入されることによって始まる。
However, in the conventional bidirectional circuit shown in FIGS. □ was not very small, making it difficult to reduce sensitivity. That is, the gate trigger current component T is the active current component I that contributes to the conduction of the first thyristor section 4 or the second thyristor section 5, that is, the trigger, and the reactive current component I that does not contribute to the trigger. Tb, and is expressed as the sum of the above two current components. Therefore, in order to achieve high sensitivity, it is necessary to reduce the reactive current component (2) that does not contribute to the trigger. For example, the first thyristor section 4 and the second thyristor section 5 The conduction is between n1 region and n4
The product of the resistance (base resistance) R of the p2 region sandwiched by the p2 region and the current flowing there is 22B. The region begins by injecting electrons.

従って、第8図〜第11図の構造のサイリスタでは、n
 領域の下方例のp2領域を流れるゲートトリガ電流工
 が有効電流成分工  となりゲーGT       
  GTa 上電極Gとp2領域との接¥M部分Aと、第1の主を極
T と92領域との接続部分Bとの闇の22領域から成
る矢印7で示す電流通路に流れるゲート電流工 は上記
のトリガーに寄与しない無効電T 流成分I  となる、従ってこのyi路のy!!LHI
抵抗Tb 値Rを大きくして無効電流成分I。□を減少させす ることが望ましい、しかし第8図〜第11図の構造の双
方向サイリスタではn2領域と04領域とを電気的に分
離しつつ矢印7で示すゲート電流通路の抵抗値を大きく
することは困難であった。
Therefore, in the thyristor having the structure shown in FIGS. 8 to 11, n
The gate trigger current flowing through the p2 region in the lower example of the region is the effective current component, and the game GT
GTa Gate current flowing in the current path shown by arrow 7, which consists of 22 dark areas, between the connection part A between the upper electrode G and the p2 region, and the connection part B between the first main pole T and the 92 region. becomes the reactive current T flow component I that does not contribute to the above trigger, so y! of this yi path! ! LHI
Reactive current component I by increasing resistance Tb value R. It is desirable to reduce □, but in the bidirectional thyristor with the structure shown in FIGS. 8 to 11, the resistance value of the gate current path shown by arrow 7 is increased while electrically separating the n2 region and the 04 region. That was difficult.

この問題を解決するために、第12図〜第14図に示す
ように、n 領域の中にp2領域を島状に残存させ、こ
の島状部分8にゲート電極Gを接続させな構造の双方向
サイリスタが提案されている。第13図では厚さ方向が
著しく拡大されているため、14領域が厚く示されてい
るが、n4領域の横方向長さに比較してこの厚さは著し
く小さいので、矢印9で示すゲート電流通路の一端Aか
ら他iBまでの抵抗値はn 領域の下側のp2領域の横
方向の抵抗値でほとんど決まる。n4領域の下のp 領
域の不純物濃度は22領域の表面の不純物濃度よりも著
しく低い0例えば、p2領域の表面部分の不純物濃度は
1017〜1018CIl−3オーダーであり、n 領
域の下方部分の不純物濃度は1015〜1016 cm
−3オーダーに設計される。
In order to solve this problem, as shown in FIGS. 12 to 14, the p2 region is left in the form of an island within the n region, and the gate electrode G is not connected to the island-like portion 8. Direct thyristors have been proposed. In FIG. 13, the thickness direction is significantly enlarged, so the 14 region is shown thicker, but this thickness is significantly smaller than the lateral length of the n4 region, so the gate current indicated by arrow 9 The resistance value from one end A of the path to the other end iB is almost determined by the lateral resistance value of the p2 region below the n region. The impurity concentration of the p region below the n4 region is significantly lower than the impurity concentration of the surface of the 22 region. Concentration is 1015-1016 cm
- Designed to 3 orders of magnitude.

第12図及び第13図の構造にすると、島状のP2領域
を含む矢印9で示す通路のみがゲートトリガ電流I。□
の電流通路となる。このため、ゲートトリガ電流I は
全て有効電流成分I  となり、GT        
   GTa 無効電流成分成分 はほとんどなくなる、従って、Tb 第8図〜第11図の構造よりも、ゲートトリガ電流工。
With the structure shown in FIGS. 12 and 13, only the path indicated by the arrow 9 including the island-shaped P2 region carries the gate trigger current I. □
becomes a current path. Therefore, all of the gate trigger current I becomes the effective current component I, and GT
GTa reactive current component is almost eliminated, therefore, Tb is gate-triggered current component than the structure of FIGS. 8 to 11.

□の減少が可能となる。しカル、p2領域のうちn4領
域の下方部分では不純物濃度が小さいために、この部分
の抵抗の温度依存性(温度変化による抵抗率変化)が大
きくなる。これは、半導体の不純物濃度と抵抗率との関
係を示す第15図から明らかである。結県として、ゲー
トトリガ電流I6□の温度依存性(温度変化による電流
値の変化率)が大きくなり、ターンオン特性の温度特性
が良好に得られなくなる。なお、第8図〜第11図の場
合は、無効電流成分工  を有する分だけGTb。
It is possible to reduce □. Since the impurity concentration is low in the lower portion of the n4 region in the p2 region, the temperature dependence of the resistance in this portion (resistivity change due to temperature change) becomes large. This is clear from FIG. 15, which shows the relationship between the impurity concentration and resistivity of the semiconductor. As a result, the temperature dependence (rate of change in current value due to temperature change) of the gate trigger current I6□ increases, making it difficult to obtain good temperature characteristics of turn-on characteristics. In the case of FIGS. 8 to 11, GTb is equal to the amount of reactive current component.

高感化の点では不利となるが、無効電流成分■。□、の
電流通路となるp2領域の表面近傍では抵抗の温度依存
性が小さく、第12図〜第14図に比べてゲートトリガ
電流工。1 の温度依存性は小さい また、第2の土竜[!T2が正電位になる第1及び第2
のモードにおいて、92領域のn4領域の下方部分には
22領域と01領域の間のpn接合から延びる空乏層が
広がる。この空乏層は矢印9で示すゲート電流通路を狭
め、抵抗値R1を増加するように作用する。つまりゲー
トトリガ電流I6□が主電極間電圧V、に依存する現象
が強まり、望ましくなかった。また、双方向サイリスタ
ではゲート環rjIGに第1の主電極に対して正のゲー
ト電圧V。を印加する第1及び第4のモードで、n2領
域とp2領域の間のpn接合を順バイアスすることが第
1のサイリスタ部もしくは第2のサイリスタ部をターン
オンする引き金となる。ここで、第12図〜第14図の
双方向サイリスタでは、ゲート電流通路の抵抗値RPB
とゲート電流工。の積に応じたバイアス電圧がn2 領
域と22  領域の間のpn接合の順バイアスに有効に
作用しないため、第8図〜第11図の双方向サイリスタ
にくらべて第1のモードにおけるゲートトリガ電流工。
Although it is disadvantageous in terms of high sensitivity, reactive current component ■. The temperature dependence of resistance is small near the surface of the p2 region, which becomes the current path of □, and the gate trigger current flow is smaller than that in FIGS. 12 to 14. The temperature dependence of 1 is small.Also, the second earth dragon [! The first and second T2 has a positive potential.
In this mode, a depletion layer extending from the pn junction between the 22 region and the 01 region spreads in the lower part of the n4 region of the 92 region. This depletion layer acts to narrow the gate current path shown by arrow 9 and increase the resistance value R1. In other words, the phenomenon in which the gate trigger current I6□ depends on the main electrode voltage V becomes stronger, which is not desirable. In addition, in a bidirectional thyristor, a positive gate voltage V is applied to the gate ring rjIG with respect to the first main electrode. In the first and fourth modes of applying , forward biasing the pn junction between the n2 region and p2 region triggers turning on the first thyristor section or the second thyristor section. Here, in the bidirectional thyristors shown in FIGS. 12 to 14, the resistance value RPB of the gate current path is
and gate electrician. The gate trigger current in the first mode is lower than that of the bidirectional thyristors shown in FIGS. 8 to 11 because the bias voltage corresponding to the product of Engineering.

、が増大するという欠点が生じる。, increases.

そこで、本発明は上記の問題を解決し、ゲートトリガ電
流工。□を減少させて高感度化を実現し、更にこの高感
度化に伴う他のターンオン特性の低下を防止することが
できる双方向サイリスクを提供することを目的とする。
Therefore, the present invention solves the above problems and provides a gate trigger current engineer. It is an object of the present invention to provide a bidirectional SI risk that can achieve high sensitivity by reducing □ and also prevent deterioration of other turn-on characteristics accompanying this high sensitivity.

[課題を解決するための手段] 上記目的を達成するための本発明は、実施例を示す図面
の符号を参照して説明すると、第1導電型の第1の半導
体領域n1と、前記第1の半導体領域n1の一方の側に
隣接する第2導電型の第2の半導体領域P1と、前記第
1の半導体領域n1の他方の側に隣接する第2導電型の
第3の半導体領域p2とを有する半導体基体を有し、前
記第3の半導体領域p2には前記半導体基体の表面に露
出する部分を有して前記第3の半導体領域P2 に包囲
されている第1導電型の第4及び第5の半導体領域n 
 、n4が形成されており、前記第2の、2 半導体領域p工には前記半導体基体の表面に露出する部
分を有して前記第2の半導体領域p1に包囲されている
第1導電型の第6の半導体領域n3が形成されており、
前記第6の半導体領域n3は平面的に見たときに前記第
5の半導体領域n4に重なる部分を有し、前記第3及び
第4の半導体領域P  、n4の表面は第1の主電極T
 に接しており、前記第3及び第5の半導体領域p2、
n4の表面はゲート電極Gに接しており、前記第2及び
第6の半導体領域p  、n3の表面は第2の主電極T
2に接してなる双方向サイリスタにおいて、前記第3の
半導体領域p2が前記第5の半導体領域n4に切込み状
に侵入している侵入部分11と有し、この侵入部分11
は前記半導体基体の表面に露出しており、前記ゲート電
極Gが前記侵入部分11の奥まった部分11aで前記第
3の半導体領域P2と接続されていることを特徴とする
双方向サイリスタに係わるものである。
[Means for Solving the Problems] To achieve the above object, the present invention will be described with reference to the reference numerals in the drawings showing the embodiments. a second semiconductor region P1 of the second conductivity type adjacent to one side of the semiconductor region n1; and a third semiconductor region P2 of the second conductivity type adjacent to the other side of the first semiconductor region n1. The third semiconductor region p2 has a fourth semiconductor substrate of the first conductivity type surrounded by the third semiconductor region P2 and has a portion exposed on the surface of the semiconductor substrate. fifth semiconductor region n
, n4 are formed, and the second semiconductor region p has a portion exposed to the surface of the semiconductor substrate and is of a first conductivity type surrounded by the second semiconductor region p1. A sixth semiconductor region n3 is formed,
The sixth semiconductor region n3 has a portion overlapping the fifth semiconductor region n4 when viewed in plan, and the surfaces of the third and fourth semiconductor regions P and n4 are connected to the first main electrode T.
the third and fifth semiconductor regions p2,
The surface of n4 is in contact with the gate electrode G, the second and sixth semiconductor regions p, and the surface of n3 is in contact with the second main electrode T.
2, the third semiconductor region p2 has an intrusion portion 11 intruding into the fifth semiconductor region n4 in the form of a notch, and the intrusion portion 11
relates to a bidirectional thyristor, characterized in that the gate electrode G is exposed on the surface of the semiconductor substrate, and the gate electrode G is connected to the third semiconductor region P2 at a recessed portion 11a of the intrusion portion 11. It is.

[作 用] 上記発明における第3の半導体領域p2の第5の半導体
領域n4への侵入部分11はゲート電流■。1のうち無
効電流成分工。□、の通路として作用する。この侵入部
分11は複数の半導体領域の相互間を分離するための領
域ではないので、大きな設計の自由度を有する。従って
、侵入部分11の長さ及び幅を最適抵抗値が得られるよ
うに最定することができる。即ち、無効電流成分I。1
.の電流通路の抵抗値を侵入部分11の抵抗によって増
大させることで無効電流成分■。1.が減少し、結果と
してゲートトリガ電流工。工が減少し、高感度化を高水
準に達成することができる。また、無効電流成分工  
の通路として作用する侵入部分11Tb は第3の半導体領域p2の不純物濃度の寄い表面領域を
含むので無効電流成分工。1bの温度特性は良好である
。従って、ゲートトリガ電流工。1の温度特性も比較的
良好になり、更に主電極間電圧のゲートトリガ電流工。
[Function] The intrusion portion 11 of the third semiconductor region p2 into the fifth semiconductor region n4 in the above invention has a gate current ■. 1. Reactive current component work. □, acts as a passageway. Since this intrusion portion 11 is not a region for isolating a plurality of semiconductor regions from each other, it has a large degree of freedom in design. Therefore, the length and width of the intrusion portion 11 can be optimized to obtain the optimum resistance value. That is, reactive current component I. 1
.. By increasing the resistance value of the current path by the resistance of the intrusion part 11, the reactive current component ■. 1. As a result, the gate trigger current is reduced. It is possible to achieve a high level of sensitivity. In addition, reactive current component
Since the intrusion portion 11Tb, which acts as a path, includes a surface region with a low impurity concentration of the third semiconductor region p2, a reactive current component is generated. The temperature characteristics of 1b are good. Therefore, the gate trigger current engineer. The temperature characteristics of 1 are also relatively good, and the gate trigger current control of the voltage between the main electrodes is also relatively good.

□への影響も少なくなる。The impact on □ will also be reduced.

[実施例] 次に、第1図〜第5図を参照して本発明の実施例に係わ
る双方向サイリスタ(トライアック)を説明する。但し
、第1図〜第5図において、第8図〜第11図と実質的
に同一の部分には同一の符号を付してその説明を省略す
る。
[Embodiment] Next, a bidirectional thyristor (TRIAC) according to an embodiment of the present invention will be described with reference to FIGS. 1 to 5. However, in FIGS. 1 to 5, parts that are substantially the same as those in FIGS. 8 to 11 are designated by the same reference numerals, and their explanations will be omitted.

第1図〜第5図に示す双方向サイリスタは、第8図〜第
11図の双方向サイリスタのn4領域のパターン及びゲ
ート電極Gの配置を変えた他は第8図〜第11図と実質
的に同一に構成されている。
The bidirectional thyristors shown in FIGS. 1 to 5 are substantially the same as those shown in FIGS. 8 to 11, except that the pattern of the n4 region and the arrangement of the gate electrode G are changed. are configured identically.

本実施例のn4領域(第5の半導体領域)は、第1図か
ら明らかなように切込み部を有し、ここに22領域(第
3の半導体領域)の侵入部分11が配置されている。こ
の侵入部分11は、n4領域を不純物拡散で形成する時
にマスクした部分であり、第4図から明らかなようにn
4領域を上から下に分断するように形成されている。n
21域とn4領域との闇の幅狭領域2をゲート電流の無
効電流成分■。1.の電流通路として利用し、更に侵入
部分11もその一部として利用するなめに、侵入部分1
1の入口は幅狭領域2の右端近傍に配置されている。即
ち、n4領域の右側に片寄って侵入部分11が配置され
ている。侵入部分11の長さし はこれが延びる方向の
n 領域の幅W□の約577となっている。また、侵入
部分11の幅即ち切込み幅W2はn4領域の第1図左右
方向の幅の約177になっている一P2領域から成る侵
入部分11の美即ち先端部11aは絶縁膜3によって被
覆されていないが、侵入部分11のこれ以外の部分は第
3国に示すように絶縁rIA3で被覆されている。ゲー
ト電極Gはn4領域のほぼ全部と侵入部分11とを覆う
ように配設されているが、侵入部分11においては先端
部Llaのみに接している。従って、侵入部分11のゲ
ート電極Gに接触する先端部11aから侵入部分11の
入口までの92領域を抵抗値の比較的大きい無効電流成
分工GTb通路として使用することができる。 本実施
例の双方向サイリスタは以下のような効泉を有する。
As is clear from FIG. 1, the n4 region (fifth semiconductor region) of this embodiment has a notch, in which the intrusion portion 11 of the 22 region (third semiconductor region) is arranged. This intrusion portion 11 is a portion masked when forming the n4 region by impurity diffusion, and as is clear from FIG.
It is formed to divide four areas from top to bottom. n
The dark narrow region 2 between the 21 region and the n4 region is the reactive current component of the gate current ■. 1. In order to use the intrusion part 1 as a current path and also use the intrusion part 11 as a part of it, the intrusion part 1
The entrance 1 is located near the right end of the narrow region 2. That is, the intrusion portion 11 is disposed off to the right side of the n4 region. The length of the intrusion portion 11 is approximately 577 times the width W of the n region in the direction in which it extends. Further, the width of the intrusion portion 11, that is, the cut width W2 is approximately 177 times the width of the n4 region in the left-right direction in FIG. However, other parts of the intrusion portion 11 are covered with insulating rIA3 as shown in the third country. The gate electrode G is arranged so as to cover almost the entire n4 region and the intrusion portion 11, but in the intrusion portion 11, it contacts only the tip Lla. Therefore, 92 regions from the tip portion 11a of the penetration portion 11 that contacts the gate electrode G to the entrance of the penetration portion 11 can be used as a reactive current component path GTb having a relatively large resistance value. The bidirectional thyristor of this embodiment has the following effects.

(1) 無効電流成分I  を制限できるためTb ゲートトリガ電流工。1が減少し、高感度化が実現でき
る。即ち、ゲート電極Gはp2領域に対して侵入部分1
1の先端部11aのみで接触している。
(1) Since the reactive current component I can be limited, Tb is the gate trigger current factor. 1 is reduced, and high sensitivity can be achieved. That is, the gate electrode G has a penetrating portion 1 with respect to the p2 region.
Only the tip portion 11a of 1 is in contact with the other.

従って、侵入部分11は無効電流成分■GTbの通路の
一部となりとなり、この部分の抵抗によって無効電流成
分■  を制限することができる。要すTb るに、無効電流成分I。16通路の−mAは侵入部分1
1の先端部11aであり、他4Bは第1の主電極T と
92領域との接触部がn4領域に最も近接している部分
であり、AとBとの間に幅狭領域2と侵入部分11とが
介在するので、第8図〜第11図に示すものよりも侵入
部分11の分だけ抵抗値が大きくなり、無効電流成分I
  が減少Tb しゲートトリガ電流I。□が小さくなる。第1図〜第5
図の構造にすれば、ゲートトリガ電流の値即ち悪魔を第
8区〜第11図の双方向サイリスタよりも向上すること
ができる。
Therefore, the intrusion portion 11 becomes a part of the path of the reactive current component (GTb), and the resistance of this portion can limit the reactive current component (2). Required Tb Basically, reactive current component I. -mA of 16 passages is intrusion part 1
1, and the other 4B is the part where the contact part between the first main electrode T and the region 92 is closest to the n4 region, and the narrow region 2 and the intrusion between A and B are Since the intervening portion 11 is present, the resistance value becomes larger by the intrusion portion 11 than that shown in FIGS. 8 to 11, and the reactive current component I
decreases Tb and gate trigger current I. □ becomes smaller. Figures 1 to 5
With the structure shown in the figure, the value of the gate trigger current, that is, the value of the gate trigger current, can be improved compared to the bidirectional thyristors shown in sections 8 to 11.

(2) ゲートトリガ電流■。1の温度特性が良好であ
る。即ち、ゲートトリガ電流工。1のうち無効電流成分
I6□、の電流経路が抵抗値の温度による変効率が比較
的小さい92領域の表面側の不純物濃度の高い領域に形
成されるため、無効電流成分工。Tbの温度依存性は小
さい、従って無効電流成分I  と有効電流成分工  
とを加えたゲーGTb               
   GTaトトリガ電流■6□の温度依存性は第8〜
第11図の双方向サイリスタとほぼ同等に小さくでき、
高感度化に伴うゲートトリガ電流工。□の温度特性の大
きな低下を防止できる。
(2) Gate trigger current■. 1 has good temperature characteristics. i.e. gate trigger current engineer. 1, the current path of the reactive current component I6□ is formed in a region with a high impurity concentration on the surface side of the region 92, where the change rate of resistance value due to temperature is relatively small. The temperature dependence of Tb is small, so the reactive current component I and the active current component
Game GTb with
The temperature dependence of GTa trigger current ■6□ is 8th~
It can be made almost as small as the bidirectional thyristor shown in Figure 11,
Gate trigger current engineering due to increased sensitivity. A large decrease in the temperature characteristics of □ can be prevented.

(3) 侵入部分11は主電極間の電圧に基づく空乏層
が形成されない領域樟形成されている。
(3) The intrusion portion 11 is formed as a region in which a depletion layer is not formed due to the voltage between the main electrodes.

従って、ゲートトリガ電流工。□の主y 7rWl電圧
に対する依存性が小さい。
Therefore, the gate trigger current engineer. The dependence of □ on the main y7rWl voltage is small.

(4) 第1のモードでのゲートトリガ電流I釘の増大
が防止できる。
(4) Increase in gate trigger current I in the first mode can be prevented.

[変形例コ 本発明は上述の実施例に限定されるものでなく、例えば
次の変形が可能なものである。
[Modifications] The present invention is not limited to the above-described embodiments, and for example, the following modifications are possible.

(1) 第6図に示すように幅狭の侵入部分11に屈曲
部分を設けてもよい、このようにすることで、侵入部分
11の長さが増大し、結果として電流経路の抵抗が増大
できる。
(1) As shown in FIG. 6, a bent portion may be provided in the narrow intrusion portion 11. By doing so, the length of the intrusion portion 11 increases, and as a result, the resistance of the current path increases. can.

(2) 第7図に示すようにゲート電極Gに切込み部1
3を設け、ゲート電極Gをn4領域にほぼ対応した平面
パターンとし、侵入部分11においてはこの先端部11
a上のみにゲート電極Gが位置するようにしてもよい。
(2) As shown in Figure 7, there is a notch 1 in the gate electrode G.
3 is provided, and the gate electrode G is formed into a planar pattern that almost corresponds to the n4 region.
The gate electrode G may be located only on the area a.

(3)  P2領域及びp3領域の表面の一部に、高濃
度のp型頭域から成るガードリング領域及びEQR(等
電位リング領域)を形成してもよい。
(3) A guard ring region and an EQR (equipotential ring region) consisting of a highly concentrated p-type head region may be formed on part of the surfaces of the P2 region and the p3 region.

(4) ゲート型iGは侵入部分11の近傍で接続され
るのが望ましいが、侵入部分11の中はどで接続されて
いても侵入部分1工の接続部分から入口部分までの抵抗
分で無効電流成分I  をTb 制限することができる。
(4) It is desirable that the gate type iG be connected near the intrusion part 11, but no matter where it is connected inside the intrusion part 11, it will be ineffective due to the resistance from the connection part of the intrusion part 1 to the entrance part. The current component I can be limited by Tb.

< 5 )  n 4領域(ゲート領域)が22領域の
角近傍以外に形成されたタイプの双方向サイリスタ(セ
ンターゲート型双方向サイリスタやサイドゲート型双方
向サイリスタ)にも有効である。
<5) It is also effective for bidirectional thyristors of the type in which the n4 regions (gate regions) are formed other than near the corners of the 22 regions (center gate bidirectional thyristors and side gate bidirectional thyristors).

(6)  n 2領域のT1電極側の形状を工夫してG
“モードのI。、を改善した双方向サイリスタに組合せ
ても有効である。
(6) G by devising the shape of the T1 electrode side of the n2 region.
It is also effective to combine "Mode I." with an improved bidirectional thyristor.

[発明の効果] 上述のように本発明によれば、高悪度化が達成され、か
つゲートトリガ電流の温度特性や主ti間電圧依存性に
も優れた双方向サイリスタを提供することができる。
[Effects of the Invention] As described above, according to the present invention, it is possible to provide a bidirectional thyristor that achieves high deterioration and also has excellent temperature characteristics of gate trigger current and voltage dependence between main Ti. .

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は本発明の一実施例に係わる双方向サイリスタの
半導体基体の表面における各領域の配置を示す平面図、 第2図は第1図の半導体基体に絶縁膜及び電極を設けた
状態を示す平面図、 第3図は第1図、第2図、第5図の■−■裸に相当する
部分の断面図、 第4図は第2図のIV −IV IIの一部断面図、第
5図は第3図のV−V線部分の断面図、第6図は変形例
を第2図に対応して示す平面図、第7図は別の変形例の
ゲート電極及びこの近傍を拡大して示す平面図、 第8図は従来の双方向サイリスタの第9図、第10図、
第11図の■−■線に対応する部分の断面図、 第9図は第8図の双方向サイリスタの半導体基体の表面
を示す平面図、 T%10区は第9図の半導体基体に絶縁膜と電極を設け
た状態を示す平面図、 第11図は第8図のXI−XI線断面図、第12図は別
の従来例の双方向サイリスタを示す平面図、 ’741311141!12図のXII[−XI[!!
断面図、第14図は第13図のXrV−XrV線断面図
第15図は半導体の不純物濃度と抵抗率と濃度との関係
をしめす図である。 2・・・播狭頒域、11・・・侵入部分、11a・・・
先端部、nl・・・第1の半導体領域、n2・・・第4
の半導体領域、n3・・・第6の半導体領域、n4・・
・第5の半導体領域、pl・・・第2の半導体領域、P
2・・・第3の半導体領域、T1・・・第1の主電極、
T2・・・第2の主電極、G・・・ゲート電極。
FIG. 1 is a plan view showing the arrangement of each region on the surface of a semiconductor substrate of a bidirectional thyristor according to an embodiment of the present invention, and FIG. 2 shows a state in which an insulating film and an electrode are provided on the semiconductor substrate of FIG. 1. 3 is a sectional view of a portion corresponding to ■-■ bare in FIGS. 1, 2, and 5; FIG. 4 is a partial sectional view of IV-IV II in FIG. 2; 5 is a sectional view taken along the line V-V in FIG. 3, FIG. 6 is a plan view showing a modified example corresponding to FIG. 2, and FIG. 7 is a diagram showing the gate electrode and its vicinity in another modified example. FIG. 8 is an enlarged plan view of a conventional bidirectional thyristor, FIGS. 9 and 10,
A cross-sectional view of a portion corresponding to the line ■-■ in FIG. 11. FIG. 9 is a plan view showing the surface of the semiconductor substrate of the bidirectional thyristor in FIG. 8. The T%10 section is insulated on the semiconductor substrate in FIG. 11 is a sectional view taken along the line XI-XI in FIG. 8; FIG. 12 is a plan view showing another conventional bidirectional thyristor; '741311141! XII[-XI[! !
FIG. 14 is a sectional view taken along the line XrV-XrV in FIG. 13, and FIG. 15 is a diagram showing the relationship between impurity concentration, resistivity, and concentration of a semiconductor. 2... Narrow distribution area, 11... Intrusion part, 11a...
Tip, nl...first semiconductor region, n2...fourth
semiconductor region, n3...sixth semiconductor region, n4...
-Fifth semiconductor region, pl...second semiconductor region, P
2... Third semiconductor region, T1... First main electrode,
T2...second main electrode, G...gate electrode.

Claims (1)

【特許請求の範囲】[Claims] 第1導電型の第1の半導体領域(n_1)と、前記第1
の半導体領域(n_1)に隣接する第2導電型の第2の
半導体領域(p_1)と、前記第1の半導体領域(n_
1)の他方の側に隣接する第2導電型の第3の半導体領
域(p_2)とを有する半導体基体を有し、前記第3の
半導体領域(p_2)には前記半導体基体の表面に露出
する部分を有して前記第3の半導体領域(p_2)に包
囲されている第1導電型の第4及び第5の半導体領域(
n_2)(n_4)が形成されており、前記第2の半導
体領域(p_1)には前記半導体基体の表面に露出する
部分を有して前記第2の半導体領域(p_1)に包囲さ
れている第1導電型の第6の半導体領域(n_3)が形
成されており、前記第6の半導体領域(n_3)は平面
的に見たときに前記第5の半導体領域(n_4)に重な
る部分を有し、前記第3及び第4の半導体領域(p_2
)(n_2)の表面は第1の主電極(T_1)に接して
おり、前記第3及び第5の半導体領域(p_2)(n_
4)の表面はゲート電極(G)に接しており、前記第2
及び第6の半導体領域(p_1)(n_3)の表面は第
2の主電極(T_2)に接してなる双方向サイリスタに
おいて、前記第3の半導体領域(p_2)が前記第5の
半導体領域(n_4)に切込み状に侵入している部分(
11)を有し、この侵入部分(11)は前記半導体基体
の表面に露出しており、前記ゲート電極(G)が前記侵
入部分(11)の奥まった部分(11a)で前記第3の
半導体領域(p_2)と接続されていることを特徴とす
る双方向サイリスタ。
a first semiconductor region (n_1) of a first conductivity type;
a second semiconductor region (p_1) of the second conductivity type adjacent to the semiconductor region (n_1) of the first semiconductor region (n_1);
1) has a semiconductor substrate having a third semiconductor region (p_2) of a second conductivity type adjacent to the other side of the semiconductor substrate, and the third semiconductor region (p_2) is exposed on the surface of the semiconductor substrate. fourth and fifth semiconductor regions (p_2) of the first conductivity type surrounded by the third semiconductor region (p_2);
n_2) (n_4) is formed, and the second semiconductor region (p_1) has a portion exposed to the surface of the semiconductor substrate and is surrounded by the second semiconductor region (p_1). A sixth semiconductor region (n_3) of one conductivity type is formed, and the sixth semiconductor region (n_3) has a portion overlapping with the fifth semiconductor region (n_4) when viewed in plan. , the third and fourth semiconductor regions (p_2
)(n_2) is in contact with the first main electrode (T_1), and the surface of the third and fifth semiconductor regions (p_2)(n_
4) is in contact with the gate electrode (G), and the surface of the second
In a bidirectional thyristor in which the surfaces of the sixth semiconductor regions (p_1) (n_3) are in contact with the second main electrode (T_2), the third semiconductor region (p_2) is in contact with the fifth semiconductor region (n_4). ) into the notch-like part (
11), the intrusion part (11) is exposed on the surface of the semiconductor substrate, and the gate electrode (G) is connected to the third semiconductor at a deep part (11a) of the intrusion part (11). A bidirectional thyristor characterized in that it is connected to a region (p_2).
JP63164357A 1988-07-01 1988-07-01 Bidirectional thyristor Expired - Fee Related JPH0671080B2 (en)

Priority Applications (2)

Application Number Priority Date Filing Date Title
JP63164357A JPH0671080B2 (en) 1988-07-01 1988-07-01 Bidirectional thyristor
US07/370,385 US4994885A (en) 1988-07-01 1989-06-22 Bidirectional triode thyristor

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP63164357A JPH0671080B2 (en) 1988-07-01 1988-07-01 Bidirectional thyristor

Publications (2)

Publication Number Publication Date
JPH0214574A true JPH0214574A (en) 1990-01-18
JPH0671080B2 JPH0671080B2 (en) 1994-09-07

Family

ID=15791613

Family Applications (1)

Application Number Title Priority Date Filing Date
JP63164357A Expired - Fee Related JPH0671080B2 (en) 1988-07-01 1988-07-01 Bidirectional thyristor

Country Status (1)

Country Link
JP (1) JPH0671080B2 (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN110600545A (en) * 2019-10-09 2019-12-20 上海韦尔半导体股份有限公司 Bidirectional thyristor and electronic product

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS60247970A (en) * 1984-05-23 1985-12-07 Toshiba Corp Bi-directional semiconductor device
JPS61199664A (en) * 1985-03-01 1986-09-04 Toshiba Corp Semiconductor device

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS60247970A (en) * 1984-05-23 1985-12-07 Toshiba Corp Bi-directional semiconductor device
JPS61199664A (en) * 1985-03-01 1986-09-04 Toshiba Corp Semiconductor device

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN110600545A (en) * 2019-10-09 2019-12-20 上海韦尔半导体股份有限公司 Bidirectional thyristor and electronic product
CN110600545B (en) * 2019-10-09 2023-08-11 上海韦尔半导体股份有限公司 Bidirectional thyristor and electronic product

Also Published As

Publication number Publication date
JPH0671080B2 (en) 1994-09-07

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