JPH01307264A - Pnpn surge-preventing device - Google Patents

Pnpn surge-preventing device

Info

Publication number
JPH01307264A
JPH01307264A JP13731088A JP13731088A JPH01307264A JP H01307264 A JPH01307264 A JP H01307264A JP 13731088 A JP13731088 A JP 13731088A JP 13731088 A JP13731088 A JP 13731088A JP H01307264 A JPH01307264 A JP H01307264A
Authority
JP
Japan
Prior art keywords
semiconductor substrate
specified
surge
range
preventing
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP13731088A
Other languages
Japanese (ja)
Other versions
JP2668238B2 (en
Inventor
Yoshiaki Kamijo
上條 芳昭
Hidetaka Sato
秀隆 佐藤
Nobuyuki Miyadera
宮寺 伸行
Hiroyuki Ono
博之 大野
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Shindengen Electric Manufacturing Co Ltd
Nippon Telegraph and Telephone Corp
Original Assignee
Shindengen Electric Manufacturing Co Ltd
Nippon Telegraph and Telephone Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Shindengen Electric Manufacturing Co Ltd, Nippon Telegraph and Telephone Corp filed Critical Shindengen Electric Manufacturing Co Ltd
Priority to JP63137310A priority Critical patent/JP2668238B2/en
Publication of JPH01307264A publication Critical patent/JPH01307264A/en
Application granted granted Critical
Publication of JP2668238B2 publication Critical patent/JP2668238B2/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/86Types of semiconductor device ; Multistep manufacturing processes therefor controllable only by variation of the electric current supplied, or only the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched
    • H01L29/861Diodes
    • H01L29/87Thyristor diodes, e.g. Shockley diodes, break-over diodes

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Thyristors (AREA)
  • Emergency Protection Circuit Devices (AREA)

Abstract

PURPOSE:To provide an antisurging device improved characteristics for preventing lighting surge, by specifying resistivity of a P-type semiconductor substrate, diffused surface concentration of base regions, diffused depth and overlapping width between emitter regions. CONSTITUTION:A breaker voltage VBO is generally dependent on a thickness of a semiconductor substrate 1, resistivity rho thereof, a diffusion surface concentration NSB of base regions and diffusion depth XJB. In order to satisfy all the characteristics required for a lightening surge preventing device, device parameters must be designed properly. Thus, resistivity of the P-type semiconductor substrate 1 is specified in a range of 1.0-3.5OMEGAcm, the diffused surface concentration NSB of the base regions 2, 2' is specified in a range of 3X10<17>-7X10<18>cm<-3>, the diffusion depth XjB is specified in a range of 20-50mum and the mutual overlapping width (d) between the emitter regions 3 and 3' is specified in a range of 200-800mum. In this manner, it is possible to obtain a highly reliable surge-preventing device having all the characteristics required for preventing lightening surge.

Description

【発明の詳細な説明】 (発明の属する技術分野) 本発明は雷サージ防護にすぐれた特性をもつPNPPN
サージ防護デバイスに関するものである。
DETAILED DESCRIPTION OF THE INVENTION (Technical field to which the invention pertains) The present invention relates to PNPPN having excellent characteristics in lightning surge protection.
It relates to surge protection devices.

(従来技術) 2端子双方向サイリスタは良く知られるように、従来か
ら交流調光装置や、瞬時点灯蛍光灯スタータ、更にはナ
トリウムランプの起動素子などのパワー用、或いはトリ
ガ素子として広く使用されている。また近年短時間過電
流耐量が大きいという特性の特徴と、小型安価であり、
しかも2端子であって使用が簡単であるなどの理由から
雷サージ防護用の素子としても幅広く使用される傾向に
ある。特にその性能は各種のサージ吸収装置のなかでも
電話交換機や端末電話機の雷サージ防護に最も適するも
のとして注目され始めている。ところで、例えば電話機
のように多数台が分散配置されて保守に困難を伴うもの
にあっては、故障の少ない信頼性に優れたものの要求と
同時に、確実な雷防護を可能として、電話機回路の正常
な動作を阻害させないための酷しい動作特性が要求され
る。
(Prior Art) As is well known, two-terminal bidirectional thyristors have been widely used as power or trigger elements for AC dimmers, instantaneous fluorescent lamp starters, and starting elements for sodium lamps. There is. In addition, in recent years, it has been characterized by high short-term overcurrent capability, and is small and inexpensive.
Moreover, since it has two terminals and is easy to use, it tends to be widely used as a lightning surge protection element. In particular, its performance has begun to draw attention as it is the most suitable of all surge absorption devices for lightning surge protection for telephone exchanges and terminal telephones. By the way, for example, in the case of items such as telephones, which are difficult to maintain because they are distributed in large numbers, there is a need for products that are highly reliable and have few breakdowns, and at the same time, it is necessary to ensure that the telephone circuits are in good working condition by ensuring reliable lightning protection. Severe operating characteristics are required in order not to impede normal operation.

例えば、 (1)雷サージに対して安定なブレークオーバー電圧■
8゜をもつこと。
For example, (1) Breakover voltage stable against lightning surge■
Must have an angle of 8°.

(2)大きな雷サージ電流耐量■、をもつこと。(2) Must have a large lightning surge current withstand capacity.

(3)大きな保持電流■、をもつこと。(3) Have a large holding current.

(4)静電容量が極力小さいこと。(4) Capacitance must be as small as possible.

などの特性が要求される。しかし現在のPNPNサージ
防護素子の構造パラメータと前記の特性とは互いに相反
する関係にある。従って、一方の特性を満足させると他
方の特性を悪化させるため、従来のPNPNサージ防護
デバイスではすべての特性を満足させるものを得るのは
非常に困難であった。すでにこの半導体装置の基本構造
は特公昭41−15902号、特公昭42−14254
号によって公知であるが、構造パラメータと特性の定量
的な関係が明確でなかった。
The following characteristics are required. However, the structural parameters and the above-mentioned characteristics of current PNPN surge protection devices are in a contradictory relationship with each other. Therefore, satisfying one characteristic deteriorates the other characteristic, so it has been very difficult to obtain a conventional PNPN surge protection device that satisfies all the characteristics. The basic structure of this semiconductor device has already been published in Japanese Patent Publication Nos. 41-15902 and 14254-1973.
However, the quantitative relationship between structural parameters and properties was not clear.

(発明の目的) 本発明は前記の如き電話機の雷サージ防護用としての酷
しい要求を満足させうるPNPN雷サージ防護素子の堤
供を目的としてなされたものである。以下に図面を用い
てその詳細を説明する。
(Object of the Invention) The present invention has been made for the purpose of providing a PNPN lightning surge protection element that can satisfy the severe requirements for lightning surge protection for telephones as described above. The details will be explained below using the drawings.

(発明の構成) (発明の特徴と従来の技術の差) PNPNサージ防護デバイスの断面構造図を第1図に示
す。P型半導体基板1、拡散で形成したN型ベース領域
2.2°、P型エミッタ領域3.3′、オーミック領域
5.5°および表面不活性膜6,6゛と電極7.7′な
どからPNPN構造が構成される。
(Structure of the Invention) (Characteristics of the Invention and Differences between the Prior Art) A cross-sectional structural diagram of a PNPN surge protection device is shown in FIG. P-type semiconductor substrate 1, N-type base region 2.2° formed by diffusion, P-type emitter region 3.3', ohmic region 5.5°, surface inactive film 6, 6', electrode 7.7', etc. A PNPN structure is constructed from .

第2図は第1図の等価モデル図を示す。2箇のサイリス
ク8.9が逆並列に配置され、かつそれぞれのゲートが
横方向抵抗R1,R2,R3によりショートゲートされ
た双方向装置である。次に動作を説明する。
FIG. 2 shows an equivalent model diagram of FIG. 1. It is a bidirectional device in which two cyrisks 8.9 are arranged in antiparallel, and each gate is short gated by lateral resistors R1, R2, and R3. Next, the operation will be explained.

端子7,7”間に端子7側が正極性となる電圧を、印加
すると接合JRは逆方向バイアスとなり、接合Jsは順
方向バイアスとなる。一方接合J1は抵抗R1の電圧降
下で順バイアスになる。この状態において印加電圧が低
い時には接合J2の逆方向特性により制限される電流が
電極7から流れ出し抵抗R,,R,,R,などによって
サイリスタ9側からサイリスク8側に分流し、分流電流
i4と共に電極7゛に流れこむ、印加電圧がブレークオ
ーバ電圧V、。を越えると逆方向電流が急激に増加し、
これに伴ってエミッタ領域3直下の抵抗R1と分流電流
iIによる電圧降下(i+XR+)が生じて接合J、が
順方向バイアスとなる。そしてこの電圧降下が接合J+
の拡散電位を越えるとエミッタ領域3からベース領域2
に正孔が注入され始める。
When a voltage is applied between terminals 7 and 7'' so that the terminal 7 side is positive, junction JR becomes reverse biased and junction Js becomes forward biased.On the other hand, junction J1 becomes forward biased due to the voltage drop across resistor R1. In this state, when the applied voltage is low, a current limited by the reverse characteristic of the junction J2 flows from the electrode 7 and is shunted from the thyristor 9 side to the thyristor 8 side by the resistors R, , R, , R, etc., and the shunt current i4 When the applied voltage that flows into the electrode 7 at the same time exceeds the breakover voltage V, the reverse current increases rapidly,
Along with this, a voltage drop (i+XR+) occurs due to the resistor R1 directly under the emitter region 3 and the shunt current iI, and the junction J becomes forward biased. And this voltage drop is the junction J+
When the diffusion potential of
Holes begin to be injected into.

一方策2図のサイリスタ8において3.2.1から形成
されるPNP )ランリスクと、2.1.2’から形成
されるNPN)ランリスクの電流増幅率α、。
On the other hand, in the thyristor 8 of Fig. 2, the current amplification factor α of the PNP) run risk formed from 3.2.1 and the NPN) run risk formed from 2.1.2'.

α2は電流と共に増加する。α1+αt==1に達する
とサイリスタ8がオン状態となる。また電極7への印加
電圧の極性が反対になると同様原理にてサイリスタ9が
オン状態となる。第3図は上記の特性である。I3はオ
ン状態に移行する電流即ち遷移点電流、V!はオン電流
tcにおけるオン電圧である。
α2 increases with current. When α1+αt==1, the thyristor 8 is turned on. Further, when the polarity of the voltage applied to the electrode 7 is reversed, the thyristor 9 is turned on based on the same principle. FIG. 3 shows the above characteristics. I3 is the current transitioning to the on state, that is, the transition point current, V! is the on-voltage at the on-current tc.

次にデバイスパラメータと緒特性との関係を定量的に述
べる。
Next, we quantitatively describe the relationship between device parameters and characteristics.

■ ブレークオーバー電圧VIOは一般に半導体基板1
の厚さ、その比抵抗ρ、ベース領域の拡散表面濃度N5
ll、拡散深さX口に依存する。また各領域の不純物濃
度およびその縦方向の寸法関係に依存する電流増幅率α
、にょって変化する。
■ Breakover voltage VIO is generally applied to semiconductor substrate 1.
, its specific resistance ρ, and the diffusion surface concentration N5 in the base region.
ll, depends on diffusion depth x mouth. In addition, the current amplification factor α depends on the impurity concentration of each region and its vertical dimension relationship.
, it changes depending on the situation.

第4図はベース領域2,2゛のN8.を一定として、X
口をパラメータとして実験によって求めた■、。とρの
関係を示したものである。vloはρの増加とともに高
(なる。またXj、が大となることによっても高くなる
。第5図にρを一定とし、ベース領域2.2”のX口を
パラメータとして求めたV、。とNSBの関係図を示す
。曲線A(実線)からNs、が高゛(なるに伴い■廊。
FIG. 4 shows N8 in the base area 2,2''. Assuming that X is constant,
■, determined through experiments using the mouth as a parameter. This shows the relationship between and ρ. vlo becomes higher as ρ increases. It also increases as Xj becomes larger. Figure 5 shows V, which is determined by keeping ρ constant and using the X opening of the base area 2.2" as a parameter. The relationship diagram of NSB is shown. As Ns becomes higher from curve A (solid line),

が低くなることがわかる。can be seen to be lower.

■ 保持電流■、はエミッタ領域3の直下のベース領域
2の伝導度σに依存する。σは■ベース領域2.2′を
形成するN31+  XJI、■エミッタ     。
(2) The holding current (2) depends on the conductivity σ of the base region 2 immediately below the emitter region 3. σ is ■N31+XJI forming base region 2.2', ■emitter.

拡散深さXJtとXj、との比xjE/ X J1%■
電流増幅率αhα2に依存する。第5図の曲線B(点線
)はXJIをパラメータとしてNsBと1゜を示すもの
である。但し、X j t/ X口は一定としている。
Ratio between diffusion depth XJt and Xj, xjE/XJ1%■
It depends on the current amplification factor αhα2. Curve B (dotted line) in FIG. 5 shows NsB and 1° using XJI as a parameter. However, X j t/X mouth is kept constant.

’NSBが高くなるにともない、111が増加すること
がわかる。
It can be seen that as NSB becomes higher, 111 increases.

■ 第6図にエミッタ領域3,3゛の相互位置に重ね幅
dを有するデバイスの断面構造を示す。
(2) FIG. 6 shows a cross-sectional structure of a device having an overlapping width d at the mutual positions of the emitter regions 3, 3'.

第7図にdとIC+ ターンオン時間tonの関係を示
す。但しρ、N、□ Xj、を一定とした。
FIG. 7 shows the relationship between d and IC+ turn-on time ton. However, ρ, N, and □Xj were kept constant.

dが200〜700−が最適でありそれ以降エミッタ実
効面積の減少の影響が加わり低下する。このように、d
の選定により、適切なl(、、tonを得ることができ
る。
The optimum value is d between 200 and 700, and thereafter it decreases due to the influence of the reduction in the effective area of the emitter. In this way, d
By selecting , an appropriate l(,,ton) can be obtained.

■ 静電容量C4は、■ベース領域2,2”の面積、■
は半導体基板1の比抵抗ρ、■ベース領域2゜2゛のN
5Ilの関係を示す。C4はN5Ilが大となるに伴い
増加し、ρが大となると減少する。
■ Capacitance C4 is: ■ Area of base region 2,2", ■
is the specific resistance ρ of the semiconductor substrate 1, ■N of the base region 2゜2゛
5Il relationship is shown. C4 increases as N5Il increases, and decreases as ρ increases.

以上デバイスパラメータと特性の関係について述べた。The relationship between device parameters and characteristics has been described above.

従って雷サージ防護デバイスとして要求される各特性を
満足させるためには、上記列挙事項を考慮してデバイス
パラメータを設計することが必要である。従って、V2
Oを100〜220v、雷サージ電流耐量Ic>150
^、保持電流1.≧75mA、静電容量(0バイアス)
Cj≦400PFの特性を満足させるデバイスパラメー
タは第4図、第5図、第7図、第8図から以下の通りと
なる。
Therefore, in order to satisfy each characteristic required of a lightning surge protection device, it is necessary to design device parameters in consideration of the above-mentioned items. Therefore, V2
O 100-220V, lightning surge current withstand capacity Ic>150
^, holding current 1. ≧75mA, capacitance (0 bias)
The device parameters that satisfy the characteristic of Cj≦400PF are as follows from FIGS. 4, 5, 7, and 8.

■ P型半導体基板1の比抵抗の範囲を1.0〜3.5
Ωcm。
■ Set the specific resistance range of P-type semiconductor substrate 1 to 1.0 to 3.5.
Ωcm.

■ ベース領域2,2゛の拡散表面濃度N31を3×1
0” 〜7 XIO”cm−’、拡散深さXj8を20
〜50μm■ エミッタ領域3,3゛の相互位置の重ね
幅d=200〜800pr11 (実施例) 第6図に示した本発明の一実施例の構造は次のようにし
て作られる。
■ Diffusion surface concentration N31 of base region 2.2゛ is 3×1
0" to 7 XIO"cm-', diffusion depth Xj8 to 20
-50 .mu.m. The overlapping width d of the mutual positions of the emitter regions 3, 3' is 200 to 800 pr11 (Embodiment) The structure of the embodiment of the present invention shown in FIG. 6 is manufactured as follows.

■両面が平滑な上記比抵抗範囲内のP型シリコン基板1
に水蒸気酸化膜付法により5iOz膜をつける。
■P-type silicon substrate 1 with smooth both sides and within the above specific resistance range
A 5iOz film is applied to the surface using the steam oxidation method.

■次に両面写真蝕刻法によりSin、膜を選択除去して
ベース領域2,2゛となるべき窓を開ける。
(2) Next, the Sin film is selectively removed by double-sided photolithography to open a window that will become the base region 2,2''.

そして5iozvをマスキングとして選択燐沈着を実施
し燐ガラスを除去したのち規定深さのベース領域2.2
”を拡散する。
Then, selective phosphorus deposition was performed using 5iozv as masking to remove phosphorus glass, and then the base area 2.2 to a specified depth was removed.
” to spread the word.

■その後同じく選択燐沈着法によってベース領域2,2
°内にオーミック領域5,5゛を形成する。
■After that, the base areas 2 and 2 are also
An ohmic region 5,5' is formed within 100°.

■SiO□膜上の燐ガラスを除去し、エミッタ領域3.
3°とチャネルストッパー領域4.4“にP型拡散層を
同時に選択拡散法により形成する。
■Remove the phosphorus glass on the SiO□ film and remove the emitter area 3.
P-type diffusion layers are simultaneously formed in the 3° and channel stopper regions 4.4'' by selective diffusion.

■その後半導体基板1の両面に半導体不活性ガラス膜を
全面に焼成し、 ■最後に写真蝕刻により外側のガラス膜6.6”を残し
て電極7,7゛の窓を開は蒸着、写真蝕刻法によって、
電極7,7゛を形成する。
■After that, a semiconductor inert glass film is baked on the entire surface on both sides of the semiconductor substrate 1, and ■Finally, the outer glass film 6.6" is left by photo-etching and the window of the electrode 7,7" is opened by vapor deposition and photo-etching. By law,
Electrodes 7, 7' are formed.

なお■、。に対する上記比抵抗範囲は余りにも広い。従
って実際的には比抵抗値を0.2Ωctn程度の区分で
選定しそれぞれのρに適した上記範囲内のN、やXj、
を調整して必要とする■8゜を得ると共に、エミッタ領
域3,3°直下の伝導度を一定に保持するエミッタ領域
を実施して必要な1.1を確保するのがよい。また第6
図中に示すようにP型のチャネルストッパ領域4,4“
を設け、半導体用ガラスを用いたブレーナ構造とするこ
とによって、PNPN防護デバイスを信頼度の高いもの
とすることができる。
In addition, ■. The above resistivity range is too wide. Therefore, in practice, select specific resistance values in divisions of about 0.2 Ωctn, and select N, Xj, or Xj within the above range suitable for each ρ.
It is preferable to adjust the angle to obtain the required angle of 1.8 degrees, and to maintain the required conductivity of 1.1 by creating an emitter region that maintains the conductivity constant just below the emitter region 3.3 degrees. Also the 6th
As shown in the figure, P-type channel stopper regions 4, 4''
By providing a brainer structure using semiconductor glass, the PNPN protection device can be made highly reliable.

(発明の効果) 以上から明らかなように、本発明によれば雷サージ防護
用として要求される緒特性を備えた高信頼僕なPNPN
サージ防護デバイスを提供できる。
(Effects of the Invention) As is clear from the above, according to the present invention, a highly reliable PNPN having the characteristics required for lightning surge protection.
Can provide surge protection devices.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は上記のPNPNサージ防護デバイスの断面構造
図、第2図はその等価モデル図、第3図はそのV−1特
性図、第4図、第5図、第7図。 第8図は本発明の特性決定のための図、第6図は本発明
の一実施例を示す断面構造図である。 特許出願人  日本電信電話株式会社 外1名
FIG. 1 is a cross-sectional structural diagram of the above-mentioned PNPN surge protection device, FIG. 2 is its equivalent model diagram, FIG. 3 is its V-1 characteristic diagram, and FIGS. 4, 5, and 7. FIG. 8 is a diagram for determining the characteristics of the present invention, and FIG. 6 is a cross-sectional structural diagram showing one embodiment of the present invention. Patent applicant: 1 person other than Nippon Telegraph and Telephone Corporation

Claims (1)

【特許請求の範囲】[Claims]  PNPNサージ防護デバイスにおいて、半導体基板を
P型とし、そのエミッタ領域をベース領域内の中央部に
おいて重ね合わせると共に、前記P型半導体基板の比抵
抗ρを1.0〜3.5Ωcm、ベース領域の拡散表面積
濃度N_S_Bを3×10^1^7〜7×10^1^8
cm^−^3、拡散深さxgmを20〜50μm、エミ
ッタ領域の重ね合わせ幅dを200〜800μmとした
ことを特徴とするPNPNサージ防護デバイス。
In the PNPN surge protection device, the semiconductor substrate is P type, the emitter region thereof is overlapped at the center of the base region, the specific resistance ρ of the P type semiconductor substrate is 1.0 to 3.5 Ωcm, and the base region is diffused. Surface area concentration N_S_B is 3 x 10^1^7 ~ 7 x 10^1^8
cm^-^3, a diffusion depth xgm of 20 to 50 μm, and an overlapping width d of emitter regions of 200 to 800 μm.
JP63137310A 1988-06-06 1988-06-06 PNPN surge protection device Expired - Lifetime JP2668238B2 (en)

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JP63137310A JP2668238B2 (en) 1988-06-06 1988-06-06 PNPN surge protection device

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JP63137310A JP2668238B2 (en) 1988-06-06 1988-06-06 PNPN surge protection device

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JPH01307264A true JPH01307264A (en) 1989-12-12
JP2668238B2 JP2668238B2 (en) 1997-10-27

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Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH04106935A (en) * 1990-08-27 1992-04-08 Shindengen Electric Mfg Co Ltd Dual direction thyristor
JPH04190623A (en) * 1990-11-22 1992-07-09 Fuji Electric Co Ltd Surge protector for semiconductor electronic appliance
JPH05218457A (en) * 1991-10-16 1993-08-27 Philips Gloeilampenfab:Nv Two terminal semiconductor device
CN109148432A (en) * 2017-06-15 2019-01-04 上海韦尔半导体股份有限公司 Surge Protector and preparation method thereof

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS54109386A (en) * 1978-02-15 1979-08-27 Nec Home Electronics Ltd Manufacture for silicon symmetrical switch
JPS58118151A (en) * 1982-01-06 1983-07-14 Toshiba Corp Bidirectional semiconductor switch element
JPS58188164A (en) * 1982-04-27 1983-11-02 Nec Corp High withstand voltage mis type semiconductor device
JPS61199664A (en) * 1985-03-01 1986-09-04 Toshiba Corp Semiconductor device

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS54109386A (en) * 1978-02-15 1979-08-27 Nec Home Electronics Ltd Manufacture for silicon symmetrical switch
JPS58118151A (en) * 1982-01-06 1983-07-14 Toshiba Corp Bidirectional semiconductor switch element
JPS58188164A (en) * 1982-04-27 1983-11-02 Nec Corp High withstand voltage mis type semiconductor device
JPS61199664A (en) * 1985-03-01 1986-09-04 Toshiba Corp Semiconductor device

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH04106935A (en) * 1990-08-27 1992-04-08 Shindengen Electric Mfg Co Ltd Dual direction thyristor
JPH04190623A (en) * 1990-11-22 1992-07-09 Fuji Electric Co Ltd Surge protector for semiconductor electronic appliance
JPH05218457A (en) * 1991-10-16 1993-08-27 Philips Gloeilampenfab:Nv Two terminal semiconductor device
CN109148432A (en) * 2017-06-15 2019-01-04 上海韦尔半导体股份有限公司 Surge Protector and preparation method thereof

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