JPS61194971A - Circuit for determining picture element for enlargement/ reduction circuit of variable density images - Google Patents

Abstract

PURPOSE:To obtain high quality images by performing enlargement or reduction at the operation step where density of each picture element is represented in a binary number of (n) bits. CONSTITUTION:Densities Dp:a, Dg:b, Dr:c and Ds:d of picture elements P, Q, R and S read out of the back-up memory 11 are stored in registers 16-19, and sent to adders 20-23. Calculation arithmetic circuits 24 and 25 respectively perform (Dr+Ds)-(Dp+Dg)=Dx and (Dg+Dr)-(Dp+Ds)=Dy to calculate absolute values (n) and (p) of Dx and Dy and symbols O and (g). Multipliers 26 and 27 respectively perform Ax¦Dx¦:t and Ay¦Dy¦:u, or multiply absolute values (n) of Dx and (p) of Dy by the lower (h) bits of the X address Ax:r and the lower (h) bits of the Y address Ay:s respectively generated by the X and Y address generator circuits 13 and 14. Arithmetic operation circuits 28 and 29 add or subtract Ac¦Dx¦/K and Ay¦Dy¦/K(K=2K) to or from Dp+Dg and Dp+Ds. The adder 30 adds up these values to generate (Dp+Dg+Dr+ Ds)+{(AxDx+AyDy)/K}. For the display output device 15, the least significant bit is ignored, and [(Dp+Dg+Ds)+{(AxDx+AyDy)/K}]/2 is given as the density (z) of new picture elements.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to an image enlarging/reducing circuit, and more particularly to a pixel determining circuit in a grayscale image enlarging/reducing circuit.

[Conventional technology]

The conventional method for enlarging/reducing grayscale images using the above circuit is as follows:
The original image, in which each pixel has shading, is converted into a binary image using means such as dithering or density patterning, and then enlarged or reduced.

[Problem that the invention seeks to solve]

However, when using the conventional enlarging/reducing methods mentioned above, such as the dither method or the density pattern method, the shading of each pixel is once separated into multiple pixels, so when enlarging/reducing the image, the image becomes rough or the outline blurs. This has the disadvantage of causing deterioration in image quality.

The present invention provides a pixel determining circuit which solves the above-mentioned problem by performing enlargement/reduction at the stage when the density of each pixel is expressed as an n-bit binary number.

[Means for Solving the Problems] The present invention expresses the density of each pixel as a binary number of n pits.The horizontal direction is the X axis, and the vertical direction is the Y axis. , when the coordinate unit is 1/K (K=24) between pixels, and the horizontal and vertical expansion/reduction ratios of the orthogonal coordinate system are α=/L, ,β=Le-7, respectively. ,0≦
Coordinates T (αr
, Lz* cyLy), and x1≦αAx<
'h + 3/1≦(LyLy≦y2 Pixel P("t +11) eQ(zt-yz)e of the original image
Determine the color of the pixel at the coordinate T(GZLZIα) by R(2:21Y2)l 5(Zz+Yx), and sequentially
In a circuit that enlarges or reduces an image by changing cLv, the density of each pixel P, Q, R, and S of the original image is set to D.
If p*Dp rD7 rDs, then Dp-”D6+ D
An adder that generates p"Dys Dy"Dr+Dp+Ds, and (Dr+D8)-(D
.

+Dρ=D, and (Dr”Dr)−CDp+Ds)=
Two sets of arithmetic units that perform subtraction of Dy and generate respective signs and absolute values, X address α-〇, Y address cLyLy
Two sets of multipliers perform multiplication of the lower 4 bits A, , A11 and D, D, and Dp+Dy and Dp+DB, respectively.
Add A, D, /K to D, / (D, +DfP)
+ (A, D, /K) and (Dr+Ds)” (A
Two sets of arithmetic units that generate yDyc), and (Da+D,)
+(A-K), (D, +D,)+ (A, D1
This is a pixel determining circuit in a grayscale image enlargement/reduction circuit characterized by comprising an adder for adding //K).

〔Example〕

FIG. 1 is a diagram showing an outline and data flow of an image enlargement/reduction circuit using the pixel determination circuit of the present invention. The enlargement/reduction circuit 2 is given in advance by the CPU 4 the enlargement/reduction ratio, the increment of the X address, the Y address, and the size of the image. An image input device 1, typically a scanner or a storage device, sequentially converts an image into a pixel density α, and stores this in a buffer memory 5. When the density α of pixels for several lines is stored in the buffer memory 5, the buffer memory control circuit 6
is the original image pixel P(Wt+1/,)*Q(Zx+
Yz) + R(Zzyyz) + 5(sc2.yt).

her r) r+ DB is read out by generating a buffer memory control signal d and sent to the pixel determining circuit 9. signal 71
L)+t''+8 are the respective concentrations DJ)I Dp+ I)r+
It corresponds to D8. Here, set the input start point of the original image to the origin (0
, 0), the size of each pixel in the X and Y directions is divided into = 24, and the coordinate unit is the size, and the enlargement/reduction ratio in the X and Y directions is α = /L, , β = / L1. Expressed as (
c, 11) = (cLzLz,c 1 for the coordinate T
When pixels are generated, if the number of pixels in the X direction and Y direction of the image is WxIw/, the corners -α, Lπ, Xg, = αiy
Since pixels can be generated until , the number of pixels in the X direction and Y direction is -/L2. , Mind νization.

Therefore, the original image can be multiplied by 1 times KA-z and K/L, respectively. Therefore, the parameter/timing control circuit 10
generates increments in the X direction and Y direction, :g, Lv:f, and the 7'C buffer memory control circuit 6 generates the X address addition signal t for one line each time the buffer memory 5 is read. Each time the buffer memory 5 is read, a Y address addition signal is generated to generate an X address and a Y address. It can be controlled by the image size i. By the way, the pixel determination circuit 9 determines the density of each of the above-mentioned pixels P, Q, R, and S.

Dl r Drs The pixel density at the coordinates (cL+Lz+ayLy) is determined from Ds, the X address, and the Y address, and is sent to the image output device 3 typified by a display, printer, or storage device.

Next, the configuration and operation of the pixel determining circuit will be explained using FIG. 2, which shows one embodiment of the present invention.

In FIG. 2, registers 16.17 and 18.19 contain pixels P, Q, and R read out from the backup memory 11, respectively.
, S()s:d, - each concentration Dp:α+ DfP:bt D,>c, ,
, is stored by the write pulse e generated by the Huffmeter/timing control circuit 12. Register 6, 17.
18. Densities Dp:f and Dp:t* stored in 19 respectively
Dr: N, D5: j to adders 20 and 21.

22.Add in 23, respectively D, +DIi+, :j, D
? , +D8:A, D, +Ds=1, D, , +Dr:
generate m. The arithmetic operation circuits 24 and 25 are each (Dr
+Ds)-(D,)+Dg,)=Dzs (Dy+I
)r)-(Dp+Ds)=Dy, and calculate the absolute value n of )
and the sign O, the absolute value p of ~ and the sign t are generated. The multipliers 26 and 27 input the lower n bits of the X address generated by the X address generation circuit 13 and the X address generation circuit 14, respectively: r, the lower 4 bits of the Y address to 28 and the absolute value n5 of the absolute value p of Dy. and each AzlDzl
Generate :t, AylDyl :u. The arithmetic operation circuits 28 and 29 are Dp+D, +Dp” A and 1n are applied to D8.
It adds or subtracts A, ID, l/K to zl/. If the sign 6 of ) or the sign t of D is positive, addition is performed, and if it is negative, subtraction is performed. Adder 30 (D, +D , )+ (A
From 2. //K):υ, (D.

"Ds)" (AyDy/K): Add @D, (Dp"Dy+Dr+Ds)" (%D+
A11DY)/K) is generated. For the image output device 15, [(Dp+D
.

+D? , +DS )+ ((Aaz”A11Dy)/K
)]/2 is sent as density 2 of the new pixel.

〔Effect of the invention〕

As explained above, according to the present invention, when I! Since the image that expresses the lightness of the image is enlarged or reduced at the stage where the density of each pixel is expressed as an n-bit binary number without first decomposing it into multiple pixels, there is no fluctuation in the image, and therefore image deterioration is reduced. This has the effect of making it possible to obtain high-quality images with less noise.

[Brief explanation of the drawing]

FIG. 1 is a diagram showing an outline of the image enlargement/reduction path and data flow using the pixel determining circuit of the present invention, and FIG. 2 is a block diagram of a circuit showing an embodiment of the pixel determining circuit of the present invention. It is. 1... Image input device, 2... Enlarging/reducing circuit, 3...
...Image output device, 9...Pixel determination circuit, α...Pixel density, i...Size of original image, p...Density of pixel P, ? ...Density of pixel Q, r...Density of pixel R, S
... Density of pixel S, 11 ... Buffer memory, 12
...parameter/timing control circuit, 13...X
Address generation circuit, 14...X address generation circuit, 1
5... Image output device, 16, 17.

Claims (1)

[Claims] (1) Horizontal W that expresses the density of each pixel as an n-bit binary number
The horizontal direction of the matrix original image of __x pixels and vertical W_y pixels is the X axis, the vertical direction is the Y axis, and 1/K between pixels (K = 2^h)
is the unit of coordinates, and the horizontal and vertical expansion/reduction ratios of the orthogonal coordinate system are α=K/L_x and β=K/L_y, respectively, then 0≦a_xL_x≦W_x, 0≦a_yL_
Coordinates T (a_xL_x, a_y
L_y), x_1≦a_xL_x<x_y
, y_1≦a_yL_y≦y_2 pixels P(x_1, y_1), Q(x_1, y_2), R of the original image such that y_1≦a_yL_y≦y_2
(x_2, y_2), S(x_2, y_1) to determine the color of the pixel at coordinates T (a_xL_x, a_yL_y), and sequentially change a_x, a_y to enlarge or reduce the image. pixels P, Q, R, S
Let the respective concentrations of D_p, D_g, D_r, and D_s be D_r+D_s, D_p+D_g, D_g+D_r,
An adder that generates D_p+D_s and an adder connected to the output of the adder (D_r+D_s)-(D_p+D_g)=D
_x and (D_g+D_r)-(D_p+D_s)=D
Two sets of arithmetic units that perform subtraction of _y and generate respective signs and absolute values, an X address a_xL_x, and a Y address a_
Lower h bits of yL_y A_x, A_y and D_x, D_
two sets of multipliers that perform multiplication with y, and D_p+D_g, D
Two sets of arithmetic units that add A_xD_x and A_yD_y/K to __p+D_s to generate (D_p+D_g)+(A_xD_x/K) and (D_r+D_s)+(A_yD_y/K), and (D_p+D_g)+(A_xD
_x/K), (D_r+D_s)+(A_yD_y/K
), and an adder for adding .