JP3234422B2 - Pseudo gradation processor - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a pseudo-gradation processing device for simulating the display of a predetermined number of bits or more in a display device which performs display using image display data of predetermined bits. In other words, the present invention relates to a pseudo-gradation processing device for further increasing the gradation display of the LCD display device by a digital driver of a predetermined bit and performing a display close to an image.

[0002]

2. Description of the Related Art In recent years, high-definition color LCD displays for multimedia office automation have been developed. The color LCD has a built-in 3-bit or 4-bit digital driver for each of R, G, and B colors. For example,
Color LCD with 3-bit digital driver
A display of eight gradations for each color is possible, and a total of 512 colors can be displayed. However, this is sufficient when used simply as a monitor for OA, but is insufficient for displaying video such as moving images and still images for multimedia, and further increase in gradation is desired. Was rare.

Therefore, a method has been proposed in which a component which cannot be displayed by one pixel is diffused into an adjacent pixel around the same screen frame (error diffusion within a frame) to thereby increase the number of gray levels in a pseudo manner. In the present specification, the term error data means data represented by lower bits that cannot be displayed by a digital driver of a display device among constituent bits of image data.

FIG. 12 shows a pseudo gradation processing apparatus using error diffusion in a frame. A device for performing pseudo gradation processing by holding lower-order bits of image data of one pixel that are not displayed as error data and adding the error data to the image data of the next pixel. I have. In FIG. 12 , a latch circuit 11 latches 6-bit original image data GD sequentially applied in synchronization with a dot clock DCK and outputs the same to an arithmetic circuit 12. The arithmetic circuit 12 includes an original image data GD and an error data holding circuit 13
Are added to generate the 6-bit corrected image data. The error data holding circuit 13
The lower 2 bits of the corrected image data are converted to the dot clock DCK.
And outputs it to the arithmetic circuit 12 when the original image data GD of the next pixel is latched by the latch circuit 11.
The upper 4 bits of the corrected image data are the image display data HD
And applied to the output latch circuit 14. By performing display using the 4-bit image display data HD, lower-order 2-bit error data is sequentially diffused to adjacent pixels, so that an intermediate gradation is displayed by averaging the luminance of a plurality of pixels. become.

That is, when the original image data is "100010", first, "00" of the error data EI is added to the original image data GD "100010" to generate corrected image data "100010", “10” is held in the error data holding circuit 13 as the error data EI, and the upper 4 bits “1000” are output as the image display data HD, but the error data EI “10” is added to the next original image data GD. Therefore, the corrected image data becomes “100100”, and the error data EI holds “00”. By repeating this operation, “1000” and “1001” are alternately displayed for each pixel, so that half-tone display is performed by the two pixels. The 1/4 gradation represented by the least significant bit of is represented by four pixels.

Therefore, by applying this pseudo gradation process to each of the R, G, and B colors, the gradation of each color can be expressed in the same 64 gradations as the original image data GD. However, in the above-described pseudo gradation processing device, since the error diffusion process is a horizontal addition process, the effect of the left image is transmitted to the right image, and as a result, the image display data is affected. If there is movement of the displayed image or if the shading changes, this pseudo-gradation processing can achieve a significant improvement in image quality, but the shading of the displayed image, such as the sky or a human face, can be reduced. In a flat case, the influence of the error data due to the change in the discontinuous image data on the left side appears to the extent that it can be recognized by the eyes, and the image quality of the display deteriorates.

For example, when a flat background screen is displayed on a personal computer screen and the mouse cursor crawls on the screen, it looks as if the mouse cursor has a tail. That is,
When the mouse cursor is displayed in a flat image of light and shade, an error in the image data for displaying the mouse cursor appears on the far right side, and the image changes there.

In a flat image of light and shade,
Since the carry due to the addition of the error data occurs periodically, the position of the brighter pixel and the position of the darker pixel are
Since the coincidence occurs in the adjacent horizontal scanning lines and also in each frame, a vertical line appears on the display screen, causing deterioration in image quality. Therefore, the present applicant has invented an improved proposal disclosed in Japanese Patent Application No. 4-286055. The content is determined by comparing the image data of the immediately preceding pixel with the image data of the current pixel. If the difference is equal to or greater than a predetermined value, the outline (edge) of the image, that is, the relation between the previous image and the future image is compared. It is determined that there is no error, and the error data accumulated so far is reset. As a result, it was possible to prevent the influence of the previous image from appearing on the next image of different quality.

[0009] Further, the applicant of the present application has filed Japanese Patent Application No. 5-2786.
No. 93 was invented. The content is such that, in a flat gray-scale image, error data is reset for each pixel number of a numerical value represented by the bit number of error data, and the timing of the reset pixel is different for each horizontal scanning line. It is. According to this improvement, in a flat image, the carry caused by the error data is dispersed for each horizontal scanning line to eliminate the occurrence of a specific pattern, and the effect of the error data does not remain until later. Image quality is improved

[0010]

However, if the edge of the image is detected and the error data is reset,
Since there is no accumulation of error data of the image after the edge, the effect of error diffusion does not appear in the image near the edge, and there is a concern that the image quality may be degraded. In particular, in the case of a display in which flat images having different color tones or luminances overlap each other, such as an image created by a computer, the deterioration of the image quality is conspicuous in a portion after the boundary. When a line or the like having a slightly different luminance (a luminance difference represented by the number of bits of error data) is displayed on a flat screen, the boundary is taken as an edge and the error data is reset. There was a risk that the data would not carry and that line would not be displayed.

Further, as described above, in the pseudo gradation processing apparatus for periodically resetting error data, the reset timing is set to be different for each line, but the edge is detected regardless of the timing. When the error data is reset in this manner, there is no accumulation of error data after the edge, as in the case described above, so that no carry occurs near the edge and there is a concern that the image quality may be degraded.

[0012]

SUMMARY OF THE INVENTION The present invention has been made in view of the above points, and has an arithmetic means for adding accumulated error data to each image data supplied for each pixel;
Error data holding means for accumulating and holding a predetermined number of lower-order bits of the processed image data obtained as a result of the arithmetic means as error data for the next pixel, and an error for diffusing the error data to other pixels. In a pseudo gradation processing apparatus for performing diffusion processing to add gradation information equal to or more than the number of gradations that can be displayed by the image display data to image display data having a smaller number of bits than the number of bits of the image data, corresponding to the change of the image data supplied to each, based on the error data image data after the change has, assuming that image data after the change is continuous from the previous change
Error to be added to the image data of the pixel immediately after the change
Create data and select the error data by the selection means
The arithmetic means is applied to the pixel data of the pixel immediately after the change.
And is stored in the error data storage unit.
Processed image obtained as a result of the operation means, which is power data
Error data creating means for creating error data of a predetermined number of lower-order bits of data; and converting the error data created by the error data creating means into error data held in the error data holding means and supplying the error data to the arithmetic means. After the image data is changed, the influence of the error data before the change is eliminated, and an error diffusion process based on the created error data is enabled.

Further, there are a plurality of reset means for resetting error data of the error data holding means, error decoding means for decoding error data of the image data, and a plurality of reset patterns for determining a pixel position at which reset is performed. According to the decoding output of the error decoding means,
One of the patterns being selected, reset control means for controlling the reset means based on the reset pattern, reset pixel positions reset according to the reset pattern selected by the reset control means, and pixel positions of the supplied image data Pixel distance data generating means for generating pixel distance data indicating the separation distance, and corresponding to a change in the image data supplied for each pixel, based on error data of the pixel after the change and the pixel distance data of the pixel. Error data creating means for creating error data to be held in the error data holding means, assuming that the image data after the change has been continuous before the change; The error data is converted to error data held in the error data holding means and supplied to the arithmetic means. And a selection unit, after the change of the image data, by eliminating the influence of previous error data change is obtained by allowing the error diffusion processing based on the error data created in the above.

The error data creating means creates error data to be added to the image data of the pixel immediately after the change, and the error data is selected by the selecting means, and is added to the image data of the pixel immediately after the change. The addition corresponds to a specific image. Further, the error data to be added to the image data of the pixel immediately after the change is not added to the image data of the pixel immediately after the change, and the error data to be added to the image data of the pixel next to the pixel immediately after the change is the error data. The error data is created by the error data creating means, and the created error data is held in the error data holding means so as to correspond to a specific image.

The error data to be added to the image data of the pixel next to the pixel immediately after the change held in the error data holding means is the error data by the selection means when further succeeding pixels are discontinuous. without selecting the error data of the data holding means, said error data is not added, further wherein further
By selecting the error data to be added to the subsequent pixels, it corresponds to a specific image.

[0016]

According to the above means, when the supplied image data of the pixel is different from the image data of the previous pixel and is recognized as an edge, the error data held in the error data holding means before the change is stored in the error data holding means. Instead, the error data created by the error data creating means is added to the image data after the change, so that the error data of the pixel before the change is prevented from affecting the pixel after the change. , The error diffusion of the pixels becomes uniform. Here, the error data generating means considers that the image data after the change is continuous from before the change, and uses the error data of the pixel after the change to add the error data to be added to the image data after the change. create.

Further, the reset control means selects one of a plurality of reset patterns based on the error data of the image data. Therefore, the reset means is controlled by the selected reset pattern, and the error data holding means is provided. Is periodically reset.
Therefore, by generating pixel distance data indicating the distance of the pixel after the change from the reset pixel position of the reset pattern selected by the error data of the image data after the change by the pixel distance data generating means, the image data after the change Assuming that the data has been continuous before the change, error data to be added to the image data after the change can be created based on the pixel distance data and the error data.

Further, by adding the created error data to the pixel data immediately after the change, a display with a small display change such that there is only a change within the range of the number of bits of the error data is displayed on a flat screen. If you do.
Further, the error data created for the next pixel is not added to the image data immediately after the change but is held in the error data holding means as error data of the next pixel. It corresponds to image data, for example, a checkered pattern created by a computer.

Further, when the image data of the pixel following the pixel immediately after the change is discontinuous, error data to be added to the image data of the next pixel immediately after the change is not added. It supports a checkered pattern using two pixels.

[0020]

FIG. 1 is a block diagram of a pseudo gradation processing apparatus showing an embodiment of the present invention. The pseudo gradation processing apparatus is provided between an output section of original image data of each color of R, G and B and an LCD driver of each color. Of the device to be processed, and processes the 8-bit original image data GD to generate 4-bit image display data HD.
Is a device for outputting to a 4-bit input LCD driver.

In the pseudo gradation processor of FIG. 1, the latch circuit 21 is a circuit for sequentially holding 8-bit original image data GD inputted in synchronization with the dot clock DCK. D-FFs. The arithmetic circuit 22 outputs the image data GD output from the latch circuit 21.
And 4-bit error data E output from the selector 23
This is an 8-bit addition circuit for adding D. Of the 8-bit output processed image data of the arithmetic circuit 22, the upper 4 bits are held in the latch circuit 24 by the dot clock DCK, and are stored in the LCD 4 as image display data HD.
Supplied to the bit input digital driver. The latch circuit 24 includes four D-FFs.

On the other hand, the lower 4 bits of the 8-bit output processed image data of the arithmetic circuit 22 are used as error data EN to be added to the image data of the next pixel.
5 is supplied. The reset circuit 26 to which the output of the error data holding circuit 25 is applied performs reset control of an operation of supplying the error data EN held by the error data holding circuit 25 to the selector 23 as it is and an operation of supplying data of “0000”. It is controlled by the output RES of the circuit 27. The error data holding circuit 25 includes four D-FFs, and the holding operation is controlled by the dot clock DCK. Therefore, the error data holding circuit 25 holds the error data accumulated up to one pixel before.

The reset control circuit 27 outputs the image data GD
Based on the lower 4 bits of
An optimum reset pattern corresponding to the error data is selected from a plurality of reset patterns for determining a pixel position for resetting the error data ED, and the reset circuit 26 is controlled. This is a circuit that outputs pixel distance data PDD indicating how far a pixel of the image data GD is from a reset pixel position determined by a selected reset pattern.

The error data creating circuit 28 to which the pixel distance data PDD is supplied is recognized when the image data GD held in the latch circuit 21 is different from the image data GD of the previous pixel, that is, as the edge of the image. In this case, assuming that the changed image data GD held in the latch circuit 21 has been continuously supplied from before, the current pixel, that is, the image data GD held in the latch circuit 21 The error data ME1 to be added to the pixel is created, and the error data ME2 to be added to the image data GD of the next pixel is created, assuming that the image data of the pixel next to the current pixel is the same. Circuit. The specific operation of the error data creation circuit 28 will be described later in detail, but the configuration thereof includes an addition circuit 29 that adds “1” to the pixel distance data PDD and a pixel distance data PD
An adding circuit 30 for adding "2" to D; a latch circuit 21
The multiplication circuit 31 multiplies the error data GDE of the image data held in the multiplication circuit by the output of the addition circuit 29, and the multiplication circuit 3 similarly multiplies the error data GDE by the output of the addition circuit 30
2 and the output of the multiplication circuit 31 is the error data M
The signal is output to the selector 23 as E1, and the output of the multiplication circuit 32 is output to the selector 23 as error data ME2.

The selector 23 determines whether the error data ME 1, ME 2,
This is a circuit for selectively outputting the output of the error data holding circuit 25 via the ME 2 and the reset circuit 26, and its operation is controlled by a control signal SEL of the image data discriminating circuit 33. On the other hand, a mask circuit 34 is provided between the latch circuit 21 and the arithmetic circuit 22. This mask circuit 34
Is provided in the lower 4 bit signal line of the 8 bit image data GD. That is, an operation of passing the error data GDE and an operation of applying the data “0000” to the arithmetic circuit 22 while masking the error data GDE are performed. The control of this operation is performed by the control signal MSK of the image data discrimination circuit 33 according to the continuity and discontinuity of the image data GD. Therefore, the error data GDE
Is masked, even if the error data ED selected by the selector 23 is added in the arithmetic circuit 22, no carry occurs in the upper 4 bits, and the error data ED of the selector 23 is , And the error data ED is not added to the image data GD held in the latch circuit 21. Details will be described later.

Next, the reset control circuit 27 will be described with reference to FIG. The reset control circuit 27 decodes the 4-bit error data GDE,
Error decoding circuit 35 for generating 16 decoding outputs
And a pattern selection signal generating circuit 3 for selecting one of the five set reset patterns according to the decode output.
6 and 5 reset patterns and reset pattern generation circuits 37, 38, and 3 for generating pixel distance data indicating the distance of the current pixel from the reset pixel position.
9, 40, 41, a 4-bit H line counter 42 for counting the horizontal synchronization signal HSYNC in order to generate a reset pattern, and a reset pattern generation circuit 3
The selector 43 is configured to select one of 7 to 41 based on the output of the pattern selection signal generating circuit 36.

In this embodiment, there are five types of reset patterns, and a pattern selection signal generating circuit 36 for generating a pattern selection signal SEL in accordance with the decoded output of the error decoding circuit 35 will be described later in detail. When the value is "1" or "15", the first reset pattern is selected, and the value of the error data is "2", "3",
At the time of “8”, “13”, “14”, the second reset pattern is selected, and the value of the error data is “4”, “6”, “1”.
When the value is "0" or "12", the third reset pattern is selected. When the value of the error data is "5" or "11", the fourth reset pattern is selected. The value of the error data is "7".
It operates so as to select the fifth pattern at "9".

On the other hand, reset pattern generation circuits 37-4
Reference numeral 1 denotes a circuit for generating first, second, third, fourth, and fifth reset patterns, and outputs a reset signal corresponding to each reset pattern for each horizontal line counted by the H line counter 42. The pixel position where the error data EN is generated is determined. The H line counter 42 is reset by the vertical synchronization signal VSYNC, and counts 16 horizontal lines repeatedly by counting the horizontal synchronization signal HSYNC. In this embodiment, since the number of bits of error data is 4 bits, a reset pattern is set in an area of 16 pixels in the horizontal direction × 16 lines in the vertical direction, and this area (pattern area) is displayed on the screen. Repeated.

Each of the reset pattern generation circuits 37 to 41 has an H line decoder 45 for decoding the count value of the H line counter 42 as shown in the block diagram of FIG.
And a 4-bit dot counter 46 for counting the dot clock DCK, and a preset data generating circuit 47 for generating preset data corresponding to a horizontal line in the dot counter 46 based on the output of the H line decoder 45.

The H line decoder 45 detects the count value of the H line counter 42, that is, which line in the pattern area the line to be displayed is located. Then, preset data corresponding to each line of the pattern area is set in the preset data generation circuit 47 and selected by the output of the H line decoder 45. The selected preset data is preset in the dot counter 46 by the horizontal synchronization signal HSYNC. Further, since the preset data set for each line differs in the reset pattern generation circuits 37 to 41, the first to fifth reset patterns can be created. The reset signal RESn is output from the dot counter 46.
Is output when the count value of is "15". The count value CNTn of the dot counter 46 is output to the pattern selection circuit 43 as pixel distance data.

Next, an example of the reset pattern and the carry pixel position at that time in this embodiment, that is, 16 × 16
Are shown in FIGS. 4 to 8. In FIG. 4 to FIG. 8, the numbers of the pixel positions are given in the horizontal direction, and the line numbers are given in the vertical direction. FIG. 4A is a schematic diagram of a pattern area showing a first reset pattern set in the reset pattern generation circuit 37. FIG. This reset pattern is a pattern selected when the error data of the image data is “1” and “15”. In this pattern, when the line is “1”, the pixel is reset at the first pixel “1”. Since the reset circuit 26 is operated when the pixel to be reset is latched by the latch circuit 21 by the dot clock DCK, the preset data preset in the dot counter 46 is one before “15”, that is, "14". Preset data corresponding to each line is determined as shown in the figure, such as "8" for the preset data for line "2" and "2" for line "3" as shown in the figure. In this reset pattern, the reset pixel position of the next line is shifted to the right by 6 pixels with respect to the previous line. Therefore, for example, on a continuous screen in which the error data GDE is “1”, # shown in FIG.
Carry occurs at the pixel position of the mark.

FIG. 5A is a schematic diagram of a pattern area showing the second reset pattern set in the reset pattern generation circuit 38. This reset pattern is a pattern in which the reset pixel position is shifted three pixels to the right with respect to the previous line, and the error data of the image data is “2”,
This is a pattern selected in the case of “3”, “8”, “13”, and “14”. In this pattern, when the line is “1”, the pixel is reset at the first pixel “1”. Therefore, the preset data is “14”. Preset data corresponding to each line is determined as shown in the figure, such as "11" for the preset data for the line "2" and "8" for the line "3" as shown in the figure. Therefore, for example, the error data G
In a continuous screen in which the DE is “8”, a carry occurs at the pixel position indicated by the mark # shown in FIG. 5B.

FIG. 6A is a schematic diagram of a pattern area showing a third reset pattern set in the reset pattern generation circuit 39. This reset pattern is a pattern in which the reset pixel position is shifted to the right by 14 pixels with respect to the previous line, and the error data of the image data is “4”,
This is a pattern selected in the case of “6”, “10”, and “12”. In this pattern, when the line is “1”, the pixel is reset at the first pixel “1”.
Therefore, the preset data is “14”. Preset data corresponding to each line is determined as shown in the drawing, such as preset data "0" for line "2" and preset data "2" for line "3". Therefore, for example, the error data GD
In a continuous screen in which E is “4”, a carry occurs at the pixel position indicated by the mark # shown in FIG.

FIG. 7A is a schematic diagram of a pattern area showing the fourth reset pattern set in the reset pattern generation circuit 40. This reset pattern is a pattern in which the reset pixel position is shifted to the right by 11 pixels with respect to the previous line, and the error data of the image data is “5”,
And the pattern selected in the case of “11”. In this pattern, when the line is “1”, the pixel is reset at the first pixel “1”. Therefore, the preset data is “14”. Preset data corresponding to each line is determined as shown in the drawing, such as "3" for the preset data at the time of the line "2" and "8" at the time of the line "3". Accordingly, for example, on a continuous screen in which the error data GDE is “5”, a carry occurs at the pixel position indicated by # in FIG. 7B.

FIG. 8A is a schematic diagram of a pattern area showing the fifth reset pattern set in the reset pattern generation circuit 41. This reset pattern is a pattern in which the reset pixel position is shifted to the right by 13 pixels with respect to the previous line, and the error data of the image data is “7”,
And the pattern selected in the case of “9”. In this pattern, when the line is “1”, the pixel is reset at the first pixel “1”. Therefore, the preset data is “14”. Preset data corresponding to each line is determined as shown in the drawing, such as "1" for the preset data at the time of the line "2" and "4" at the time of the line "3". Therefore,
For example, on a continuous screen in which the error data GDE is “7”, a carry occurs at the pixel position indicated by the mark # shown in FIG. 8B.

As described above, in this embodiment, five types of reset patterns are set. Basically, there are fifteen types of reset patterns corresponding to each value of each pixel data. However, carry-over pixel positions from "0" to "7" and non-carrying pixel positions from "8" to "15" of the error data form an inverted pattern. In other words, the pattern for making the carry pixel position uniform and the pattern for making the non-carry pixel position uniform can be made the same. Further, in the present embodiment, reset patterns having little difference in screen uniformity are shared and grouped into five types.

As described above, as shown in FIGS. 4 to 8, by changing the reset pattern according to the contents of the error data GDE, the image data is generated by the specific image data on the same, that is, a flat screen. Generation of patterns can be prevented. FIG. 9 is a diagram showing a change pattern of the image data GD, and this change pattern is detected by the image data discrimination circuit 33. Hereinafter, the operations of FIGS. 1, 2 and 3 will be described for each case shown in FIG.

Processing Example 1 First, FIG. 9A shows a case where the same image data Da is continuously supplied and different image data Db is continuously supplied after the pixel n.
For example, when the error data GDE of the image data Da is “1”, the outputs RES1 and CNT1 of the reset pattern generation circuit 43 are selected by the error decoding circuit 35, the pattern selection signal generation circuit 36, and the pattern selection circuit 43. That is, the reset pattern shown in FIG. 4 is selected. On the other hand, the selector 23 supplies the output of the reset circuit 26 to the arithmetic circuit 22 based on the output SEL of the image data determination circuit 33. Here, the pixel of the image data GD held in the latch circuit 21 is the pixel n-4 of FIG. 9A, and the pixel “7” of the line “2” shown in FIG. In this case, the reset signal RES1 is generated because the count value of the dot counter 46 is “15”. Therefore, the reset circuit 26 outputs “0” to the arithmetic circuit 22.
, The error data is not added to the image data Da. On the other hand, the lower 4 bits of the output of the arithmetic circuit 22 are the error data of the pixel n-4, and the error data E
N is held in the error data holding circuit 25 by the next dot clock DCK. Then, the next pixel n−3 (=
In 8), since the reset signal RES1 is not generated, the held error data EN is output from the reset circuit 26 to the arithmetic circuit 22, so that the error data ED is added to the next pixel.

Next, at the pixel n (= 11), the image data changes to image data Db. Error data GDE of image data Db
Is "8", the reset control circuit 27 selects the reset pattern created by the reset pattern generation circuit 38, that is, the reset pattern shown in FIG. On the other hand, the image data determination circuit 33
At the time of (= 11), the selector 23 is controlled to select the output ME1 of the error data creation circuit 28 and output it to the arithmetic circuit 22. At this time, the count value CNT2 of the dot counter 46 of the reset pattern generation circuit 38 is selected by the pattern selection circuit 43 and supplied to the error data creation circuit 28 as pixel distance data PDD. Error data creation circuit 2
8 is the error data E to be added to the pixel n (= 11), assuming that the image data Db has been continuous before the change.
D is created. As can be seen from FIG. 5A, the error data ED to be added to the pixel “11” on the line “2” is data obtained by adding the error data GDE seven times from the reset pixel position “4”. Therefore, the count value of the dot counter 46 is “6” at the pixel n (= 11) (that is, it indicates the position of the immediately preceding pixel).
Therefore, the addition circuit 29 adds “1”. The added numerical value “7” and the error data “8” are multiplied by the multiplying circuit 31, and the lower 4 bits of the multiplication result are error data ED to be added and are output to ME 1. Therefore,
The error data ME1 selected by the selector 23 is added by the arithmetic circuit 22 to the image data Db of the pixel n (= 11). The error data EN resulting from the addition is used as the error data ED to be added to the pixel n + 1 as the error data holding circuit 2.
5 is held. In the pixel n + 1, the selector 23 selects the output of the error data holding circuit 25 via the reset circuit 26.

With the above operation, the error data ME1 to be added to the pixel n is created, and error diffusion is performed on the assumption that the image data GD of the pixel after the change is continuous from before the change. Processing Example 2: In the above-described processing example 1, the error data ED is added to the pixel n immediately after the change, and a good effect is obtained. However, when a change in the pixel is detected and the addition operation is performed, (b) in FIG. )
In the case of, there is a disadvantage. That is, this is a case where the image data GD changes for each pixel. Such a pixel pattern is used when a computer produces a flat image of an intermediate color that cannot be represented by image data. In other words, this is a case where an intermediate color is to be obtained by alternately outputting different image data GD for each pixel. That is, it is a pattern called a checkered pattern. In this pattern, if the same processing as in the processing example 1 is performed, the error data created for each pixel is added, so that a carry may occur in a specific pixel and the pattern may be recognized as a pattern. .

To cope with the pattern shown in FIG. 9B, even if a change in the image data GD is detected, no error data is added to the pixel n immediately after the change.
Since the change width of the image data GD is large in the case of a normal checkerboard pattern, the image data discrimination circuit 33 detects that the change width is equal to or larger than a predetermined value. At this time, even if the change width is equal to or larger than a predetermined value, the pixel n + 1 and the subsequent pixels may be the same as the pixel n. In this case, error data to be added to the image data GD of the pixel n + 1 is created. The operation will be described below.

As described above, it is assumed that the error data GDE of the image data Db is “8” and the pixel position of the pixel n is the pixel “11” of the line “2”. Pixel n (= 11)
, The image data determination circuit 33 controls the selector 23 to select the output ME2 of the error data creation circuit 28, and controls the mask circuit 34 by the control signal MSK to cut off the error data GDE of the image data GD. The image data GD having the error data “0” is calculated by the arithmetic circuit 22.
Output to

On the other hand, when it is assumed that the image data GD of the pixel n continues thereafter, the error data ED to be added to the pixel n + 1 (= 12) becomes the error data “8” from the reset position of the pixel “4”. Is the data added eight times. Thus, the addition circuit 3 adds the count value “6” of the dot counter 46 to
At 0, “2” is added. The added data "8" is multiplied by the error data "8" in the multiplication circuit 32. The lower 4 bits of the multiplication result are error data ME2
Is output as Therefore, the error data ME2 selected by the selector 23 is added in the arithmetic circuit 22, but since the lower 4 bits of the image data GD are "0", no carry is generated by the addition, and the lower bit of the output is not generated. 4
The error data ME2 is output to the bit as it is.
The error data EN is held in the error data holding circuit 25. Therefore, in this case, the image data G of the pixel n
Error data ED is not substantially added to D, and error data EN to be added to pixel n + 1 (= 12) is created. If the image data of the pixel n + 1 is different from the pixel n by a predetermined value or more, as described above, the selector 2
3 selects the error data ME2, the error data EN held in the error data holding circuit 25 is the pixel n + 1
Is not added to the image data GD. On the other hand, pixel n + 1
Is the same as the pixel n, the selector 2
3, the error data EN held in the error data holding circuit 25 is selected and added to the image data GD.

Processing Example 3: Next, the pixel pattern shown in FIG. 9C is a case of a checkered pattern using two pixels. In this case, when the processing of the processing example 2 is performed, the pixel n + 1
Carry may occur, and a specific pattern may occur. Therefore, in the case of the processing example 2, the pixel n
When +1 (12) is held in the latch circuit 21, the image data determination circuit 33 detects whether the image data GD of the pixel n + 2 is different from the image data GD of the pixel n + 1 by a predetermined width or more. If they are the same, the processing of processing example 2 is performed. If the width is equal to or larger than the predetermined width, the pixel pattern is determined to be the pixel pattern of FIG. 9C, and the error data GDE of the image data GD is masked by the control signal MSK. Accordingly, the arithmetic circuit 22 performs addition with the error data EN held in the error data holding circuit 25, but no carry occurs because the error data GDE is "0". That is, pixel n +
This is equivalent to the fact that the error data EN has not been added to one image data GD. At the time of the next pixel n + 2, the same error data EN is held in the error data holding circuit 25. However, since the processing of the pixel n + 2 is the above-described processing example 2, it is created for the pixel n + 1 after all. Error data M
E2 will be reset without being used. FIG.
0 indicates a display pattern based on the image data sequence shown in FIG. In FIG. 10, the pixel numbers are assigned in the horizontal direction and the line numbers are assigned in the vertical direction. As shown in FIG. 10A, in each line, error data “1” continues up to pixel position “16”, and error data “8” continues from pixel position “17”. FIG. 10B shows a reset pixel position in such a pattern. In FIG. 10B, a reset pixel position based on the reset pattern selected by the reset control circuit 27 is indicated by an asterisk. That is, the first pattern generated by the reset pattern generation circuit 37 up to the pixel position “16” is the second pattern generated by the reset pattern generation circuit 38 after the pixel position “17”. Further, when resetting is performed at the change time point of the image data GD, that is, at the edge, as in the related art, the resetting is forcibly performed at the pixel position “17” as indicated by the + mark.

FIG. 11 shows the positions of carry-up pixels when the reset pattern shown in FIG. 10B and the forced reset are used in combination, with # marks. As shown in FIG. 11A, the carry position after the pixel position “17” has many portions that match each other, and the original carry by the second reset pattern is performed. The pixel position is "32" or later. Therefore, the image quality is deteriorated in the display portion at the pixel position “31” from the pixel position “17” which is the boundary of the image.

FIG. 11B shows a display pattern based on the processing example 1 described above. As described above, in the processing example 1,
The reset is performed at the pixel position indicated by * in FIG. 10B (the reset is not performed at the pixel indicated by +), and the error data ED after the pixel position “17” is created. As shown in FIG. 11 (b), the carry is made based on the original reset pattern from the pixel position "17" and thereafter. Therefore, the carry position is uniform without being disturbed.
A decrease in display image quality can be prevented.

According to the processing example 2, even if the error data is created, the error data is not added to the image data GD at the pixel position "17", so that the carry at the pixel position "17" is not performed. That is, the # mark shown at the pixel position "17" of the pattern shown in FIG. Therefore, the same effect can be achieved also in the case of the processing example 2.

[0048]

As described above, according to the present invention, in a pseudo gradation processing apparatus using an error diffusion processing method for sequentially adding error data to adjacent pixels, the influence of an error in left image data is reduced by a predetermined number of pixels. The reset pattern for convergence within is set according to the error data, and is selected, so that it does not adversely affect the image data on the right side, and has a one-pixel checker pattern and a two-pixel checker pattern. In the case of a pattern, the created error data ME1 and ME
Since 2 is not used and there is no carry, it is possible to prevent the occurrence of a specific pattern by error diffusion. And FIG.
In the pixel pattern described in (a), when the change of the image data GD is equal to or less than a predetermined value, the error data ME1 created is added to the image data GD of the pixel immediately after the change, and when the change is equal to or more than a predetermined value. Since the created pixel data ME2 is added to the image data GD of the next pixel immediately after the change, the image quality after the edge of the screen is improved. Therefore, the effect is remarkable especially when a flat screen is created by a computer.

[Brief description of the drawings]

FIG. 1 is a block diagram showing an embodiment of the present invention.

FIG. 2 is a block diagram showing a detailed configuration of some of the blocks shown in FIG.

FIG. 3 shows a detailed configuration of some blocks shown in FIG. 2;

FIG. 4 is a schematic diagram showing a first reset pattern and a screen.

FIG. 5 is a schematic diagram showing a second reset pattern and a screen.

FIG. 6 is a schematic diagram showing a third reset pattern and a screen.

FIG. 7 is a schematic diagram showing a fourth reset pattern and a screen.

FIG. 8 is a schematic diagram showing a fifth reset pattern and a screen.

FIG. 9 is a schematic diagram of a pixel for explaining the embodiment shown in FIGS. 1, 2 and 3;

FIG. 10 is a schematic diagram showing a data pattern and a reset pattern for explaining the effect of the display example shown in FIG. 9A.

FIG. 11 is a schematic diagram showing a conventional display pattern based on the pattern shown in FIG. 10 and a display pattern of the present embodiment.

FIG. 12 is a block diagram showing a conventional example.

[Explanation of symbols]

 Reference Signs List 21 latch circuit 22 arithmetic circuit 23 selector 24 latch circuit 25 error data holding circuit 26 reset circuit 27 reset control circuit 28 error data creation circuit 29, 30 addition circuit 31, 32 multiplication circuit 33 image data discrimination circuit 34 mask circuit

──────────────────────────────────────────────────続 き Continued on the front page (72) Inventor Makoto Kitagawa 2-5-5 Keihanhondori, Moriguchi-shi, Osaka Sanyo Electric Co., Ltd. (72) Inventor Yusuke Tsutsui 2-5-1 Keihanhondori, Moriguchi-shi, Osaka No. 5 Sanyo Electric Co., Ltd. (72) Inventor Hisao Uehara 2-5-5 Keihanhondori, Moriguchi-shi, Osaka Sanyo Electric Co., Ltd. (56) References JP 5-91328 (JP, A) JP JP-A-7-123259 (JP, A) JP-A-6-138858 (JP, A) JP-A-8-1001663 (JP, A) JP-A-7-140924 (JP, A) JP-A-6-301364 (JP) , A) (58) Fields investigated (Int. Cl. ⁷ , DB name) G09G 3/00-5/42 G02F 1/133 505-580 H04N 1/40 G06T 5/00

Claims (5)

(57) [Claims] An arithmetic means for adding accumulated error data to each image data supplied for each pixel, and a predetermined number of lower-order bits of processed image data obtained as a result of the arithmetic means are added to the next pixel. Error data holding means for accumulating and holding as error data for performing error diffusion processing for diffusing the error data to other pixels, thereby displaying image display data having a smaller number of bits than the number of bits of the original image data. A pseudo-grayscale processing device for adding grayscale information equal to or more than the number of grayscales that can be displayed by the image display data, wherein the pseudograyscale processing device corresponds to a change in the image data supplied for each pixel and has based on the error data, as the image data after the change is continuous from the previous change
Assuming that it is added to the image data of the pixel immediately after the change
Error data, and the error data is selected by the selection means.
The above calculation is performed on the pixel data of the pixel immediately after the change.
Means, and the data is added and held in the error data holding means.
Processing that is the result of the arithmetic means
Error data creating means for creating error data of a predetermined number of lower bits of the physical image data, and detecting a change in the image data, and selecting a signal according to the change
The basis, and a said error data creating means selection means for supplying to said calculating means instead of the error data held error data generated in the error data storage means by, after the change of the image data is changed before A pseudo-gradation processing device which eliminates the influence of the error data and enables error diffusion processing based on the created error data. 2. An arithmetic unit for adding error data accumulated to each image data supplied for each pixel, and a predetermined number of lower-order bits of the processed image data obtained as a result of the arithmetic unit are used as an error of the next pixel. Error data holding means for accumulating and holding the data as data, and performing error diffusion processing for diffusing the error data to other pixels, thereby displaying the image display data having a smaller number of bits than the number of bits of the image data. In a pseudo gradation processing apparatus for adding gradation information equal to or more than the number of gradations that can be displayed by data, reset means for resetting error data of the error data holding means, and error decoding means for decoding error data of the image data And a plurality of reset patterns for determining a pixel position at which resetting is performed. And reset control means for controlling the reset means based on the reset pattern, and a distance between a reset pixel position to be reset according to the reset pattern selected by the reset control means and a pixel position of the supplied image data. A pixel distance data generating means for generating pixel distance data indicating a distance, and assuming that the changed image data has been continuous before the change, the pixel data is added to the image data of the pixel immediately after the change.
Error data to be created, and the error data is
Therefore, the pixel data of the pixel selected and
The addition is performed by using the arithmetic means, and the error data is stored in the error data holding means.
The result of said arithmetic means being data to be retained
Error data generating means for generating error data of a predetermined number of lower-order bits of the processed image data, and converting the error data generated by the error data generating means to error data held in the error data holding means. A pseudo-gradation processing device, comprising: a selection unit that supplies the error data before and after the change of the image data, thereby enabling an error diffusion process based on the created error data. 3. The error data creating means creates error data to be added to the image data of the pixel immediately after the change.
3. The pseudo gradation processing apparatus according to claim 1, wherein the error data is selected by the selection unit and added to the image data of the pixel immediately after the change. 4. The error data to be added to the image data of the pixel immediately after the change is not added to the image data of the pixel immediately after the change, but should be added to the image data of the pixel following the pixel immediately after the change. 4. The pseudo gradation processing apparatus according to claim 3, wherein error data is created by said error data creating means, and the created error data is output by said arithmetic means and held in said error data holding means. 5. The error data to be added to the image data of the pixel next to the pixel immediately after the change held in the error data holding means, if the subsequent pixels are discontinuous, the error data is set by the selection means. 5. The pseudo gradation processing apparatus according to claim 4, wherein the error data of the data holding means is not selected, the error data is not added, and the error data to be added to the further succeeding pixels is selected.