JP2975823B2 - Pseudo gradation processor - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a pseudo-gradation processing device for simulating the display of a predetermined number of bits or more in a display device which performs display using image display data of predetermined bits. In other words, the present invention relates to a pseudo gradation processing apparatus for further increasing the gradation display of an LCD display device by a digital driver of a predetermined bit and performing a display close to an original image.

[0002]

2. Description of the Related Art In recent years, high-definition color LCD displays for multimedia office automation have been developed. The color LCD has a built-in 3-bit or 4-bit digital driver for each of R, G, and B colors. For example,
Color LCD with 3-bit digital driver
A display of eight gradations for each color is possible, and a total of 512 colors can be displayed. However, this is sufficient when used simply as a monitor for OA, but is insufficient for displaying video such as moving images and still images for multimedia, and further increase in gradation is desired. Was rare.

Therefore, a method has been proposed in which a component which cannot be displayed by one pixel is diffused into an adjacent pixel around the same screen frame (error diffusion within a frame) to thereby increase the number of gray levels in a pseudo manner. FIG. 4 shows a pseudo-gradation processing device using one of the methods, in which lower-order bits of image data of one pixel that are not displayed are held as error data,
This is a device that performs pseudo gradation processing by adding the image data to the image data of the next pixel, and shows a processing device for one-color image data. In FIG. 4, a latch circuit 11 latches 6-bit original image data SD sequentially applied in synchronization with a dot clock DK and outputs the same to an arithmetic circuit 12. The arithmetic circuit 12 includes the original image data SD and the error data holding circuit 1
The error data EI output from 3 is added to generate 6-bit corrected image data. Error data holding circuit 13
Represents the lower two bits of the corrected image data as the dot clock D
K, and output to the arithmetic circuit 12 when the original image data SD of the next pixel is latched by the latch circuit 11. The upper 4 bits of the corrected image data are output as image display data GD and applied to the output latch circuit 14. By performing display using the 4-bit image display data GD, lower 2-bit error data is sequentially diffused to adjacent pixels, so that an intermediate gradation is displayed by averaging the luminance of a plurality of pixels. become.

For example, if the original image data SD is "10001"
0 ", and when the original image data SD is a continuous pixel, simply displaying the upper 4 bits is" 100 ".
Since all pixels are displayed by “0”, the lower 2
The gradation of bit “10” is not displayed. However, in the case of the pseudo gradation processing apparatus of FIG.
The error data EI “00” is added to “100010” to generate corrected image data “100010”, the lower bit “10” of which is held in the error data holding circuit 13 as the error data EI, and the upper four bits “10”. Although "1000" is output as the image display data GD, the error data EI "10" is added to the next original image data SD, so that the corrected image data is "100100" and the error data EI is "00". Will be retained. By repeating this operation, “1000” and “1001” are alternately displayed for each pixel, so that the display of half gradation is performed by the two pixels.
The 階 調 gradation represented by the least significant bit of D is represented by four pixels.

[0005] Therefore, by applying the pseudo gradation processing to each of the R, G, and B colors, the gradation of each color can be expressed as 64 gradations, which is the same as the original image data SD.

[0006]

In the above-described pseudo-gradation processing device, the error diffusion process is a horizontal addition process, so that the influence of the left image is transmitted to the right image, and consequently the image display data is changed. Will have an effect. If there is movement of the displayed image or if the shading changes, this pseudo-gradation processing can achieve a significant improvement in image quality, but the shading of the displayed image, such as the sky or a human face, can be reduced. When flat, the effect of the error data appears to be noticeable to the eye,
The display image quality is degraded.

For example, when a natural image is displayed on a personal computer,
When the mouse cursor crawls on the screen, the mouse cursor appears to have a tail. In other words, when the mouse cursor is displayed in a flat image of light and shade, an error of the image data for displaying the mouse cursor appears on the far right side, and the image changes there. For example, in the state where the pixels of the original image data “010000” continue, for the original image data for displaying the mouse cursor,
When the value of a certain pixel becomes “100111”, the error data becomes “11”, which is sequentially added and held as error data, so that the image changes to the far right side far away. Therefore, when the mouse cursor moves on the screen, the change in the image also moves, so that the image looks as if it were trailing.

In a flat image of light and shade,
Since the carry due to the addition of the error data occurs periodically, the position of the brighter pixel and the position of the darker pixel are
Since the coincidence occurs in the adjacent horizontal scanning lines and also in each frame, a vertical line appears on the display screen, causing deterioration in image quality. That is, for example, “10000
When the original image data of “1” is continuous, the result of the addition processing of the first pixel is “100001” and the error data is “01”, and the addition of the next pixel is “100010” and the error data is “10”. , The next pixel addition is "1000
11 ", error data" 11 ", and further addition of the next pixel result in" 100100 "and error data" 00 ", and this is repeated. Therefore, in this case, a carry to the upper 4 bits of image display data occurs periodically in a 4-pixel cycle.

[0009]

SUMMARY OF THE INVENTION The present invention has been made in view of the above points, and has an arithmetic means for adding error data to each original image data supplied for each pixel, and a result of the arithmetic means. Error data holding means for holding a predetermined number of lower-order bits of the obtained processed image data as the next error data, and displaying the image display data with a bit number smaller than the bit number of the original image data by the image display data. A pseudo-gray-scale processing device for adding gray-scale information equal to or more than a possible number of gray levels, wherein a flat image detecting means for detecting that a change in an image is flat by comparing the original image data for each pixel; Reset means for resetting the error data of the error data holding means for each predetermined number of pixels according to the detection output of the flat image detection means, and the influence of the error data will be added later. A pseudo gradation processing device to prevent the left.

[0010] Further, based on the output of the flat image detecting means, reset timing generating means for driving the reset means for each pixel number ^{equal to} an integral multiple of the numerical value (2 ⁿ ) represented by the bit number (n) of the error data is provided. By preparing
The effect of the error data converges within a certain number of pixels. Further, the reset timing generating means varies the reset timing for each horizontal scanning line, and the reset timing generating means varies the reset timing for each horizontal scanning line,
By making the reset timing different for each frame even in the same horizontal scanning line, the positions where the carry occurs are dispersed and the deterioration of the image quality can be prevented.

[0011]

According to the above-described means, the flat image detecting means determines whether the original image data applied to each pixel is one pixel before and two pixels before.
By comparing the original image data with that before the pixel, the change width of the original image data is checked, and when the change of the data is within a predetermined value, the image is recognized as a flat screen and a detection output is generated. If this detection output does not occur, it is determined that the density of the image is not flat, and normal pseudo gradation processing is performed. That is,
Error data is added to the original image data, the upper predetermined bits of the addition result are output as image display data, and the lower predetermined bits are held as error data for addition to the next original image data.

On the other hand, when a detection output is generated from the flat image detection means, the reset means resets the error data of the error data holding means at a predetermined pixel cycle. As a result, the error data up to that point does not affect subsequent pixels, and the image quality of a flat image is improved.
Further, by changing the position of the pixel to be reset for each adjacent horizontal scanning line by the reset timing generating means, and changing the position of the pixel to be reset for each frame even for the same horizontal scanning line, the image display data can be obtained. Since the position of the carry-up pixel varies throughout the screen, it is possible to prevent the occurrence of vertical lines and the like, and to improve the image quality. Further, the result of the pseudo gradation process can be effectively represented.

[0013]

FIG. 1 is a block diagram of a pseudo gradation processing apparatus showing an embodiment of the present invention. The pseudo gradation processing apparatus is provided between an output section of original image data of each color of R, G and B and an LCD driver of each color. This is a device that processes 6-bit original image data SD and outputs it as 4-bit image display data GD to a 4-bit input LCD driver.

In the pseudo gradation processing apparatus shown in FIG. 1, the latch circuit 21 receives the input signal in synchronization with the dot clock DK.
A circuit for sequentially holding original image data SD of bits,
Specifically, it is composed of six D-FFs. Arithmetic circuit 2
Reference numeral 2 denotes a circuit for adding the original image data SD output from the latch circuit 21 and the 2-bit error data EI of one pixel before output from the error data holding circuit 24. Of the 6-bit output corrected image data of the arithmetic circuit 22, the upper 4 bits are latched by the latch circuit 25 by the dot clock DK.
And supplied to the 4-bit input digital driver of the LCD as image display data GD. Latch circuit 25
Is composed of four D-FFs.

On the other hand, the lower 2 bits of the 6-bit output corrected image data of the arithmetic circuit 22 are supplied as error data EI to an error data holding circuit 24 via a reset circuit 23. The reset circuit 23 switches between the operation of supplying the error data EI from the arithmetic circuit 22 to the error data holding circuit 24 as it is and the operation of supplying the data “00” by the output RES of the reset timing generation circuit 27. The error data holding circuit 24 is composed of two D-FFs, and the holding operation is controlled by the dot clock DK.

The flat image detecting circuit 26, based on the original image data SD sent in synchronization with the dot clock DK, the original image data SD one pixel before and two pixels before and the image data SD of the currently supplied pixel Are compared, and it is detected that the amount of change is equal to or less than a predetermined value, and it is detected that the image has a flat shading. Specifically, a latch circuit 31 that holds the original image data SD output from the latch circuit 21 by the dot clock DK, a latch circuit 32 that holds the output of the latch circuit 31 by the dot clock DK, A comparison circuit 2 for comparing each of the output of C.32 with the supplied original image data SD
8 and 29, and an AND circuit 30 for calculating the logical product of the outputs of the comparison circuits 28 and 29.

Here, each of the latch circuits 31 and 32 is constituted by six D-FFs, and constitutes a two-stage shift register for each bit. Therefore, each time the dot clock DK is input, the original image data SD is sequentially shifted, so that the latch circuit 31 holds the original image data SD one pixel before, and the latch circuit 32 stores the original image data SD two pixels before. Data SD is held. The comparison circuit 28 sets the detection output to “H” when the difference between the original image data SD and the latch circuit 31 is within a predetermined value, and the comparison circuit 29 sets the detection output when the difference between the original image data SD and the latch circuit 32 is within a predetermined value. The detection output is set to “H”. Therefore, the AND circuit 30 outputs the detection output DET of “H” when the difference between the original image data SD one pixel before and two pixels before and the current original image data SD are both within a predetermined value. In the above description, the 6 bits of the original image data SD are compared, but the upper 5 bits or 4 bits may be compared depending on the allowable range of the difference.

The reset timing generating circuit 27 includes a dot clock DK, a horizontal synchronizing signal H _{SY NC} , and a vertical synchronizing signal V
_This is a circuit that generates a reset signal RES for operating the reset circuit 23 by _SYNC . When the output of the flat image detection circuit 26 is “H”, the timing of a dot cycle for resetting error data is determined.
The timing is generated so that the timing of resetting is different for each horizontal scanning line and each frame.

Next, the operation of FIG. 1 will be described. When the original image data SD _(N) of the _Nth pixel is held in the latch circuit 21, the arithmetic circuit 22 calculates the 2-bit error data EI _(N-1) one pixel before and the original image data SD _(N) . Add and output. When a carry occurs as a result of this addition, the arithmetic circuit 22
Outputs the maximum value, that is, data in which all 6 bits are “1”. At this time, the latch circuit 31 of the flat image detection circuit 26 holds the original image data SD _(N−1) one pixel before, and the latch circuit 32 stores the original image data SD _(N−1) two pixels before.
_(N-2) is held. As a result of the comparison between the comparison circuits 28 and 29, when the detection output DET of the AND circuit 30 is “L”, the output RES of the reset timing generation circuit 27 is “L”.
Are supplied to the error data holding circuit 24 as error data EI _(N) . The upper 4 bits of the output of the arithmetic circuit 22 are output to the latch circuit 25 as image display data GD _(N) .

Next, when the original image data SD _{(N + 1)} is applied in synchronization with the dot clock DK, the original image data SD _{(N + 1)} is applied.
_{(N + 1)} is held in the latch circuit 21. At the same time, the error data EI _(N) output from the arithmetic circuit 22 is held in the error data holding circuit 24 and the image display data GD _(N) is held in the latch circuit 25 and output by the dot clock DK. Further, the original image data SD outputted from the latch circuit 21 _(N) is held in the latch circuit 31 of the flat screen detection circuit 26, the original image data SD _(N held in the latch circuit 31 to latch circuit 32 _-1) is retained. Hereinafter, the original image data SD _{(N + 1)}
Is performed.

When the original image data SD _(N) is held in the latch circuit 21, the flat image detection circuit 26
Becomes high when the reset timing generation circuit 27 generates the reset signal RES, the reset signal RES becomes high.
, The reset circuit 23 becomes the arithmetic circuit 22
The clear data “00” is output to the error data holding circuit 24 in place of the error data EI _(N) output from.
Therefore, when the next dot clock DK arrives, "00" is held in the error data holding circuit 24, and the accumulation of the error data is cleared at this point.

Next, the configuration and operation of the reset timing generation circuit 27 will be described. As shown in FIG. 2, the reset timing generation circuit 27 includes a dot counter 33 for counting the dot clock DK, an H counter 34 for counting the horizontal synchronization signal H _SYNC , a V counter 35 for counting the vertical synchronization signal V _SYNC , It comprises a decoder 36 for decoding the output of each of the counters 33, 34, 35.
The dot counter 33 is configured to be reset by the vertical synchronization signal _HSYNC , and counts the number of pixels in one horizontal scanning line. The H counter 34 is configured to be reset by the vertical synchronization signal _VSYNC , and counts the number of lines in one frame. The V counter 35 counts the number of frames.

The decoder 36 includes counters 33, 34,
A timing for resetting the error data EI is generated based on the count value of 35, and a reset signal RES is output when the detection output DET of the flat screen detection circuit 26 is "H" at the timing. In the case of this embodiment, since the error data is 2 bits, the minimum value of 2 bits “0”
The carry occurs at every 4 pixels at "1". Therefore, if the reset is performed at an integral multiple of 2 ⁿ (n is the number of bits of the error data), the error data can be cleared without impairing the gradation display of the error data.

However, if reset is always performed at the same position in each horizontal scanning line and each frame, a carry-up position occurs in the same pixel, and this is displayed as a vertical line. Therefore, the decoder 36 performs decoding so that reset is performed at a different pixel position for each horizontal scanning line and reset is performed at a different pixel position for each frame.

Specifically, a reset position and a reset interval as shown in FIG. 3 are set. In FIG. 3, a number in parentheses indicating a pixel indicates a pixel number. In the case of an odd-numbered frame, at line “0”, pixels (3), (7),.
Reset at the timing of (4m + 3) (m = 0, 1, 2, 3,...), Pixels (1), (5) in line "1"
... Reset at the timing of (4m + 1), pixel (2) at line “2”, (6)... Reset at the timing of (4m + 2), pixel (0) at line “3”,
(4) Reset is performed at the timing of (4m).
Subsequent lines are a repetition of line “0” to line “3”.

In the case of an even frame, at line "0",
At the timing of the pixels (0), (4)... (4m), and at the line “1”, the pixels (2), (6)... (4m + 2)
At the timing of the line “2”, the pixels (1) and (5)
... at timing (4m + 1), line "3"
Reset is performed at the timing of pixels (3), (7)... (4m + 3). Subsequent lines are similarly repeated from line “0” to line “3”.

In order to realize the reset timing shown in FIG. 3, the decoder 36 sets the count value of the dot counter 33 to
4m, 4m + 1, 4m + 2, and 4m + 3, respectively. The output of these decode blocks is counted by the H counter 34 as 4h, 4h.
+1, 4h + 2, 4h + 3 (h = 0, 1, 2, 3,...
The selection is made by a combination of a decode output for detecting ()) and a decode output for detecting that the count value of the V counter 35 is an odd number or an even number. The decoded output is ANDed with the detection output DET of the flat screen detection circuit 26 to be output as a reset signal RES.

As described above, by making the reset timing different for each line and making the reset timing different for every two frames, the reset timing is uniformly distributed on the display screen. No image is displayed, and deterioration of image quality can be prevented. In the example of FIG. 3, the reset pattern is changed between the odd-numbered frame and the even-numbered frame. However, the reset pattern may be changed every four frames, and may be repeated every four frames.

[0029]

As described above, according to the present invention, in a pseudo gradation processing apparatus using an error diffusion processing method of sequentially adding error data to adjacent pixels, the influence of an error in left image data is a predetermined number of pixels. It has the advantage of not adversely affecting the image data on the right because it converges within the range. Also, for a flat image of halftone, accurate error diffusion processing can be guaranteed, so that correct gradation performance can be obtained and moving images can be displayed. For an image or a random image, it is possible to prevent the original performance degradation of the gradation display due to the reset of the error. Further, by dispersing the reset timing in a flat image, and further dispersing the timing between frames, a change in luminance due to a carry appearing on the screen is dispersed, and deterioration of the image quality in the flat image can be prevented. is there.

[Brief description of the drawings]

FIG. 1 is a block diagram showing an embodiment of the present invention.

FIG. 2 is a block diagram showing a configuration of a partial block shown in FIG.

FIG. 3 is a diagram for explaining an operation realized by the configuration shown in FIG. 2;

FIG. 4 is a block diagram showing a conventional technique.

[Explanation of symbols]

 Reference Signs List 21 latch circuit 22 arithmetic circuit 23 reset circuit 24 error data holding circuit 25 latch circuit 26 flat image detection circuit 27 reset timing generation circuit

──────────────────────────────────────────────────続 き Continued on the front page (58) Field surveyed (Int.Cl. ⁶ , DB name) G09G 5/02 G06T 5/00 G09G 5/36 H04N 1/405

Claims (4)

(57) [Claims] An arithmetic unit for adding error data to each original image data supplied for each pixel, and a predetermined number of lower bits of processed image data obtained as a result of the arithmetic unit are held as next error data. Error data holding means, a pseudo-gray-scale processing device for adding to the image display data of the number of bits smaller than the number of bits of the original image data the gradation information of the number of gradations that can be displayed by the image display data or more, Flat image detecting means for detecting that the change of the image is flat by comparing the original image data for each pixel; and detecting the error data of the error data holding means by a detection output of the flat image detecting means for a predetermined pixel. A pseudo-gradation processing apparatus comprising reset means for resetting every number, and preventing the influence of the error data from remaining afterwards. 2. A reset timing generating means for driving the reset means for each pixel number which is an integral multiple of a numerical value (2 ⁿ ) represented by the bit number (n) of the error data based on an output of the flat image detecting means. The pseudo gradation processing device according to claim 1, further comprising: 3. The pseudo gradation processing device according to claim 2, wherein said reset timing generating means makes reset timing different for each horizontal scanning line. 4. The reset timing generating means according to claim 2, wherein the reset timing is made different for each horizontal scanning line, and the reset timing is made different for each frame even in the same horizontal scanning line. Pseudo gradation processing device.