JP2820036B2 - Display device gradation correction circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a gradation correction circuit for a display device for correcting display characteristics which are inverted with respect to an input luminance level.

[0002]

2. Description of the Related Art Recently, as a thin and lightweight display device, P
Display devices such as DPs (plasma display panels) and LCDs have attracted attention. The driving method of the PDP or the like is completely different from the conventional CRT driving method, and is a direct driving method using a digitized video input signal. Therefore, the luminance gradation emitted from the panel surface is determined by the number of bits of the signal to be handled.

[0003] In the AC type PDP, sufficient characteristics are obtained with respect to luminance and life, but with respect to gradation display, an address / display separation type driving method (ADS subfield method).
Has been proposed. Explaining the driving sequence of this method, one frame is composed of 8 pixels whose relative ratio of luminance is 1, 2, 4, 8, 16, 32, 64, 128.
It is composed of a number of subfields, and displays 256 gradations by combining the luminance of eight screens. Each subfield is composed of an address period in which data for one refreshed screen is written and a sustain period for determining a luminance level of the subfield. In the address period, first, wall charges are initially formed on each pixel at the same time for the entire screen, and then a sustain pulse is applied to the entire screen to perform display. The brightness of the subfield is proportional to the number of sustain pulses and is set to a predetermined brightness. In this way, 256 gradation display is realized.

In the above-described AC driving method, as the number of gradations increases, the number of bits in an address period as a preparation period for lighting and emitting a panel within one frame period increases. The period becomes relatively short, and the maximum luminance decreases.

As described above, since the luminance gradation emitted from the panel surface is determined by the number of bits of the signal to be handled, the picture quality is improved by increasing the number of bits of the signal to be handled, but the emission luminance is reduced, and conversely. If the number of bits of the signal to be handled is reduced, the light emission luminance increases, but the gradation display decreases and the image quality deteriorates.

[0006] In the case of a general video signal, an error diffusion process is performed to minimize the shading error between the input signal and the emission luminance while reducing the number of bits of the output drive signal from the number of bits of the input signal. This is a process for expressing a pseudo-halftone, and is used when expressing grayscale with a small number of gradations.

Therefore, an error diffusion processing circuit is conventionally used, and as a result, as shown in FIG. 5, the output luminance is instantaneously represented by four bits like a solid-line staircase as shown in FIG. In spite of the fact that the levels are output, in fact, the stepwise upper and lower emission luminance levels of the solid line are alternately output at a predetermined ratio, so that they are recognized in an averaged state, and y = x is the corrected luminance line.

[0008]

In general, the display becomes higher stepwise as shown by the solid line in FIG. 5, and the input level of the drive signal is brighter when N + 1 than N. However, in a panel such as a PDP having a digital drive method developed in recent years, depending on display data,
In some cases, N + 1 is displayed darker than N.

For example, as shown in FIG.
Inversion starts from the 28th bit, and 144 bits after 16 bits
Even the bits are still inverted from the previous level, and finally become higher at 160 bits than the previous level. Therefore, 32 bits from 128 bits to 160 bits are the inverted section, and the interval is darker than the previous level. Will be done.

However, in the conventional circuit, the input level is N
Since the processing on the circuit is performed on the premise that N + 1 is displayed brighter than that of N + 1, when the display characteristics are inverted as shown in FIG. 6, the portion that should be displayed brightly is displayed darkly. Therefore, there is a problem that a sense of incongruity occurs in the image, and no measures have been taken against this problem.

According to the present invention, by adding a simple circuit, even when the display characteristics are inverted with respect to the input luminance level, the input level N + 1 is always displayed brighter than the input level N. It is an object of the present invention to provide a gradation correction circuit for performing correction.

[0012]

SUMMARY OF THE INVENTION The present invention relates to a display apparatus in which a display panel is directly driven by a digitized video input signal to display an image. Signal 13
, A level comparison circuit 14 for comparing data from a new video data input terminal 10 with the signal 12 of the inversion start level, and opening / closing control based on the output of the level comparison circuit 14. A gate circuit 15 for outputting the signal 13 in the inversion section, and an addition circuit 16 for adding the data of the new video data input terminal 10 and the signal 13 in the inversion section. , A display number counter 18 for each bit, a display area ratio operation circuit 19, a memory 20, a luminance deviation amount operation circuit 21, and a luminance comparison circuit 22.

[0013]

When video data is input, the display number counter 18 for each bit counts the display number of each bit in one frame. Next, the display area ratio calculation circuit 19 obtains the display area ratio, and the brightness deviation calculation circuit 21 calculates the brightness deviation of each bit based on the obtained display area ratio and the data in the memory 20.

The luminance deviation amounts are sequentially compared by the luminance comparing circuit 22. If the data after the previous data is smaller than the previous data, that is, if the so-called inversion phenomenon occurs, the signal (B) 12 of the inversion start level and the inversion section From the signal 13 of FIG. From the video data input terminal 10, new data A one frame later is sequentially input to the level comparison circuit 14. The levels A and B are compared by the level comparison circuit 14.

If the operation result of the level comparison circuit 14 satisfies a certain section A ≧ B, the output of the signal 13 in the inversion section is sent to the addition circuit 16 and added to the input signal of the video data input terminal 10 to be shifted. The output becomes the same level as the luminance level of the driven input signal. Hereinafter, similarly, the corrected emission luminance characteristic is sent from the output terminal 17 to the error diffusion processing circuit, where the error diffusion processing is performed, and is supplied to a display such as a PDP.

[0016]

An embodiment of the present invention will be described below with reference to the drawings. In FIG. 1, reference numeral 10 denotes a video data input terminal from a video source. The output side of the video data input terminal 10 branches into three, and is connected to the input side of the emission luminance characteristic acquisition circuit 11, one input side of the level comparison circuit 14, and one input side of the addition circuit 16, respectively. I have.

The signal (B) 12 of the inversion start level of the light emission luminance characteristic acquisition circuit 11 is applied to the other input side of the level comparison circuit 14, and the output side of the level comparison circuit 14 and the light emission luminance characteristic acquisition circuit The signal 13 in the inversion section of the circuit 11 is applied to the input side of the gate circuit 15, and the output side of the gate circuit 15 is connected to the other input side of the adder circuit 16. Output terminal 17 of this adder circuit 16
Are PDP, L via an error diffusion processing circuit (not shown)
Connected to a display such as a CD.

The details of the emission luminance characteristic acquisition circuit 11 are as follows.
As shown in FIG. 2, a display number counter 18 for each bit for counting a plurality of (M) bits of video data in a memory corresponding to each bit, and a calculation of a display area ratio by dividing the number of display dots by the total number of dots. And a memory 2 comprising a look-up table in which characteristics of a luminance deviation with respect to a display area ratio of a display element are stored in advance.
0, a luminance deviation amount calculating circuit 21 for calculating a luminance deviation of each bit, and a luminance comparing circuit 22 for comparing the luminance of each level and outputting a signal (B) 12 of an inversion start level and a signal 13 of an inversion section. Become.

In the above configuration, when the video data (A) is input from the video data input terminal 10 to the emission luminance characteristic acquisition circuit 11, the emission luminance characteristic acquisition circuit 11 obtains the emission luminance characteristic for each frame. The obtained light emission luminance characteristic is transmitted to the error diffusion processing circuit during the vertical synchronization period of the video signal.

More specifically, in FIG. 2, when M bits of video data are input from the video data input terminal 10, each bit is displayed by a display number counter 18 comprising M counters corresponding to each bit. Count the number of displays in the frame. Next, the display area ratio calculation circuit 19 calculates "display dot number (output of the display number counter 18 of each bit) ÷ total number of dots" to obtain a display area ratio. The display area ratio obtained by the display area ratio calculation circuit 19 and the memory 2 comprising a look-up table
Based on the data of 0, the luminance deviation calculation circuit 21 calculates the luminance deviation of each bit.

A display such as a PDP or LCD has a characteristic relationship between a display area ratio and a luminance deviation as shown by a chain line or a dotted line in FIG. 3 (a horizontal line shown by a solid line is an ideal characteristic). Line). In the case of M-bit display, an arbitrary level n is represented by B0, B1, B2,.
Then, the calculation of the luminance Yn of each level is performed by the following equation. α is linear data of y = x. The calculation of the luminance deviation amount of each level is performed by the luminance deviation amount calculation circuit 21 according to the following equation.

The luminance deviation amounts obtained in this way are sequentially compared by the luminance comparing circuit 22. If the data after the previous data is smaller, that is, if the so-called reversal phenomenon occurs, the reversal start level signal 12 and the reversal start level signal 12 are compared. The signal 13 in the inversion section is output. In the case where an inversion phenomenon like the dotted line characteristic in FIG. 4 (similar to FIG. 6) occurs as an example, the inversion start level signal 12 of the emission luminance characteristic acquisition circuit 11 starts inversion at the 128th bit. Since it continues up to 159 bits,
The signal B of each level is output, and the level comparison circuit 1
4 is input.

From the video data input terminal 10, new data A one frame later is sequentially input to the level comparison circuit 14. The levels of A and B correspond to the level comparison circuit 14
Are compared. Up to 127 bits, A <B, and there is no output from the level comparison circuit 14. Therefore, the gate of the gate circuit 15 is not opened, and only new data A is output to the output terminal 17.
Output to

If the operation result of the level comparison circuit 14 is 1
When A ≧ B from 28 bits to 143 bits, the gate of the gate circuit 15 is opened by the output of the level comparison circuit 14, and 32 bits of the output 13 of the signal 13 in the inversion section of the emission luminance characteristic acquisition circuit 11 are added to the addition circuit 16. Sent to
It is added to the input signal of the video data input terminal 10.
That is, for 128 bits, 32 bits are added to 1 bit.
The output is the same level as the luminance level of the 60-bit drive input signal.

In the same manner, in 144 bits, the luminance level is the same as the 176-bit luminance level in the previous frame, and in 160 bits, the luminance level is the same as the 192-bit luminance level in the previous frame,... This is the state (solid line in FIG. 4). The light emission luminance characteristics thus corrected are sent from the output terminal 17 to the error diffusion processing circuit, where the error diffusion processing is performed, and supplied to a display such as a PDP or LCD.

[0026]

【The invention's effect】

(1) PDP with digital drive method developed in recent years,
On a panel such as an LCD, depending on display data, the input level may be darker when the input level is N + 1 than when the display level is N. However, according to the present invention, the input level is shifted by the inversion interval. Even if there is an input level, N + 1 is always displayed brighter than N. Therefore, the image does not feel uncomfortable.

(2) A light emission luminance characteristic acquisition circuit 11, a level comparison circuit 14, a gate circuit 15, and an addition circuit 16 are added at the preceding stage of the error diffusion processing circuit. can do.

[Brief description of the drawings]

FIG. 1 is a block diagram showing one embodiment of a gradation correction circuit of a display device according to the present invention.

FIG. 2 is a detailed block diagram of a light emission luminance characteristic acquisition circuit 11 in FIG.

FIG. 3 is a characteristic diagram showing a relationship between a display area ratio and a luminance deviation.

FIG. 4 is a light emission luminance characteristic diagram in which an inversion section is shifted according to the present invention.

FIG. 5 is a typical emission luminance characteristic diagram.

FIG. 6 is a light emission luminance characteristic diagram having an inversion section.

[Explanation of symbols]

Reference Signs List 10: video data input terminal, 11: emission luminance characteristic acquisition circuit, 12: signal of inversion start level, 13: signal of inversion section, 14: level comparison circuit, 15: gate circuit, 16 ...
Adder circuit, 17 output terminal, 18 display number counter of each bit, 19 display area ratio calculation circuit, 20 memory, 2
1 ... Luminance deviation amount calculation circuit, 22 ... Luminance comparison circuit.

Continued on the front page (51) Int.Cl. ⁶ Identification code FI G09G 3/28 G09G 3/28 K 3/36 3/36 H04N 5/66 H04N 5/66 A (72) Inventor Masayuki Kobayashi Kawasaki-shi, Kanagawa Fujitsu General, Ltd., 1116, Suatsucho, Takatsu-ku (72) Inventor: Hayato Denda 1116, Suenaga, Takatsu-ku, Kawasaki, Kanagawa Prefecture, Ltd. Fujitsu General Co., Ltd. (58) Field surveyed (Int.Cl. ⁶ , DB name) G09G 3/00-3/38 H04N 5/66

Claims (4)

(57) [Claims] 1. A display apparatus in which a display panel is directly driven by a digitized video input signal to display an image, and a light emission luminance for outputting a signal 12 of an inversion start level in a frame and a signal 13 of an inversion section. A characteristic acquisition circuit 11, a level comparison circuit 14 for comparing data from a new video data input terminal 10 with the inversion start level signal 12, and an opening / closing control by an output of the level comparison circuit 14; A gradation correction circuit for a display device, comprising: a gate circuit 15 for outputting a signal 13; and an addition circuit 16 for adding data of a new video data input terminal 10 and a signal 13 in an inversion section. 2. A display device in which a display panel is directly driven by a digitized video input signal to display an image, and a light emission luminance for outputting an inversion start level signal 12 and an inversion section signal 13 in a frame. A characteristic acquisition circuit 11, a level comparison circuit 14 for comparing data from a new video data input terminal 10 with the inversion start level signal 12, and an opening / closing control by an output of the level comparison circuit 14; A gate circuit 15 for outputting a signal 13; and an addition circuit 16 for adding the data of the new video data input terminal 10 and the signal 13 in the inversion section. Counter 18, display area ratio calculation circuit 19, memory 20, brightness deviation amount calculation circuit 21, and brightness comparison circuit 22
A gradation correction circuit for a display device, comprising: 3. A display device in which a display panel such as a PDP or an LCD is directly driven by a digitized video input signal to display an image, an inversion start level signal 12 and an inversion section signal 13 in a frame.
, A level comparison circuit 14 for comparing data from a new video data input terminal 10 with the signal 12 of the inversion start level, and opening / closing control based on the output of the level comparison circuit 14. A gate circuit 15 for outputting the signal 13 in the inversion section, and an addition circuit 16 for adding the data of the new video data input terminal 10 and the signal 13 in the inversion section.
Wherein the output is supplied to a display panel 10 composed of a PDP, an LCD, or the like via an error diffusion processing circuit. 4. A display device in which a display panel such as a PDP or an LCD is directly driven by a digitized video input signal to display an image, an inversion start level signal 12 and an inversion section signal 13 in a frame. , A level comparison circuit 14 for comparing data from a new video data input terminal 10 with the signal 12 of the inversion start level, and an opening / closing control by the output of the level comparison circuit 14. A gate circuit 15 that outputs the signal 13 of the inversion section, and an addition circuit 16 that adds the data of the new video data input terminal 10 and the signal 13 of the inversion section. A display number counter 18 for each bit for counting a plurality of bits of video data in a memory corresponding to each bit; A display area ratio calculation circuit 19 for calculating the display area ratio by dividing the number of dots by the total number of dots;
A memory 20 comprising a look-up table in which the characteristics of the luminance deviation with respect to the display area ratio of the display element are stored in advance, a luminance deviation amount calculating circuit 21 for calculating the luminance deviation of each bit,
The luminance of each level is compared, and the signal 1 of the inversion start level
2. A gradation correction circuit for a display device, comprising: a luminance comparison circuit 22 for outputting a signal 13 of an inversion section;