JPH09244577A - Error diffusion processor for display device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To adapt luminance to proper gradation by obtaining a luminance changing amt. as per a display area rate of a subfield and also obtaining a calculating expression of an emitting luminance level of a driving signal level. SOLUTION: A diffusion output signal of M bits (e.g. a binary code signal) outputted from an error diffusion circuit 12 is converted into a driving signal for displaying a halftone image in a display panel 10a for <2M-gradation image data (e.g. a subfield data composed of M subfields with weight of Yk of one frame) by a subfield array converting circuit 40. The display area rate Sk of the display panel 10a is obtained by a video output monitoring circuit 14a based on this converted driving signal. The luminance changing amt. Δk (Sk) as for the display area rate Sk is obtained by a calculation circuit 42, and also the emitting luminance level of the driving signal level is obtained by using the calculating expression to output the data to be used for error diffusion processing to the error diffusion circuit 12.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an error diffusion processing device for displaying a pseudo halftone image by error diffusion in a digital display device having a non-linear gradation characteristic such as a PDP (plasma display panel). Is.

[0002]

2. Description of the Related Art Recently, PDPs have attracted attention as thin and lightweight display devices. The driving method of this PDP is completely different from the conventional CRT driving method, and is a direct driving method using digitized video input signals. Therefore, the luminance gradation emitted from the panel surface is
It is determined by the number of bits of the signal to be handled.

[0003] PDPs have different basic types, AC type and D type.
It is divided into two types of C type. In the AC type PDP, there was only a report on the gradation display up to a maximum of 64 gradations at the prototype level, but a future 256 gradation method using the address / display separation type driving method (ADS subfield method) has been proposed. I have.

One frame (or one field) in the ADS subfield method is composed of eight subfields having relative luminance ratios of, for example, 1, 2, 4, 8, 16, 32, 64, and 128. Display of 256 gradations is performed by a combination of screen luminances. Each subfield is composed of an address period in which data for one refreshed screen is written and a sustain period for determining a luminance level of the subfield. In the address period, first, wall charges are initially formed on each pixel at the same time for the entire screen, and then a sustain pulse is applied to the entire screen to perform display. The brightness of the subfield is proportional to the number of sustain pulses and is set to a predetermined brightness. In this way 2
56 gradation display is realized.

In the above-described AC driving method, as the number of gradations increases, the number of bits in an address period as a preparation period for lighting and emitting light in the panel within one frame period increases. The period becomes relatively short, and the maximum luminance decreases.

As described above, the luminance gradation emitted from the panel surface is determined by the number of bits of the signal to be handled. Therefore, if the number of bits of the signal to be handled is increased, the image quality is improved, but the emission luminance is reduced. If the number of bits of the signal to be handled is reduced, the light emission luminance increases, but the gradation display decreases and the image quality deteriorates.

The error diffusion process for reducing the grayscale error between the input signal and the emission brightness while reducing the bit number of the output drive signal more than the bit number of the input signal is a process for expressing pseudo halftone. , Used when expressing light and shade with few gradations. In a conventional general error diffusion circuit, a video signal of a p (eg, 8) -bit original pixel Ai, j is input from the video signal input terminal to the error diffusion circuit, and the number of bits is further changed to q ( For example, 4) Reduce the number of bits to emit light from the PDP.

Further, the light emission luminance characteristic calculation unit including a ROM or the like measures and stores the light emission luminance characteristic of the PDP from representative input data (solid line) that is as close as possible to y = x (dotted line) shown in FIG. Keep it. This emission luminance characteristic is sent to the error amount calculation unit to calculate the error, and the processing circuit unit adds the error to the input video signal and diffuses it to perform pseudo halftone display. As a result, although the light emission luminance level is like a staircase with a solid line in an instant, in reality,
The corrected luminance line is recognized in an averaged state and resembles the dotted line y = x.

However, the light emission luminance characteristic of a display device such as a PDP changes depending on data to be displayed, and may be the light emission luminance characteristic as shown in FIG. In such a case, in the method of adjusting to the typical light emission luminance characteristics as shown in FIG. 3, data other than when the representative characteristics are obtained cannot be adapted to the gradation characteristics. There has been a problem that a pseudo contour due to gradation non-adaptation appears.

Further, as shown in FIG. 5, the light emission luminance characteristic of a display device such as a PDP may have an inversion section in which the light emission luminance level decreases while the input drive signal increases. When the emission luminance level is inverted as shown in FIG. 5, there is also a portion in which the gradation characteristics of the pseudo-halftone display after error diffusion are also inverted, and what should be originally displayed brightly is displayed darkly in the image. There was a problem that something was wrong.

In order to solve such a problem, the present applicant has already proposed a tone adaptive type error diffusion processing device as shown in FIG. In FIG. 6, instead of the light emission luminance characteristic given from the ROM as in the prior art, the light emission luminance characteristic for every one or a plurality of frames is changed to the luminance deviation characteristic obtained from the load factor of the input data of the display device such as PDP. A device that is calculated based on the above-mentioned method and updates the light emission luminance characteristic for each one or a plurality of frames to perform error diffusion to prevent the appearance of pseudo contours and to prevent the image from feeling unnatural due to the reversal of the light emission luminance level. Proposed.

More specifically, the PD is obtained by performing error diffusion processing on an input video signal (not shown).
An error diffusion circuit 12 that outputs a diffusion output signal for displaying a pseudo halftone image at P10 is provided, and an inversion correction circuit 13, a video output monitoring circuit 14, and a look-up table are provided on the output side of the error diffusion circuit 12. The ROM 16 and the brightness characteristic acquisition circuit 18 are sequentially connected, and the output side of the brightness characteristic acquisition circuit 18 is connected to the error diffusion circuit 12 via the threshold value transfer circuit 20 to form a loop, and via the inversion detection circuit 21. To the inversion correction circuit 13.

The video output monitoring circuit 14 includes a sampling
Clock generation unit 22 and a plurality of bits (for example, M bits)
The data counter 24 that counts the display number of each bit in one or a plurality of frames by a plurality of (for example, M) counters corresponding to each bit of the video data, and the number of display dots counted by the data counter 24 , A count value selection unit 26 for calculating the display area ratio Sk by performing a calculation divided by the total number of dots.

The brightness characteristic acquisition circuit 18 includes a deviation calculator 28 for obtaining the brightness deviation characteristic of each bit, and the deviation calculator 2.
It is composed of a brightness characteristic calculation unit 30 which obtains a brightness deviation amount of each level based on the data of 8 and a threshold value conversion unit 32.
Reference numeral 34 denotes an arithmetic control signal generation circuit. The arithmetic control signal generation circuit 34 includes a count value selection unit 26, a deviation calculation unit 28,
It is configured to output a calculation control signal K to the brightness characteristic calculation unit 30 to cause a predetermined calculation.

The reversal correction circuit 13 corrects reversal by adding a reversal correction value to the diffusion output signal output from the error diffusion circuit 12, and the reversal detection circuit 21 includes the brightness characteristic acquisition circuit 1.
Inversion of the emission brightness level is detected from the emission brightness characteristic obtained in step 8, and an inversion correction value for obtaining a predetermined emission brightness characteristic is output to the inversion correction circuit 13.

In the above configuration, the video output monitoring circuit 1 from the error diffusion circuit 12 through the inversion correction circuit 13.
When the data is transmitted to 4, the data counter 24
Is a "M" counter corresponding to each bit of M-bit video data, and counts the "display dot number of subfield k" which is the display number of each bit in one or a plurality of frames. The count value selection unit 26 uses the “display dot number of subfield k” counted by the data counter 24.
Is divided by the “total number of dots” and the display area ratio Sk is calculated.
Ask for.

Then, using the display area ratio Sk obtained by the count value selecting unit 26 as an address and the coefficient read from the ROM 16 as a look-up table, the deviation calculating unit 28 obtains the luminance deviation characteristic of each bit. The brightness deviation amount of each level is obtained by the brightness characteristic calculation unit 30, converted into a threshold value by the threshold value conversion unit 32, and returned to the error diffusion circuit 12.

As described above, the brightness deviation amount calculation of each level is transmitted to the error diffusion circuit 12 by updating the gradation characteristic for every one or a plurality of frames. The error diffusion circuit 12 performs error diffusion processing based on this emission luminance characteristic and outputs it to the PDP 10 via the inversion correction circuit 13. With such a configuration, an image is processed in a loop of “acquisition of gradation characteristics” → “error diffusion” → “acquisition of gradation characteristics” → ... As a result, it is possible to sufficiently adapt the gradation characteristic to the data that changes every moment.

[0019]

However, in the proposed error diffusion processing device shown in FIG. 6, the emission brightness level Y (N) of the drive signal level N is calculated by the following arithmetic expression (1). However, there were the following problems.

That is, in the arithmetic expression (1), M is 1
The number of subfields that make up the frame (eg 6),
Ak is when the drive signal level N is represented by a binary number (N =
(A ₁ , A ₂ , ..., Ak, ...)) The kth bit data,
Since δ (Sk) represents the luminance deviation rate with respect to the display area rate Sk of k subfields, the weighting of a plurality of subfields (for example, 6 subfields SF1 to SF6) constituting one frame is 1 or 2. 4, 8, 16,
32, ..., It is necessary to have a configuration in which the index is increased by 2 when arranged in ascending order of weighting. For example, SF1 = 16, SF2 = 1, SF3 = 8, S
It was necessary to set F4 = 4, SF5 = 2, and SF6 = 32.

Therefore, the weighting of a plurality of subfields is 1, 2, 4, 4, 8, 8 or 1, 2, 3, 5, 7,
In the case of a display having a subfield that is not configured to double when arranged in ascending order of weight, such as 9 (for example, M having a display gradation number of 2 (M is an integer of 2 or more)).
In the case of a non-powered display), there is a problem that proper gradation adaptation cannot be performed with the emission luminance level Y (N) obtained by the calculation of the calculation formula (1).

In the case of a display in which the number of display gradations does not become 2 to the Mth power, there are the following cases already proposed by the present applicant. That is, the weighting of the n subfields SF1 to SFn is expressed by an index of 2, and n
In the case of displaying 2 n-th gradation by a combination of screen brightness, the brightness level of the drive signal changes from “2 m −1” to “2 m m” (for example, “7” to “8”). When there was a change, there was a problem that granular noise was seen on the screen corresponding to the changed part, so in order to solve this problem,
N subfields SF1 to S constituting one frame
At least one set of subfields in Fn are equally weighted (for example, 6 subfields SF
1 to SF6 are weighted as 1, 2, 4, 4, 8, and 8). In such a case, the above equation (1)
However, there is a problem that proper gradation adaptation cannot be performed with the light emission luminance level Y (N) obtained by the calculation of.

The present invention has been made in view of the above problems, and in an error diffusion processing device of a display device, weighting of a plurality of subfields constituting one frame is 1, 2, 4, 4 ,. 8, 8, 1, 2, 3,
An object of the present invention is to make it possible to perform appropriate gradation adaptation in a display device using a display panel that is not a subfield that doubles when arranged in ascending order of weight, such as 5, 7, and 9. It is what

[0024]

According to a first aspect of the present invention, there is provided an error diffusion processing device for a display device, comprising: an error diffusion circuit for obtaining a diffusion output signal having a bit number M smaller than that of an input video signal by performing an error diffusion process; One frame of an M-bit spread output signal is time-divided into M subfields, and the weight of each subfield is Yk (k = 0, 1, ..., M−).
1, the same applies hereinafter), and a subfield array conversion circuit for converting into a drive signal for displaying a halftone image on a display panel whose display gradation number is less than the Mth power of 2, and display on the display panel based on this drive signal. A video output monitoring circuit for obtaining the area ratio Sk and a level N (<
2 M), the amount of change in luminance Δk with respect to the display area ratio Sk of the subfield k is represented by Bk when the frequency of use of the subfield k is displayed on the display panel.
(Sk) is obtained, and the light emission luminance level Y (N) of the drive signal level N is calculated by the following equation (2). And an arithmetic circuit that outputs the data to be used in the error diffusion processing to the error diffusion circuit.

The subfield array conversion circuit displays an M-bit diffused output signal (for example, a binary code signal) output from the error diffusion circuit on a display panel having a display gradation number of less than 2 to the Mth power to display a halftone image. Drive signal (for example, one frame is converted into subfield data composed of M subfields having a weight of Yk). The video output monitoring circuit calculates the display area ratio Sk of the display panel based on the converted drive signal, and the arithmetic circuit calculates the luminance change amount Δk (Sk) with respect to the display area ratio Sk, and the arithmetic expression (2). Is used to obtain the light emission luminance level Y (N) of the drive signal level N, and the data for use in the error diffusion processing is output to the error diffusion circuit.

In the arithmetic expression (2), Bk represents the frequency at which the subfield k is used when the level N (<2 to the Mth power) of the drive signal is displayed on the display panel, and Yk
Represents the weight of each subfield when one frame is time-divided into M subfields in order to display a halftone image on a display panel whose display gradation number is less than the Mth power of 2. Weighting of a plurality of subfields forming a frame is 1, 2, 4, 4, 8, 8 or 1,
Even in a display device using a display panel that is not a subfield that doubles when arranged in ascending order of weight, such as 2, 3, 5, 7, and 9, set Bk and Yk to corresponding values. Therefore, proper gradation adaptation can be performed.

According to a second aspect of the present invention, in the first aspect of the invention, the arithmetic circuit includes an arithmetic control signal K and a display area ratio Sk.
And a brightness characteristic acquisition circuit having Bk × Δk (Sk) as an output content, and this brightness characteristic acquisition circuit has a calculation control signal K as an address and Bk × Yk as an output content. The second look-up table and the output contents of the first and second look-up tables are added, and the emission luminance level Y of the drive signal level N is added.
A brightness characteristic calculation circuit for obtaining (N) and a threshold conversion circuit for converting this emission brightness level Y (N) into a threshold value and outputting this threshold value to the error diffusion circuit as data for use in error diffusion processing. , The first and second look-up tables are used to increase the processing speed.

According to a third aspect of the present invention, in the first or second aspect of the invention, one frame includes six subfields (M
= 6), the weights Yk of these six subfields
(K = 0, 1, 2, ..., 5) is 1, 2, 4, 4, 8, 8
Since two sets of subfields having the same weighting are provided, the same operation as that of the invention of claim 1 or 2 is achieved, and the luminance level of the drive signal is from "2 m-1" to "2.
Even when changing to "m-th power" (for example, from "7" to "8"), it is possible to prevent granular noise from being seen on the screen corresponding to the changed portion.

According to a fourth aspect of the invention, in the invention of the third aspect, when a pixel having a drive signal level N for lighting one of the two subfields having the same weight is displayed on the display panel, the two subfields are displayed. By halving the frequency Bk at which each of the
From the viewpoint of preventing the dynamic pseudo contour from appearing on the display screen while having the same effect as the invention of claim 3, the lighting subfields and non-lighting subfields having the same weight are alternately displayed in a grid pattern. Even in such a case, proper gradation adaptation can be performed.

[0030]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS One embodiment of the present invention will be described with reference to FIG. 1, the same parts as those in FIG. 6 are designated by the same reference numerals, and detailed description thereof will be omitted. In FIG. 1, 10a is a PDP as an example of a display panel.
P10a indicates that when one frame is time-divided into M (M is an integer of 2 or more) subfields, each subfield is arranged in the ascending order of weighting, and the weighting does not increase by a factor of 2. The number of display gradations is less than this.

Reference numeral 12 is an error diffusion circuit, and this error diffusion circuit 12 uses n bits (n ≧ M + 1, for example n) by using a threshold value.
= 8), an error diffusion process is performed on an input video signal (not shown) to output an M-bit (for example, M = 6) diffusion output signal with a small number of bits for performing pseudo-halftone display. Has been done. The error diffusion circuit 1
A subfield array conversion circuit 40 is coupled to the output side of 2 through the inversion correction circuit 13.

The subfield array conversion circuit 40 is
A diffusion output signal (for example, a binary code) output from the error diffusion circuit 12 is converted into M subfield data and output. Each of the M subfield data represents data of each subfield when one frame is composed of M subfields SF1 to SFm weighted to a predetermined value.

On the output side of the subfield array conversion circuit 40, the PDP 10a and the video output monitoring circuit 14a are connected. The video output monitoring circuit 14a includes a sampling clock generator 22
And a data counter 24a for counting the display number of one or a plurality of frames of each subfield by M counters corresponding to the respective M subfield data, and output from the arithmetic control signal generation circuit 34. A count value selection unit 26 that calculates the display area ratio Sk by performing a calculation to divide the number of display dots counted by the data counter 24a by the total number of dots based on the calculation control signal K
It consists of

Reference numeral 42 denotes an arithmetic circuit. This arithmetic circuit 42 is
It comprises a first LUT (look-up table) 44 and a luminance characteristic acquisition circuit 18a, and the first LUT 44 has an operation control signal K output from the operation control signal generation circuit 34 and a display area obtained by the count value selection unit 26. Rate Sk
The output content Bk × Δk (Sk) is stored in advance as an address. Bk of the output content Bk × Δk (Sk) is the drive signal level N (<2 M) in the PDP.
10a represents the frequency with which the subfield k is used, Δk (Sk) represents the amount of change in luminance with respect to the display area ratio Sk of the subfield k, and Bk × Δk (S
The calculation result of k) is obtained by calculation using a value obtained by actually measuring the light emission luminance characteristic of the PDP 10a, and is stored in advance in the first LUT 44 as the output content of the corresponding address.

The brightness characteristic acquisition circuit 18a includes a second LU
The second LUT 46 is composed of a T46, a brightness characteristic calculation unit 30, and a threshold conversion unit 32, and the output content Bk × Yk is stored in advance in the second LUT 46, using the calculation control signal K output from the calculation control signal generation circuit as an address. This output content B
Yk of k × Yk represents the weight of the subfield k, and the calculation result of Bk × Yk is obtained by calculation using the value obtained by actually measuring the emission luminance characteristic of the PDP 10a, and the corresponding address is obtained. Output contents of the second LUT 46
Is stored in advance.

The brightness characteristic calculation unit 30 uses the output contents of the first and second LUTs 44 and 46 to calculate the light emission brightness level Y of the drive signal level N by the calculation of the following calculation formula (2).
It is configured to obtain (N).

The threshold conversion unit 32 converts the emission brightness level Y (N) output from the brightness characteristic calculation unit 30 into a threshold value, and the error diffusion circuit 12 via the threshold transfer circuit 20.
It is configured to output to Reference numeral 21 denotes an inversion detection circuit. The inversion detection circuit 21 is configured to detect inversion of gradation based on the threshold value output from the threshold value conversion unit 32 and output an inversion correction signal to the inversion correction circuit 13. ing.

The operation of the embodiment shown in FIG. 1 will be described with reference to FIG. For convenience of explanation, the PDP 10a
2A, as shown in FIG. 2A, one frame is composed of 6 (M = 6) subfields SF1 to SF6, and each subfield SF1, SF2, SF3, SF4, SF.
5, the weighting of SF6 is 1, 2, 4, 4, 8, 8 and the number of display gradations is 28 gradations (<2 to the 64th power of 64), and the gradation level 4 (N = The case of displaying 4) will be described.

To display this gradation level 4, either one of SF3 and SF4 having a weighting of 4 may be turned on, but from the viewpoint of preventing the occurrence of a dynamic false contour, FIG. As shown, the pixels that turn on SF3 and SF4
Suppose that the lit pixels are arranged alternately in the horizontal direction and the vertical direction in a staggered arrangement, and the frequency of use of SF3 is B
₂ and SF4 use frequency B ₃ are each 1/2 of the other sub-fields SF1, SF2, SF5, use frequency B ₀ of _{SF6, B 1, B 4,} B 5 is zero.

When the video data (diffusion output signal) subjected to the error diffusion processing in the error diffusion circuit 12 is input to the subfield array conversion circuit 40 via the inversion correction circuit 13, the subfield array conversion circuit 40 converts the binary code from the binary code. 2 (a), the weighted subfields SF1 to SF6 are converted into data, and the PDP 10a
To display a pseudo-halftone image, and to the video output monitoring circuit 14a to input each subfield k (k
= 0, 1, ..., 5, and so on).

The arithmetic control signal K from the arithmetic control signal generating circuit 34 and the display area ratio S obtained by the video output monitoring circuit 14a.
The calculated value Bk × Δ from the first LUT 44 with k as an address.
k (Sk) outputs and inputs to the brightness characteristic calculation unit 30.
Further, the arithmetic control signal K from the arithmetic control signal generation circuit 34.
As an address from the second LUT 46 as a calculated value Bk × Yk
Is output and input to the brightness characteristic calculation unit 30.

Next, the brightness characteristic calculator 30 performs the following calculation to obtain the emission brightness level Y (4) of the drive signal level 4.

Then, the light emission luminance level Y (N) is converted into a threshold value by the threshold value conversion unit 32 and returned to the error diffusion circuit 12 via the threshold value transfer circuit 20 to perform gradation adaptive error diffusion processing. Further, the inversion detection circuit 21 detects the inversion of the gradation from the threshold value output from the threshold value conversion unit 32, transfers the inversion correction signal to the inversion correction circuit 13, and performs the inversion correction.

In the above embodiment, the number M of subfields forming one frame is 6, two sets of them are weighted equally, and the drive signal level N (for example, N = 4) is set.
The luminance level of the drive signal is “2 m-th power-
It prevents grainy noise from appearing on the screen corresponding to the changing portion from "1" to "m to the power of 2", and switches the equally lit subfields and non-illuminated subfields in a grid pattern. Even in the case where the artificial pseudo contour is prevented from appearing on the display screen, the suitable gradation adaptation can be performed, but the present invention is not limited to this. For example, the number M of subfields forming one frame is set to 6, and it can be used when the weighting is 1, 2, 3, 5, 7, and 9, and it is also used when M is other than 6. be able to.

In the above embodiment, the arithmetic circuit is the first LU.
T and the luminance characteristic acquisition circuit are included, and the luminance characteristic acquisition circuit is provided with the second LUT to increase the calculation processing speed. However, the present invention is not limited to this.
The arithmetic circuit obtains a luminance change amount Δk (Sk) with respect to the display area ratio Sk of the subfield k, and calculates an emission luminance level Y (N) of the drive signal level N by an arithmetic expression. In this case, any data may be used as long as it is obtained in step S3 and outputs the data for use in the error diffusion processing to the error diffusion circuit.

In the above-described embodiment, the case where the display panel is a PDP has been described. However, the present invention is not limited to this, and the present invention can also be used for a digital display panel (for example, a liquid crystal display panel).

[0047]

According to the present invention, in a gradation adaptive error diffusion processing device, an M bit diffusion output signal (for example, a binary code signal) output from an error diffusion circuit is displayed with a display gradation number of less than 2 to the Mth power. Drive signal for displaying a halftone image on the display panel (for example, one frame has a weight of Y
a subfield array conversion circuit for converting into M subfields (k subfield data) and a display area ratio S of the display panel based on the drive signal.
A video output monitoring circuit for obtaining k, a luminance change amount Δk (Sk) with respect to the display area ratio Sk of the subfield k, and a light emission luminance level Y (N) for the drive signal level N are obtained.
The following formula (2) And an arithmetic circuit that outputs the data to be used in the error diffusion processing to the error diffusion circuit.

Thus, in this arithmetic expression (2),
Bk represents the frequency at which the subfield k is used when displaying the level N (<M to the power of 2) of the drive signal on the display panel, and Yk is the display panel whose display gradation number is less than M to the power of 2. Since the weight of each subfield when one frame is time-divided into M subfields to display a halftone image is represented, the weighting of a plurality of subfields forming one frame is 1, 2, 4, 4,
Even in a display device using a display panel such as 8, 8 or 1, 2, 3, 5, 7, 9 that is not a subfield that doubles when arranged in ascending order of weight, Bk and Yk are Appropriate gradation adaptation can be performed by setting corresponding values.

Further, the arithmetic circuit is composed of a first look-up table having an output content of Bk × Δk (Sk) with the arithmetic control signal K and the display area ratio Sk as an address, and the luminance characteristic acquisition circuit. A second characteristic acquisition circuit, which uses the operation control signal K as an address and outputs Bk × Yk as an output content.
A luminance characteristic calculation circuit for obtaining the light emission luminance level Y (N) of the drive signal level N by adding the output contents of the look-up table and the first and second look-up tables, and this light emission luminance level Y (N) as a threshold value. And a threshold value conversion circuit that outputs this threshold value to the error diffusion circuit as data to be used in the error diffusion processing, the calculated value Bk ×
Since the two look-up table having the output contents of Δk (Sk) and Bk × Yk is used, the calculation processing speed can be increased.

Further, one frame is composed of 6 subfields (M = 6), and the weights Yk (k = 0, 1, 2, ..., 5) of these 6 subfields are 1, 2, 4 4,
When two sets of subfields having the same weighting are provided as 8 and 8, the luminance level of the drive signal is "2 m-
From "1" to "m to the power of 2" (for example, from "7" to "8")
Even when there is a change, it is possible to prevent granular noise from being seen on the screen corresponding to the changed portion.

Further, when a pixel having a drive signal level N that lights one of two subfields having the same weight is displayed on the display panel, the frequency Bk at which each of these two subfields is used is halved. In this case, from the viewpoint of preventing dynamic pseudo contours from appearing on the display screen, even when displaying the lighting subfields and the non-lighting subfields having the same weight alternately in a grid pattern, the appropriate gradation is displayed. Adaptation can be done.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of an error diffusion processing device of a display device according to the present invention.

2A and 2B are explanatory diagrams of the operation of FIG. 1, in which FIG. 2A is an explanatory diagram of a specific example of a subfield array weighted by a subfield array conversion circuit, and FIG. 2B is a drive signal in the subfield array of FIG. It is explanatory drawing of the example of a display of PDP when level N is 4.

FIG. 3 is a characteristic diagram showing a typical example of light emission luminance characteristics.

FIG. 4 is a characteristic diagram showing another example of emission luminance characteristics.

FIG. 5 is a characteristic diagram showing an example of a light emission luminance characteristic having an inversion section.

FIG. 6 is a block diagram showing an example of an already proposed error diffusion processing device.

[Description of Reference Signs] 10, 10a ... PDP (plasma display panel), 12 ... Error diffusion circuit, 13 ... Inversion correction circuit,
14, 14a ... Video output monitoring circuit, 16 ... ROM,
18, 18a ... Luminance characteristic acquisition circuit, 20 ... Threshold transfer circuit, 21 ... Inversion detection circuit, 22 ... Sampling /
Clock generation unit, 24, 24a ... Data counter,
26 ... Count value selection unit, 28 ... Deviation calculation unit, 30
... Luminance characteristic operation unit, 32 ... Threshold conversion unit, 34 ... Operation control signal generation circuit, 40 ... Subfield array conversion circuit, 42 ... Operation circuit, 44 ... First LUT (lookup table), 46 ... Second LUT, Bk ... Frequency at which the subfield k is used when the drive signal level N is displayed on the PDP 10a, K ... Operation control signal for the subfield k, M ... Number of subfields in one frame, Sk ... Display area ratio of the subfield k , Yk
... Weight of subfield k, Y (N) ... Emission brightness level of drive signal level N, Δk (Sk) ... Amount of change in brightness with respect to display area ratio Sk of subfield k.

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Masayuki Kobayashi, 1116 Suenaga, Takatsu-ku, Kawasaki-shi, Kanagawa Prefecture, Fujitsu General Co., Ltd. (72) Seiji Matsunaga, 1116 Suenaga, Takatsu-ku, Kawasaki, Kanagawa Prefecture 72) Inventor Hayato Denda 1116 Suenaga, Takatsu-ku, Kawasaki-shi, Kanagawa Within Fujitsu General Co., Ltd. (72) Toru Aida 1116 Suenaga, Takatsu-ku, Kawasaki-shi, Kanagawa Within Fujitsu General Limited

Claims (4)

[Claims] 1. An error diffusion circuit for obtaining a diffusion output signal having a bit number M smaller than that of an input video signal by performing an error diffusion process, and the M bit diffusion output signal when one frame is divided into M subfields. A drive signal for displaying a halftone image on a display panel in which the number of display gradations is less than the Mth power of 2 by dividing the weight of each subfield into Yk (k = 0, 1, ..., M-1, and so on). A subfield array conversion circuit for converting into a display field, a video output monitor circuit for obtaining a display area ratio Sk of the display panel based on the drive signal, and a level N (<M to the power of 2) of the drive signal in the display panel. Subfield k when displaying
When the frequency at which is used is Bk, the luminance change amount Δk (Sk) with respect to the display area ratio Sk of the subfield k is obtained, and the emission luminance level Y (N) of the drive signal level N is obtained.
The arithmetic expression An error diffusion processing device for a display device, comprising: an arithmetic circuit that outputs data to be used for error diffusion processing to the error diffusion circuit. 2. The arithmetic circuit comprises a first look-up table having an arithmetic operation control signal K and a display area ratio Sk as an address and Bk × Δk (Sk) as an output content, and a luminance characteristic acquisition circuit. The acquisition circuit adds the output contents of the second look-up table whose output contents are Bk × Yk with the operation control signal K as an address, and the output contents of the first and second look-up tables to add the emission brightness level Y of the drive signal level N. A luminance characteristic calculating circuit for obtaining (N), the light emission luminance level Y (N) obtained by this luminance characteristic calculating circuit are converted into a threshold value, and this threshold value is output to the error diffusion circuit as data for use in the error diffusion processing. The error diffusion processing device for a display device according to claim 1, comprising a threshold conversion circuit. 3. One frame includes six subfields (M =
6), and the weights Yk of the 6 subfields
(K = 0, 1, 2, ..., 5) is 1, 2, 4, 4, 8, 8
An error diffusion processing device for a display device according to claim 1 or 2. 4. The frequency Bk at which each of the two subfields is used when displaying the drive signal level N for illuminating one of the two subfields having the same weight is 1/2. Item 3. An error diffusion processing device for a display device according to item 3.