JPH07175439A - Driving method for display device - Google Patents

Abstract

PURPOSE:To provide a driving method which does not generate pseudo contours by dividing an arbitrary sub-field to several sub-fields and rearranging the luminance sequence of the sub-fields between one frame so as to avert making a non-display period long. CONSTITUTION:The arbitrary sub-field among the plural sub-fields of a display device constituted to project video signals of multiple gradations by constituting one field of the plural sub-fields varying in the relative ratios of the luminance is divided to >=2 and these sub-fields are driven by rearranging scanning sequence. Image levels are changed form 127 to 128 levels. For example, SF8 is divided to two (SF8-1, 8-2) and the luminance sequence is rearranged like SF1, 3, 5, 8-2, 7, 8-1, 6, 4, 2, by which the 127 of the first frame is quantized by 111010111 and the 128 of the second frame is quantized by 000101000. Then, the images are displayed while the display period and the non-display period are alternated 9 times at approximately equal intervals in a short period of time. The non-display period is thus made sufficiently shorter than one frame and the pseudo contours are made nearly inconspicuous.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of driving a display device of a digital input signal in which one frame is composed of a plurality of subfields having different luminance relative ratios and a multi-gradation video signal is displayed. It is about.

[0002]

2. Description of the Related Art Recently, as a thin and lightweight display device, P
Attention has been paid to DP (plasma display panel). This PDP driving method is completely different from the conventional CRT driving method and is a direct driving method using a digitized video input signal. Therefore, the brightness gradation emitted from the panel surface is determined by the number of bits of the signal to be handled. PDPs can be divided into two types, AC type and DC type, which have different basic characteristics. In DC type PDPs, there have been reports of improvement methods for brightness and life, which have already been issues, and progress toward practical application is being made. is there.

On the other hand, in the AC type PDP, although sufficient characteristics have been obtained in terms of brightness and life, there has been only a report regarding gray scale display up to a maximum of 64 gray scale displays at a prototype level. Recently, address / display separation type driving method (AD
A future 256-gradation method based on the S subfield method) has been proposed. The address / display separation type driving method is a method in which n-bit input data is lit at a constant luminance for a weighting time of each bit in one frame. The panel structure of the PDP (plasma display panel) 10 used in this method is shown in FIG. 5, and the drive sequence and drive waveforms are shown in FIGS. 6 (a) and 6 (b).

In FIG. 5, an X sustain electrode 12 and a Y sustain electrode 13 which form a pair are formed on the lower surface of the surface glass substrate 11 on the display surface side by a transparent electrode and an auxiliary electrode. The auxiliary electrode forms the bus electrode 23 on a part of the transparent electrode in order to prevent a voltage drop due to the resistance of the transparent electrode. A dielectric layer 14 is provided on the X sustain electrode 12 and the Y sustain electrode 13, and a stripe rib 18 is formed on the dielectric layer 14 to separate the coupling between the cells. Further, a protective layer 15 made of a MgO film is deposited. Address electrodes 17 are formed on the back glass substrate 16 facing each other. The stripe-shaped ribs 18 on the stripes are provided between the address electrodes 17, and the address electrodes 17 are covered with R.
The (red) phosphor 19, the G (green) phosphor 20, and the B (blue) phosphor 21 are separately formed. In the discharge space 22, Ne +
Xe mixed gas is enclosed.

In FIG. 6A, one frame has a relative luminance ratio of 1, 2, 4, 8, 16, 32, 64, 128.
It is composed of 8 sub-fields, and 256 gradations are displayed by combining the brightness of 8 screens. In FIG. 6B, each subfield is refreshed 1
It is composed of an address period for writing data for the screen and a sustain period for determining the luminance level of the subfield. In the address period, wall charges are initially formed in each pixel at the same time on the entire screen, and then sustain pulses are applied to the entire screen for display. The brightness of the subfield is proportional to the number of sustain pulses and is set to a predetermined brightness. In this way, 256 gradation display is realized.

In the AC driving method as described above, as the number of gradations is increased, the number of bits in the address period as a preparation period for lighting and emitting the panel within one frame period is increased. The period is relatively short and the maximum brightness is low. In this way, since the brightness gradation emitted from the panel surface is determined by the number of bits of the signal to be handled, if the number of bits of the signal to be handled is increased, the image quality is improved, but the light emission luminance is reduced, and conversely If the number of bits is reduced, the light emission luminance is increased, but gradation display is reduced and the image quality is deteriorated.

The error diffusion process for reducing the grayscale error between the input signal and the emission brightness while reducing the bit number of the output drive signal more than the bit number of the input signal is a process for expressing pseudo halftone. , Used when expressing light and shade with few gradations. That is, in the conventional general error diffusion processing circuit, the video signal of the original pixel Ai, j of n (for example, 8) bits is input to the video signal input terminal, passes through the vertical direction addition circuit and the horizontal direction addition circuit, Further, the bit conversion circuit performs a process of reducing the number of bits to m (for example, 4) bits, and the PDP driving circuit causes the PDP to emit light.

Further, the error diffusion signal from the horizontal direction addition circuit is compared with prestored data in the error detection circuit, the difference is taken, and a predetermined coefficient is applied in the error weighting circuit for weighting. , The error detection output is the original pixel Ai, j
Pixels before h lines, for example, are added to the vertical direction addition circuit through an h line delay circuit that outputs a reproduction error Ej−1 generated by one line in the past, and are d dots before the original pixel Ai, j. No. of pixels, for example, a reproduction error Ei−1 generated by one dot in the past is added to the horizontal direction addition circuit via a d dot delay circuit. In addition,
The coefficients in the error weighting circuit are generally set so that the sum of all of them becomes 1.

As a result, although the light emission luminance level represented by 4 bits such as the stepwise shape is instantaneously output to the output terminal of the bit conversion circuit, in reality, the stepwise upper and lower light emission luminance levels are actually output. Since the levels are alternately output at a predetermined ratio, the levels are recognized in an averaged state, and the corrected luminance line is approximately y = x.

[0010]

However, for example, when the image on the left side of the image is dark and the right side of the image is bright, the image level in a part of the screen is 127 in the first frame, and Frame has changed to a level of 128. Sub-frame scanning is
As shown in FIG. 4, if SF1 to SF8 are scanned in order of luminance and 8 bits are used as an image signal, the level of 127 is 1111111.
Quantized at 0 and 128 levels are quantized at 00000001. Therefore, from 127 to 128, SF1 to SF7 are the display period, SF8 and SF
An image is displayed from 1 to SF7 as a non-display period and SF8 as a display period. When such a moving image is displayed, the non-display period becomes relatively long, which is the same period as one frame, so that the non-display period appears as a black line in the image, which appears as a false contour. there were.

According to the present invention, an arbitrary subfield is divided into several parts, and the luminance order of the subfields in one frame is rearranged so that the non-display period does not become long, so that a false contour does not occur. The purpose is to

[0012]

The present invention provides a display device in which one frame is composed of a plurality of subfields having different relative ratios of luminance so as to display a multi-gradation video signal. A driving method of a display device, characterized in that an arbitrary subfield among the subfields is divided into two or more, and the scanning order is rearranged so as to be driven.

[0013]

As for the image level, it is assumed that the first frame has a level of 127 and the next frame has a level of 128. For example, SF8 is divided into two, and the luminance order is S
By rearranging like F1, 3, 5, 8-2, 7, 8-1, 6, 4, 2, 12 in the first frame
7 levels are quantized at 111010111 and the second
The 128 levels in the frame number are 0001010
Quantized with 00. Therefore, as shown in FIG.
From 127 to 128, the display period and the non-display period are
Images are displayed in a short time and switched at approximately equal intervals 9 times. Therefore, the display period and the non-display period are sufficiently shorter than one frame, and the false contour is hardly noticeable.

[0014]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 3 shows an example of a circuit that realizes the driving method according to the present invention. The video signal (RGB) input terminal 51 and the control signal input terminal 52 of the n-bit original pixel Ai, j are connected to the write controller 53. The write control unit 53 is connected,
It is connected to the frame memory 58 via the address control unit 55 and the data control unit 56 of the I / O buffer unit 54. The control signal input terminal 52 and the external sub address setting signal input terminal 67 are connected to the read control unit 60, the address decoder 61 in the read control unit 60 is connected to the address control unit 55, and the sub address counter 62. Is transmitted through the sub address decoder 63 to the I
It is connected to the bit selection unit 57 of the / O buffer unit 54. Further, the bit selection unit 57 connected to the data control unit 56 and the sub address decoder 63 is connected to the PDP 10 via the address driver 65 and the address driver 66.

The sub-address decoder 63 uses SF1
Up to SF8, subfields having a long sustain period are divided into some and rearranged in luminance order. Example 1: The SF8 having the longest sustain period is divided into two as shown in FIG. At this time, the relative ratio of brightness of SF8 is 128
Is divided into two, 64 and 64, and address data is added to each of them to form SF8-1 and SF8-2. The luminance order is SF1, 3, 5, 8-2, 7, 8-1, 6 ,.
Rearrange as 4, 2, etc.

Example 2: The longest SF8 is divided into four, and the second longest SF7 is divided into two. At this time, the relative brightness ratio 128 of SF8 is divided into four of 32, 32, 32, and 32, and the address data is added to each, and SF8-
1, SF8-2, SF8-3, SF8-4. Similarly, the relative ratio 64 of the brightness of SF7 is divided into two, 32 and 32, and the address data is added to each, and SF7-
1, SF7-2. In addition, the brightness order is SF1,
3, 8-3, 5, 7-1, 8-1, 6, 8-2, 7-
Sort as 2, 4, 8-4, 2.

The luminance order in Examples 1 and 2 can be fixedly set in advance, but in addition, the external sub-address setting signal input terminal 67 can be used to generate a random number table of an external microcomputer. It may be possible to input a randomly set signal.

Next, the general operation of the circuit shown in FIG. 3 will be described first. Digital video signal (RGB)
Of the clock signal, the blanking signal, and the vertical and horizontal synchronization signals from the input terminal 51 to the write control unit 53.
3 and the read control unit 60. Further, the write control unit 53 outputs a write address signal according to the control signal, and the address control unit 55 of the I / O buffer unit 54.
To the data control unit 56, and the video signal data from the data control unit 56 is input to the data control unit 56 according to the address signal input from the address control unit 55.
8 to write and store.

When the writing of the video signal data for one frame is completed, the address decoder 61 of the read control unit 60.
Outputs a read address signal based on the input control signal, inputs the read address signal to the address control unit 55, reads the video signal data from the frame memory 58, and inputs the video signal data to the data control unit 56. The sub-address counter 62 of the read control unit 60 counts each period from SF1 to SF8 in one frame and outputs a count signal, and the count signal is rearranged by the sub-address decoder 63 to set the order. Output according to.

The output from the sub-address decoder 63 is input to the bit selection section 57 of the I / O buffer section 54,
The video signal data read from the frame memory 58 is also input to the bit selection unit 57.

The bit selection section 57 selects a bit of the video signal data and inputs it to the address driver 65 and the address driver 66. Further, based on the control signal from the control signal input terminal 52, an address signal is generated to generate an address. Input to driver 65 and address driver 66, and
The video signal is displayed by writing in the designated address portion of 10.

Next, the case of Example 1 will be described as a specific driving method of the present invention. Here, the image level is 127 for the first frame and 12 for the next frame.
Assume that the level has changed to 8. In Example 1, SF8 is divided into two, and the luminance order is SF1, 3, 5, 8-2,
Since they are rearranged into 7, 8-1, 6, 4, and 2, 127 levels in the first frame are quantized by 111010111, and 128 levels in the second frame are quantized by 000101000. Therefore,
From 127 to 128, the display period and the non-display period are
Images are displayed in a short time and switched at approximately equal intervals 9 times. Therefore, the display period and the non-display period are sufficiently shorter than one frame, and the false contour is hardly noticeable.

Next, the case of Example 2 of the present invention will be described. In Example 2, SF8 is divided into four, SF7 is divided into two, and the luminance order is SF1, 3, 8-3, 5 ,.
7-1, 8-1, 6, 8-2, 7-2, 4, 8-4, 2
Therefore, if the level in the first frame is 127, the level is quantized by 110110101101, and 128 in the second frame is 001.
It is quantized by 001010010. Therefore, 12
From 7 to 128, the display period and the non-display period are further shortened and the image is displayed 17 times at substantially equal intervals. Therefore, the display period and the non-display period are 1
It is even shorter than the frame, and false contours are barely noticeable.

The rearrangement order is not limited to the case where the rearrangement order is fixedly set in advance as in the first and second examples, and the signals for periodically rearranging or controlling the order of the sub address decoder 63 are externally supplied. It is also possible to use a signal from the external sub-address setting signal input terminal 67 connected to the microcomputer or the like.

[0025]

【The invention's effect】

(1) In the present invention, an arbitrary subfield is divided into two or more, and the scanning order is rearranged to drive, so that the display period and the non-display period are repeated in a state of being sufficiently shorter than one frame, and false The contour becomes inconspicuous.

(2) The longest sustain period SF8 is divided into two, and the luminance order is SF1, 3, 5, 8-2,
By rearranging like 7, 8-1, 6, 4, and 2, the display period and the non-display period can be shortened from the 127 level in the first frame to the 128 level in the second frame. , And the image is displayed by switching 9 times at substantially equal intervals. Therefore, the display period and the non-display period are sufficiently shorter than one frame, and the false contour is hardly noticeable.

(3) The longest sustain period SF8 is divided into four, the second longest SF7 is divided into two, and the luminance order is SF1, 3, 8-3, 5, 7-1, 8 -1,
6, 8-2, 7-2, 4, 8-4 and 2 are rearranged so that the level in the first frame is 127.
From the second to 128 of the second frame, the display period and the non-display period are switched in a shorter period of time, and the image is displayed 17 times at substantially equal intervals. Therefore, the display period and the non-display period become shorter than one frame, and the false contour becomes almost inconspicuous.

(4) The rearrangement order is not limited to the case where it is fixedly set in advance, and signals for controlling the rearrangement or controlling the order of the sub-address decoder 63 are connected to an external microcomputer or the like. By using the signal from the external sub address setting signal input terminal 67, the periodicity is further reduced.

[Brief description of drawings]

FIG. 1 is an explanatory diagram of subfield division showing an embodiment of a driving method of a display device according to the present invention.

FIG. 2 is an explanatory diagram showing an example of driving a video signal according to the present invention.

FIG. 3 is a block diagram showing an embodiment of a display device for implementing a driving method according to the present invention.

FIG. 4 is an explanatory diagram showing an example of driving a video signal according to a conventional method.

FIG. 5 is a perspective view of a PDP used in a 256 gradation method.

FIG. 6 is a drive sequence diagram and a drive waveform diagram in the 256 gradation method.

[Explanation of symbols]

10 ... PDP (plasma display panel), 1
1 ... Surface glass substrate, 12 ... X sustain electrode, 13 ...
Y sustain electrode, 14 ... Dielectric layer, 15 ... Protective layer, 1
6 ... Back glass substrate, 17 ... Address electrode, 18 ... Strip-shaped rib, 19 ... R (red) phosphor, 20 ... G (green)
Fluorescent material, 21 ... B (blue) fluorescent material, 22 ... Discharge space, 23
... bus electrodes, 30 ... video signal input terminals, 31 ... vertical direction addition circuit, 32 ... horizontal direction addition circuit, 33 ... bit conversion circuit, 34 ... output terminal, 35 ... error detection circuit, 36 ... h
Line delay circuit, 37 ... d dot delay circuit, 38 ... Memory, 40 ... Error weight circuit, 41 ... Error weight circuit, 51 ...
Video signal (RGB) input terminal, 52 ... Control signal input terminal, 53 ... Write control section, 54 ... I / O buffer section, 5
5 ... Address control unit, 56 ... Data control unit, 57 ... Bit selection unit, 58 ... Frame memory, 60 ... Read control unit, 61 ... Address decoder, 62 ... Sub address counter, 63 ... Sub address decoder, 65 ... Address driver, 66 ... address driver, 67 ... external sub-address setting signal input terminal.

Claims (4)

[Claims] 1. A display device in which one frame is composed of a plurality of sub-fields having different luminance relative ratios to display a multi-gradation video signal, and an arbitrary sub-field of the plurality of sub-fields is displayed. A driving method of a display device, characterized in that a field is divided into two or more, and a scanning order is rearranged for driving. 2. The method for driving a display device according to claim 1, wherein the scanning order of the subfields is randomly changed and driven in frame units according to an external subaddress setting signal. 3. A first subfield (SF1) to an eighth subfield (SF8) having different luminance relative ratios.
In a display device configured to display a multi-gradation video signal by forming a frame, two subfields (SF8) having the longest sustain period among the plurality of subfields (SF8-1, 8-2), and the scanning order is SF1, 3, 5, 8-2, 7,
A driving method of a display device, characterized in that the driving is performed by rearranging into 8-1, 6, 4, and 2. 4. A first subfield (SF1) to an eighth subfield (SF8) having different luminance relative ratios.
In a display device configured to display a multi-gradation video signal by forming a frame, four subfields (SF8) having the longest sustain period among the plurality of subfields (SF8-1, 8-2, 8
-3, 8-4), the second longest seventh subfield (SF7) is divided into two (SF7-1, 7-2), and the scanning order is SF1, 3, 8-3 ,. 5, 7-
A method for driving a display device, wherein the display device is arranged and driven in the order of 1, 8-1, 6, 8-2, 7-2, 4, 8-4 and 2.