JP2820037B2 - Error diffusion circuit of display device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a display device for displaying images and characters, which is used for gradation correction for correcting, when the light emission luminance characteristic of input data after pseudo halftone display is inverted, the characteristic. Type error diffusion circuit.

[0002]

2. Description of the Related Art Recently, as a thin and lightweight display device, P
Display devices such as DPs (plasma display panels) and LCDs have attracted attention. The driving method of the PDP or the like is completely different from the conventional CRT driving method, and is a direct driving method using a digitized video input signal. Therefore, the luminance gradation emitted from the panel surface is determined by the number of bits of the signal to be handled.

[0003] In the AC type PDP, sufficient characteristics are obtained with respect to luminance and life, but with respect to gradation display, an address / display separation type driving method (ADS subfield method).
Has been proposed. Explaining the driving sequence of this method, one frame is composed of 8 pixels whose relative ratio of luminance is 1, 2, 4, 8, 16, 32, 64, 128.
It is composed of a number of subfields, and displays 256 gradations by combining the luminance of eight screens. Each subfield is composed of an address period in which data for one refreshed screen is written and a sustain period for determining a luminance level of the subfield. In the address period, first, wall charges are initially formed on each pixel at the same time for the entire screen, and then a sustain pulse is applied to the entire screen to perform display. The brightness of the subfield is proportional to the number of sustain pulses and is set to a predetermined brightness. In this way, 256 gradation display is realized.

In the above-described AC driving method, as the number of gradations increases, the number of bits in an address period as a preparation period for lighting and emitting a panel within one frame period increases. The period becomes relatively short, and the maximum luminance decreases.

As described above, since the luminance gradation emitted from the panel surface is determined by the number of bits of the signal to be handled, the picture quality is improved by increasing the number of bits of the signal to be handled, but the emission luminance is reduced, and conversely. If the number of bits of the signal to be handled is reduced, the light emission luminance increases, but the gradation display decreases and the image quality deteriorates.

[0006] In the case of a general video signal, an error diffusion process is performed to minimize the shading error between the input signal and the emission luminance while reducing the number of bits of the output drive signal from the number of bits of the input signal. This is a process for expressing a pseudo-halftone, and is used when expressing grayscale with a small number of gradations.

Therefore, an error diffusion circuit 23 as shown in FIG. 4 has been conventionally used. This error diffusion circuit 23
An n (for example, 8) -bit original pixel signal is input from a video source to a video data input terminal 10, and the processing circuit unit 24 performs a process of reducing the number of bits to emit a PDP as a display panel. When the transfer level signal 27 is sent to the memory 26, the data stored in the memory 26 is compared with the error amount calculation unit 25, the difference is obtained, and the difference is multiplied by a predetermined coefficient. Add to signal. As a result, as shown in FIG. 5, the output after the bit conversion instantaneously outputs the light emission luminance level represented by 4 bits like a staircase of a solid line, Since the upper and lower light emission luminance levels in a staircase are alternately output at a predetermined ratio, they are recognized in an averaged state, and y =
x is the corrected luminance line.

[0008]

In general, the display becomes higher stepwise as shown by the solid line in FIG. 5, and the input level of the drive signal is brighter when N + 1 than N. In the case of a general light emission luminance characteristic having no inversion section as shown in FIG. 5, the error diffusion Δ (N) at that time is given by: y (N) for the corrected luminance characteristic and Y (N) for the light emission luminance characteristic. Error diffusion Δ (N) = corrected luminance characteristic y (N) −emission luminance characteristic Y (N) is diffused as an error to obtain a pseudo halftone. That is, in the error diffusion circuit 23, for example, Y (1
12) Since processing is performed as <Y (128), Y (1
12) and Y (128) are appropriately mixed to produce a halftone between Y (112) and Y (128).

However, in a panel such as a PDP having a digital driving method developed in recent years, an input level of N + 1 may be darker than an input level of N depending on display data. For example, as shown in FIG. 6, inversion is started from the 128th bit of the drive signal, and 14 bits after 16 bits.
Even if 4 bits are still inverted from the previous level, and finally become higher at 160 bits than the previous level. Therefore, if it is assumed that 32 bits from 128 bits to 160 bits are the inverted section, Y (112) becomes Y (12
Even if an attempt is made to appropriately mix 8) to express a luminance higher than Y (112), the result of processing by error diffusion in the error diffusion circuit 23 will display a lower luminance than Y (112).

However, in the conventional gradation adaptive error diffusion circuit, since the processing on the circuit is performed on the assumption that the input level is brighter at N + 1 than at N, the display characteristics are reduced as shown in FIG. In this case, the gray-scale characteristics of the pseudo halftone after error diffusion are also inverted, and the part that should be displayed brightly is displayed darkly. The incident occurred, and no measures were taken against it.

According to the present invention, there is provided a tone correction type error diffusion circuit for correcting, when a light emission luminance characteristic after pseudo halftone display with respect to input data is inverted, by adding a simple circuit thereto. The purpose is to provide.

[0012]

According to the present invention, there is provided a display apparatus in which a digitized video input signal is subjected to halftone display processing by an error diffusion circuit 23, and then a display panel is directly driven for display. A tone correction circuit 32 for shifting to a non-inverted section when the emission luminance characteristic is inverted at a stage subsequent to the error diffusion circuit 23.
The error diffusion circuit of the display device is characterized in that the error amount of the error diffusion circuit 23 is calculated based on the emission luminance characteristic 28 corrected by the gradation correction circuit 32.

[0013]

In the case of a light emission luminance characteristic having an inversion section, for example,
If it is assumed that 32 bits from the 128th bit of the drive signal are the inversion section, even if an attempt is made to appropriately mix Y (112) and Y (128) to express luminance higher than Y (112), the error diffusion circuit 23 The result of processing by error diffusion is
The luminance lower than Y (112) is displayed.

Therefore, the present invention performs a process of shifting the light emission luminance characteristic line by an inversion period. That is, Y
An image in which halftone is expressed by appropriately mixing (112) and Y (128) is output as a mixture of Y (112) and Y (160), and is therefore higher than Y (112). It can express brightness.

[0015]

An embodiment of the present invention will be described below with reference to the drawings. In FIG. 1, reference numeral 10 denotes a video data input terminal from a video source. An error diffusion circuit 23 and a gradation correction circuit 32 are connected to the output side of the video data input terminal 10.

The error diffusion circuit 23 includes a processing circuit 24
And the error amount calculation unit 25. An output terminal of the transfer level signal 27 of the error diffusion circuit 23 is connected to the emission luminance characteristic acquisition circuit 11 via the level comparison circuit 29 and the level shift circuit 30 of the gradation correction circuit 32. The output terminal of the emission luminance characteristic 28 on the output side of the emission luminance characteristic acquisition circuit 11 is connected to the error amount calculation unit 25, and the output terminal of the inversion start level 12 is connected to the level comparison circuit 29.
And the other input side of the level comparison circuit 14.

An output terminal of the image data 31 of the error diffusion circuit 23 is connected to one input side of the level comparison circuit 14. The output terminal of the signal 13 is connected to the input side of the gate circuit 15, and the gate circuit 1
5 is connected to the other input side of the adder circuit 16. The output terminal 17 of the addition circuit 16 is connected to the light emission luminance
It is connected to displays such as P and LCD.

The details of the emission luminance characteristic acquisition circuit 11 are as follows.
As shown in FIG. 2, a display number counter 18 for each bit for counting a plurality of (M) bits of video data in a memory corresponding to each bit, and a calculation of a display load ratio by dividing the number of display dots by the total number of dots. And a memory 2 comprising a look-up table in which characteristics of a luminance deviation with respect to a display load ratio of a display element are stored in advance.
0, a luminance deviation amount calculating circuit 21 for calculating a luminance deviation of each bit, and a luminance comparing circuit 22 for comparing the luminance of each level and outputting a signal (B) 12 of an inversion start level and a signal 13 of an inversion section. Become.

The operation of the above configuration will be described. In the case of a general light emission luminance characteristic having no inversion section as shown in FIG.
Is zero, there is no addition even if the gate of the gate circuit 15 is opened. Error diffusion Δ (N) when there is no inversion section is obtained by correcting the corrected luminance characteristic with y (N),
Assuming that the emission luminance characteristic is Y (N), Δ (N) = y (N) −Y (N) is diffused as an error to obtain a pseudo halftone. That is, in the error diffusion circuit 23, for example, Y (112) <Y (12
8), Y (112) and Y (12)
8) is mixed appropriately to produce a halftone of Y (112) and Y (128). The output subjected to the halftone processing is sent as it is from an output terminal 17 to a display such as a PDP via an adding circuit 16.

Next, in the case of a light emission luminance characteristic having an inversion section, the present invention performs an error diffusion process without using the gradation of a portion where the gradation is inverted. Two processes are performed. 1. The emission luminance characteristic line is shifted by the inversion section. 2. The signal in the inverted section of the data after error diffusion is level-shifted to a non-inverted portion and output.

Specifically, for example, as shown in FIG.
The inversion is started from the 128th bit of the drive signal, and the 144th bit after 16 bits is still inverted from the previous level, and finally becomes higher at 160 bits than the previous level. Assuming that 32 bits are an inversion section, Y (11
Even if 2) and Y (128) are appropriately mixed to express a higher luminance than Y (112), the result of processing by error diffusion by the error diffusion circuit 23 displays a lower luminance than Y (112). I will.

Therefore, the present invention provides the following two processings.
"1. The emission luminance characteristic line is shifted by the inversion section."
Is performed. More specifically, in FIG. 2, an M-bit transfer level signal 27 is sent from the error diffusion circuit 23 to a level comparison circuit 29 to compare the level with the inversion start level 12, and further obtains a light emission luminance characteristic via a level shift circuit 30. Input to the circuit 11. Then, the display number counter 18 of each bit composed of M counters corresponding to each bit counts the display number of each bit in one frame.

Next, in the display load ratio calculation circuit 19,
The calculation of “the number of display dots (the output of the display number counter 18 of each bit) ÷ the total number of dots” is performed to obtain the display load ratio. The luminance deviation calculation circuit 21 calculates the luminance deviation of each bit based on the display load ratio calculated by the display load ratio calculation circuit 19 and the data of the memory 20 including a look-up table.

In the case of displaying M bits, if an arbitrary level n is represented by B0, B1, B2,.
The calculation of the luminance Yn of each level is performed by the following equation. α is linear data of y = x. The calculation of the luminance deviation amount of each level is performed by the luminance deviation amount calculation circuit 21 according to the following equation.

The luminance deviation amounts obtained in this manner are sequentially compared by the luminance comparing circuit 22. If the data after the previous data is smaller than the previous data, that is, if there is a so-called inversion phenomenon, the signal 12 of the inversion start level is compared with the signal 12 of the inversion start level. The signal 13 of the inversion section and the emission luminance characteristic 28 corrected by shifting to the non-inversion section are output. When an inversion phenomenon like the dotted line characteristic in FIG. 3 occurs, the inversion start level signal 12 of the light emission luminance characteristic acquisition circuit 11 starts inversion at the 128th bit and continues up to 159 bits. The level signal B is output and input to the level comparison circuit 14 and the level comparison circuit 29.

From the error diffusion circuit 23, the halftone-processed video data A is sequentially input to the level comparison circuit 14. The levels A and B are compared by the level comparison circuit 14. Up to 127 bits, A <B, and there is no output from the level comparison circuit 14. Therefore, the gate of the gate circuit 15 is not opened, and only new data A is output to the output terminal 17.

If the operation result of the level comparison circuit 14 is 1
When A ≧ B from 28 bits to 143 bits, the gate of the gate circuit 15 is opened by the output of the level comparison circuit 14, and 32 bits of the output 13 of the signal 13 in the inversion section of the emission luminance characteristic acquisition circuit 11 are added to the addition circuit 16. Sent to
It is added to the halftone processed video data A. That is, for 128 bits, 32 bits are added to 160 bits.
The output is at the same level as the luminance level of the bit drive input signal.

Thus, from 128 bits to 160
Assuming that 32 bits up to the bit are an inversion section, a video that expresses halftone by appropriately mixing Y (112) and Y (128) is output as Y (112) and Y (16).
0) is mixed and output, so that Y (112)
Higher brightness can be expressed.

Hereinafter, similarly, Y (144) and Y (1
60) is appropriately mixed to express a halftone, and the output is a mixture of Y (144) and Y (176), so that a higher luminance than Y (144) can be expressed. An image expressing halftone by appropriately mixing Y (160) and Y (176) is output as Y (160) and Y (192).
Are mixed and output, so that a luminance higher than Y (160) can be expressed.

Next, in the detection of the error diffusion Δ (N), when the light is inverted, the emission luminance line Y (N) is shifted by −32, so that the error of the input signal equal to or higher than the inversion level is Δ (N). N) = y (N) −Y (N + 32), and in the case of N = level shift circuit 30, an error is calculated as Δ (130) = y (130) −Y (130 + 32), and the corrected luminance line y (N ) Is performed. The light emission luminance characteristics thus corrected are supplied from the output terminal 17 to a display such as a PDP or LCD.

[0031]

【The invention's effect】

(1) On a panel such as a PDP or an LCD, an input level of N + 1 may be displayed darker than N depending on display data, but according to the present invention, when an emission luminance characteristic is inverted. In addition, a tone correction circuit 32 for shifting to a non-inverted section is interposed, and the error amount of the error diffusion circuit 23 is calculated based on the emission luminance characteristic 28 corrected by the tone correction circuit 32. Therefore, even if there is an inversion section, the input level N + 1 is always displayed brighter than N. Therefore, the image does not feel uncomfortable.

(2) A gradation correction circuit 32 is provided at the subsequent stage of the error diffusion circuit 23 to shift the light emission luminance characteristic to a non-reversed section when the luminance characteristic is inverted. Is composed of a light emission luminance characteristic acquisition circuit 11, a level comparison circuit 14, a gate circuit 15, and an addition circuit 16, and the light emission luminance characteristic 28 of the light emission luminance characteristic acquisition circuit 11
Is used to calculate the error amount of the error amount calculation unit 25, so that the desired object can be achieved only by adding a simple circuit.

[Brief description of the drawings]

FIG. 1 is a block diagram showing an embodiment of an error diffusion circuit of a display device according to the present invention.

FIG. 2 is a detailed block diagram of a light emission luminance characteristic acquisition circuit 11 in FIG.

FIG. 3 is a light emission luminance characteristic diagram in which an inversion section is shifted according to the present invention.

FIG. 4 is a block diagram of an error diffusion circuit of a conventional display device.

FIG. 5 is a typical light emission luminance characteristic diagram without an inversion section.

FIG. 6 is a light emission luminance characteristic diagram having an inversion section.

[Explanation of symbols]

Reference Signs List 10: video data input terminal, 11: emission luminance characteristic acquisition circuit, 12: signal of inversion start level, 13: signal of inversion section, 14: level comparison circuit, 15: gate circuit, 16 ...
Addition circuit, 17 output terminal, 18 display number counter of each bit, 19 display load ratio calculation circuit, 20 memory, 2
1: luminance deviation amount calculation circuit, 22: luminance comparison circuit, 23:
Error diffusion circuit, 24 processing circuit section, 25 error amount calculation section, 26 memory, 27 transfer level signal, 28 light emission luminance characteristic, 29 level comparison circuit, 30 level shift circuit, 31 video data, 32: gradation correction circuit.

──────────────────────────────────────────────────の Continued on the front page (51) Int.Cl. ⁶ Identification code FI G09G 3/36 G09G 3/36 H04N 5/66 H04N 5/66 A (72) Inventor Masayuki Kobayashi 1116 Suenaga, Takatsu-ku, Kawasaki City, Kanagawa Prefecture Address Fujitsu General Co., Ltd. (72) Inventor Hayato Denda 1116, Suenaga, Takatsu-ku, Kawasaki City, Kanagawa Prefecture Co., Ltd. Fujitsu General Co., Ltd. (58) Field surveyed (Int.Cl. ⁶ , DB name) G09G 3/00- 3/38 H04N 5/66

Claims (4)

(57) [Claims] 1. A display device in which a digitized video input signal is subjected to halftone display processing by an error diffusion circuit 23 and then directly driven to display a display panel, and is displayed in a stage subsequent to the error diffusion circuit 23. When the light emission luminance characteristic is inverted, a gradation correction circuit 32 for shifting to a section where the light emission luminance characteristic is not inverted is interposed. 23. An error diffusion circuit for a display device, wherein 23 error amounts are calculated. 2. A display device in which a digitized video input signal is subjected to halftone display processing by an error diffusion circuit 23 and then directly driven to display a display panel, and is displayed at a subsequent stage of the error diffusion circuit 23. When the light emission luminance characteristic is inverted, a tone correction circuit 32 for shifting to a non-inverted section is interposed, and the error diffusion circuit 23 is connected to the processing circuit unit 24 and the error amount calculation unit 25. The gradation correction circuit 32 outputs the signal 12 of the inversion start level in the frame, the signal 13 of the inversion section, and the emission luminance characteristic 28 corrected by shifting to the non-inversion section. An acquisition circuit 11, video data subjected to error diffusion processing, and a signal 1 of the inversion start level
2, a gate circuit 15 that is opened and closed by the output of the level comparison circuit 14 and outputs the signal 13 in the inversion section, the video data subjected to error diffusion processing, and the signal 13 in the inversion section. An error diffusion circuit for a display device, comprising: an addition circuit 16 for adding an error amount; and an error amount of an error amount calculation unit 25 calculated by a light emission luminance characteristic 28 of the light emission luminance characteristic acquisition circuit 11. 3. A display device in which a digitized video input signal is subjected to halftone display processing by an error diffusion circuit 23 and then directly driven to display a display panel, and is displayed at a subsequent stage of the error diffusion circuit 23. When the light emission luminance characteristic is inverted, a tone correction circuit 32 for shifting to a non-inverted section is interposed, and the error diffusion circuit 23 is connected to the processing circuit unit 24 and the error amount calculation unit 25. The gradation correction circuit 32 outputs the signal 12 of the inversion start level in the frame, the signal 13 of the inversion section, and the emission luminance characteristic 28 corrected by shifting to the non-inversion section. An acquisition circuit 11, video data subjected to error diffusion processing, and a signal 1 of the inversion start level
2, a gate circuit 15 that is opened and closed by the output of the level comparison circuit 14 and outputs the signal 13 in the inversion section, the video data subjected to error diffusion processing, and the signal 13 in the inversion section. , And the light emission luminance characteristic acquisition circuit 11
Display number counter 18 for each bit, display load ratio calculation circuit 1
9, comprising a memory 20, a luminance deviation amount calculating circuit 21 and a luminance comparing circuit 22, wherein the error amount of the error amount calculating section 25 is calculated by the light emitting luminance characteristic 28 of the light emitting luminance characteristic acquiring circuit 11. Error diffusion circuit of the display device. 4. A display device in which a digitized video input signal is subjected to halftone display processing by an error diffusion circuit 23, and then directly driven to display a display panel to display the same. When the emission luminance characteristic is inverted, a tone correction circuit 32 for shifting to a non-inverted section is interposed, and the error diffusion circuit 23 is provided with a processing circuit unit 24 and an error amount calculation unit 25. The gradation correction circuit 32 outputs the signal 12 of the inversion start level in the frame, the signal 13 of the inversion section, and the emission luminance characteristic 28 corrected by shifting to the non-inversion section. An acquisition circuit 11, video data subjected to error diffusion processing, and a signal 1 of the inversion start level
2, a gate circuit 15 that is opened and closed by the output of the level comparison circuit 14 and outputs the signal 13 in the inversion section, the video data subjected to error diffusion processing, and the signal 13 in the inversion section. , And the light emission luminance characteristic acquisition circuit 11
A display number counter 18 for each bit for counting a plurality of bits of video data in a memory corresponding to each bit
A display load ratio calculating circuit 19 for calculating the display load ratio by dividing the number of display dots by the total number of dots; and a memory 20 comprising a look-up table in which characteristics of a luminance deviation with respect to the display load ratio of the display element are stored in advance. And a luminance deviation amount calculating circuit 21 for calculating the luminance deviation of each bit, and comparing the luminance of each level, and correcting by shifting the signal 12 of the inversion start level and the signal 13 of the inversion section to a section which is not inverted. An error diffusion circuit for a display device, comprising: a luminance comparison circuit for outputting a light emission luminance characteristic.