JP3327058B2 - Pseudo pattern processing circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a plasma display panel (PDP) and a liquid crystal display panel (LCD).
The present invention relates to a pseudo-pattern processing circuit for reducing a pseudo-pattern in an error diffusion processing circuit in a display device such as the above.

[0002]

2. Description of the Related Art Recently, as a thin and lightweight display device, P
Attention has been paid to DP display devices. The drive system of this PDP display device is completely different from the conventional CRT drive system, and is a direct drive system using digitized video input signals. Therefore, the luminance gradation emitted from the panel surface is determined by the number of bits of the signal to be handled.

[0003] PDPs are AC type and DC having fundamental characteristics different from each other.
Type. Among them, AC-type PDPs have sufficient characteristics in terms of luminance and lifetime, but there are only reports on gradation display up to a maximum of 64 gradations at the prototype level. However, in the future, the address and display separation type driving method (ADS subfield method) will be
A gradation method has been proposed.

In this AC driving method, as the number of gradations increases, the number of bits in an address period as a preparation period for lighting and emitting light in the panel within one frame period increases. And the maximum luminance decreases. As described above, the luminance gradation emitted from the panel surface is determined by the number of bits of the signal to be handled. Therefore, if the number of bits of the signal to be handled is increased, the image quality is improved, but the emission luminance is reduced, and conversely, the signal to be handled is If the number of bits is reduced, the light emission luminance increases, but the gradation display decreases and the image quality deteriorates.

Therefore, the applicant of the present invention has proposed a method as shown in FIG.
While reducing the number of bits of the output drive signal from the number of bits of the input signal, the grayscale error between the input signal and the light emission luminance is minimized, and even when video signals of the same level are continuously input, a pseudo pattern is generated. An error diffusion processing circuit 28 which can prevent occurrence of the error diffusion processing has been proposed.

In FIG. 3, on the output side of the load circuits 40 and 41 of the error detection circuit 35, a reproduction error E generated in the past by a pixel h lines before the original pixel A (i, j), for example, one line, is shown. The vertical direction addition circuit 31 is connected via an h-line delay circuit 36 that outputs (i, j-1), and a pixel that is d dots before the original pixel A (i, j), for example, one dot in the past. The horizontal addition circuit 32 is connected via a d-dot delay circuit 37 for outputting the generated reproduction error E (i-1, j).

[0007] The spread output signal obtained by incorporating the error by the vertical direction adder circuit 31 and the horizontal direction adder circuit 32 is sent to a bit conversion circuit 33, and the spread output signal quantized to n bits by the bit conversion circuit 33. With m (≦
n-1) bits and then output from the video output terminal 34 to the PDP.
Output as a drive signal.

In this state, when video signals of the same level are continuously input to the video signal input terminal 30, for example,
The 8-bit original pixel video signal is 55H, 55H,.
When the input is continuously made at the same level as H, the error load output values output from the load circuits 40 and 41 to the h-line delay circuit 36 and the d-dot delay circuit 37 become the same continuous values, respectively. There is a problem that the PDP displays a pseudo pattern that is a regular repeating pattern.

Therefore, in order to remove the pseudo pattern, a pseudo random pulse generation circuit 52 is further provided, and the pseudo random pulse generation circuit 52 is connected to the pseudo noise input terminal 5.
Based on a pseudo-noise signal (for example, a 2-bit signal) input at random to 4, a pseudo-random pulse having a noise level of + k, 0, and -k (for example, k is a positive real number equal to or less than 1) is generated. The pseudo random pulse is added to the signal in the error diffusion processing circuit 28 via the correction addition circuit 50.
For this reason, even if the level of the input original pixel video signal is the same continuous value, the video output signal (drive signal) output from the video output terminal 34 to the display panel (for example, PDP) can fluctuate, and the continuous same value can be obtained. Does not. Therefore,
It is possible to prevent (suppress) the occurrence of a pseudo pattern on the display panel.

[0010]

However, in the above-described method, the pseudo-random pulse generation circuit 52 generates
The noise level of the pseudo-random pulse added from the correction addition circuit 50 was independent of the luminance level of the input video signal. For this reason, in a screen where the level of the input video signal is relatively low (screen in which the video is dark), the portion where the noise level is + k in the pseudo random pulse added for the pseudo pattern erasure is bright and conspicuous, deteriorating the image quality. There was a problem.

SUMMARY OF THE INVENTION The present invention has been made in view of the above-mentioned problems, and controls the noise level of a pseudo-random pulse added for erasing a pseudo-pattern in accordance with the luminance level of an input video signal, thereby providing a pseudo-random pulse. An object of the present invention is to prevent unnecessary bright points from being displayed on a dark screen by a pulse.

[0012]

A pseudo-pattern processing circuit according to the present invention comprises: a reproduction error adding circuit for adding a reproduction error generated in the past from an original pixel to an input video signal of an n-bit original pixel; A bit conversion circuit for converting a diffusion output signal output from the reproduction error addition circuit into a signal of m (≦ n−1) bits and outputting the converted signal to a display panel, and a correction preset for correcting luminance gradation of the display panel An error detection circuit that detects a difference between a luminance level and a diffusion output signal output from the reproduction error addition circuit, weights and outputs the error, and an error load output signal output from the error detection circuit is delayed by a predetermined number of pixels and reproduced. In an error diffusion processing circuit having a delay circuit for outputting an error to the reproduction error adding circuit, an input level detection circuit for detecting a luminance level of the input video signal; When the detection output of the Le detection circuit is equal to or higher than a set value set in advance, based on a pseudo-noise signal, a plurality of noise signals including the noise signal and the 0 and noise signal of a negative level <br/> beyond at least 0 level A pseudo-random pulse generation circuit that outputs a noise signal of 0 and a negative level among the plurality of noise signals based on the pseudo noise signal when the detection output is less than the set value. ,
A correction addition circuit for adding a signal output from the pseudo random pulse generation circuit to a signal in the error diffusion processing circuit.

[0013]

The input level detection circuit detects the luminance level of the input video signal. When the luminance level of the input video signal is equal to or higher than a preset set value (in a portion where the video screen is not darker than the set value), the pseudo random pulse generation circuit generates a noise signal exceeding 0 level based on the pseudo noise signal. (For example, a pulse signal having a noise level of + k) and 0 and a negative level
Noise signal (e.g. noise level is 0, the pulse signal -k) Le outputs a noise signal of a plurality (e.g., three) including. These noise signals are added to the signal in the error diffusion processing circuit by the correction addition circuit.

For this reason, even if the luminance levels of the input video signals are continuous and the same, a plurality of noise signals (for example, when the noise level is +
k, 0, and -k pulse signals) are added to the signal in the error diffusion processing circuit, and continuous data can fluctuate.
The occurrence of a regular repeating pattern in the diffuse output is prevented.

When the luminance level of the input video signal is lower than the set value (in a portion where the video screen is darker than the set value), the pseudo-random pulse generation circuit generates
0 and negative level noise signals (eg, a noise level of 0,
-K pulse signal). These noise signals are added to the signal in the error diffusion processing circuit by the correction addition circuit.

As described above, when the luminance level of the input video signal is low, the noise signal output from the pseudo-random pulse generation circuit and added to the signal in the error diffusion processing circuit has a level of 0 and a negative level (for example, a level of 0). 0, -k)
Therefore, a bright point due to a noise signal does not occur in a dark screen, and the image quality can be improved.

[0017]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of a pseudo-pattern processing circuit according to the present invention will be described below with reference to FIG. The same parts as those in FIG. Reference numeral 30 denotes a video signal input terminal of an n-bit original pixel A (i, j). The video signal input terminal 30 passes through a vertical addition circuit 31, a correction addition circuit 50, a horizontal addition circuit 32, and The conversion circuit 33 performs processing for reducing the number of bits, and is connected to the video output terminal 34. The vertical direction adding circuit 31 and the horizontal direction adding circuit 32 constitute a reproduction error adding circuit.

Reference numeral 60 denotes an input level detection circuit for detecting the luminance level of the video signal input to the video signal input terminal 30. Reference numeral 62 denotes a pseudo-random pulse generation circuit. When the detection output of the input level detection circuit 60 is equal to or more than a preset value, the pseudo-random pulse generation circuit 62 generates a pseudo-noise signal input to the pseudo-noise input terminal 54. Based on at least the noise signal exceeding 0 level and 0
And outputting a plurality of noise signals including a noise signal of a negative level , and when the detection output is less than the set value, based on the pseudo noise signal input to the pseudo noise input terminal 54, among the plurality of noise signals, It is configured to output a noise signal of level 0 or less.

For example, if the input video signal is 8 bits (256
In the case of (gradation), the set value of the pseudo random pulse generation circuit 62 is set to 4 bits (16 gradation levels). When the pseudo noise signal input to the pseudo noise input terminal 54 is 2 bits, the pseudo random pulse generation circuit 62
Outputs a noise signal as shown in FIG.

That is, when the detection output of the input level detection circuit 60 is equal to or greater than the set value, the pseudo random pulse generation circuit 62 outputs the pseudo noise signals “00”, “01”, “ 10 "," 11 "
, The noise level is “0”, “0”, “+ k”,
A noise signal corresponding to "-k" is output. When the detection output of the input level detection circuit 60 is less than the set value, the pseudo random pulse generation circuit 62 outputs the pseudo noise signals “00”, “01”, “10”, and “11” that are randomly input.
, The noise level is “0”, “0”, “0”,
A noise signal corresponding to "-k" is output.

The other circuit configuration is the same as that of FIG. 2, and an error detection circuit 35 is connected to the output side of the horizontal direction addition circuit 32. The error detection circuit 35 stores the correction luminance level data for luminance gradation correction in advance.
An addition circuit 3 for calculating an OM 38 and a sum of a corrected luminance level set in the ROM 38 and a diffusion output signal output from the horizontal direction addition circuit 32 to output an error detection signal;
9 and a load circuit 4 for outputting an error load signal obtained by weighting the error detection signal output from the adder circuit 39 with a predetermined weight.
It consists of 0 and 41.

The load circuits 40 and 4 of the error detection circuit 35
The output side of 1 is connected to the vertical direction addition circuit 31 and the horizontal direction addition circuit 32 via an h line delay circuit 36 and a d dot delay circuit 37, respectively. The h-line delay circuit 36 delays the error load output signal output from the load circuit 40 by h lines, and outputs the original pixel A (i,
j), a reproduction error (eg, a reproduction error E (i, j-1) generated in the past by one line when h = 1) for a pixel h lines before is output to the d-dot delay circuit 3.
Numeral 7 is a signal for delaying the error load output signal output from the load circuit 41 by d dots.
The reproduction error for the pixel before the dot (for example, when d = 1, the reproduction error E (i−1,
j)) is output.

Next, the operation of the embodiment shown in FIG. 1 will be described. Density modulation is performed using two luminance gradations to create a visually pseudo gradation in a small area having a certain spread, thereby obtaining multiple gradations. This will be described in more detail. A (i, j): input pixel value of the current processing target A (i, j-1): input pixel value of one line before (when h = 1) A (i-1, j): one dot before Input pixel value (when d = 1) δv: Error load value of diffusion output pixel from the previous line δh: Error load value of diffusion output pixel from the previous line The signal and the data from the ROM 38 are summed by an adding circuit 39 to obtain an error output signal.

This error output signal is sent to the load circuits 40 and 41
, The weighted error load output signals δv and δh of Kv (<1) and Kh (= 1−Kv), respectively, and the one-line delay circuit 36 (when h = 1) and the one-dot delay circuit 37
(In the case of d = 1), and is incorporated into the original pixel A (i, j) by the vertical direction addition circuit 31 and the horizontal direction addition circuit 32. C (i, j) = A (i, j) + δv + δh Become.

Note that C (i, j): the diffusion output pixel value of the current processing target δv = Kv × [f ｛C (i, j−1)｝ − Br] δh = Kh × [f ｛C (i− [1, j) {-Br] f {C (i, j)}: Corrected luminance for C (i, j) Br: Light emission luminance level

The diffused output signal into which the error has been incorporated and diffused is sent to the bit conversion circuit 33, and the bit conversion circuit 33
The spread output signal quantized by n bits at m is given by m (≦ n
-1) Convert to bits and output from video output terminal 34. In this way, the original video input signal is diffused by incorporating errors, and a signal having a smaller number of bits than the original video input signal can obtain a smooth response without lowering the light emission luminance.

Next, the correction addition circuit 50 adds the noise signal output from the pseudo random pulse generation circuit 62 to the input signal on the output side of the vertical addition circuit 31 for each dot or line. The input level detection circuit 60 always detects the luminance level of the video signal input to the video input terminal 30. The pseudo random pulse generation circuit 62
The noise signal to be output differs depending on whether the detection output of the input level detection circuit 60 is equal to or greater than the set value. Therefore, the case where the luminance level of the original pixel video signal (for example, an 8-bit (256 gradation) video signal) input to the video signal input terminal 30 is equal to or higher than a set value (for example, the level of 4 bit (16 gradation)) The explanation will be made separately for the case of less than.

(1) In the case where the luminance level of the input video signal is equal to or higher than the set value: As shown on the left side of FIG. Signals "00", "01", "10", "1"
1, the noise level is “0”, “0”, “+”
k ”and“ −k ”are output. For this reason, even if the luminance levels of the original pixel video signals input to the video input terminal 30 are continuous and the same value, three types of noise signals with different noise levels output from the pseudo-random pulse generation circuit 62 are added to continuously output the same. Data
To prevent the occurrence of a regular repeating pattern in the diffused output. Therefore, it is possible to prevent (suppress) the occurrence of a pseudo pattern in the PDP.

At this time, the pseudo random pulse generation circuit 6
2 generates a random pulse signal (noise signal) at a period of a predetermined length (for example, periods 524 and 287) based on the pseudo noise signal, and generates + k (H level) and -k within this period.
Since the number of appearances of (L level) is equal, 524,287
The total sum of the data when the correction addition is performed during the period of the pulse number is equal to the total sum of the data when the correction addition is not performed, and the correction addition amount of the image data is ± 0.

(2) When the luminance level of the input video signal is lower than the set value: The pseudo random pulse generation circuit 62, as shown on the right side of FIG. Signals "00", "01", "10", "1"
1, the noise level is “0”, “0”,
Two types of noise signals corresponding to "0" and "-k" are output. Since this noise signal does not contain a positive level,
The noise signal (random pulse signal) added for pseudo pattern erasure does not become a bright point in a dark screen,
Image quality can be improved.

In the above embodiment, the pseudo-noise signal randomly input to the pseudo-noise input terminal has 2 bits. However, the present invention is not limited to this, and the present invention can be applied to cases other than 2 bits. Further, in the above-described embodiment, as shown in FIG. 2A, when the detection output of the input level detection circuit is equal to or more than the set value, the pseudo random pulse generation circuit generates pseudo noise signals “00” and “00” that are input randomly. 01 ”,“ 1 ”
The noise level is “0”, based on “0” and “11”.
Noise signals corresponding to “0”, “+ k”, and “−k” are output, and when the detection output is less than the set value, pseudo noise signals “00”, “01”, “10”, and “10” input randomly. 1
1, the noise level is “0”, “0”,
Although the noise signal corresponding to "0" and "-k" is output, the present invention is not limited to this.

For example, a pseudo random pulse generation circuit
When the detection output of the input level detection circuit is higher than the set value,
As in the case of FIG. 2A, the noise levels are “0”, “0”, “+ k” based on the pseudo noise signals “00”, “01”, “10”, and “11” that are randomly input. ","-
k, a noise signal corresponding to the pseudo-noise signal “00”, “01”, “10”, or “10” is input when the detection output is less than the set value, as shown in FIG.
Based on “11”, the noise level is “0”, “0”,
It may be configured to output a noise signal corresponding to “−k” or “−k”.

In the above embodiment, the reproduction error adding circuit is constituted by the vertical direction adding circuit 31 and the horizontal direction adding circuit 32,
Although the correction addition circuit 50 is inserted between the vertical addition circuit 31 and the horizontal addition circuit 32, the present invention is not limited to this. For example, the reproduction error adding circuit may be constituted by only one of the vertical direction adding circuit 31 and the horizontal direction adding circuit 32. Further, the correction and addition circuit 50 may be provided at an appropriate place where a noise signal can be added to the signal in the error diffusion processing circuit 28. For example, in FIG. 1, the video signal input terminal 30 and the vertical direction addition circuit 31
, The output side of the horizontal addition circuit 32 or between the addition circuit 39 and the load circuits 40 and 41,
May be inserted.

In the above-described embodiment, the case where the display panel is a PDP has been described. However, the present invention is not limited to this, and the present invention can be used for a display panel other than the PDP (for example, a liquid crystal display panel).

[0035]

As described above, the pseudo pattern processing circuit according to the present invention comprises a reproduction error adding circuit (for example, a vertical direction adding circuit 31 or a horizontal direction adding circuit 32), a bit conversion circuit 33, an error detecting circuit 35, and a delay circuit. Since the error detection circuit 35 detects and weights the sum of the corrected luminance level and the diffused output signal and outputs the result to the delay circuits 36 and 37, the error detection circuit 35 has a higher level than the original video input signal. With a signal of a small number of bits, the emission luminance is not reduced, and
A smooth response is obtained.

Further, on a non-dark screen where the luminance level of the input video signal is not less than the set value, the pseudo random pulse generation circuit outputs a plurality of noise signals including a noise signal exceeding 0 level and a noise signal of 0 and negative level. And a correction addition circuit 5
Since 0 adds a plurality of noise signals output from the pseudo-random pulse generation circuit to the signal in the error diffusion processing circuit, even if the level of the input original pixel video signal is the same continuous value, the video output Terminal to display panel (for example, P
DP) can fluctuate to a video output signal (drive signal) to be output to the DP), and do not have the same continuous value. Therefore, it is possible to prevent (suppress) the occurrence of a pseudo pattern on the display panel.

Further, an input level detecting circuit is provided, and on a dark screen where the luminance level of the input video signal is lower than the set value, the pseudo random pulse generating circuit outputs a noise signal of 0 and a negative level of the plurality of noise signals. However, since this noise signal is added to the signal in the error diffusion processing circuit by the correction addition circuit, the noise signal added to eliminate the pseudo pattern becomes a bright point on a dark screen and stands out. Can be solved, and the image quality can be improved.

[Brief description of the drawings]

FIG. 1 is a block diagram showing an embodiment of a pseudo pattern processing circuit according to the present invention.

FIG. 2 is an explanatory diagram illustrating an operation of the pseudo-random pulse generation circuit of FIG. 1;

FIG. 3 is a block diagram of an error diffusion processing circuit of a pseudo halftone display device already proposed by the present applicant.

[Explanation of symbols]

28: error diffusion processing circuit, 30: video signal input terminal,
31: vertical addition circuit 32: horizontal addition circuit
33: Bit conversion circuit, 34: Video output terminal, 35
... Error detection circuit, 36 ... h line delay circuit, 37 ... d
Dot delay circuit, 38 ROM, 39 addition circuit,
40, 41 ... load circuit, 50 ... correction addition circuit, 52 ...
Pseudo random pulse generation circuit, 54 ... Pseudo noise input terminal, 60 ... Input level detection circuit, 62 ... Pseudo random pulse generation circuit.

──────────────────────────────────────────────────続 き Continuing on the front page (72) Inventor Junichi Onodera 1116, Suenaga, Takatsu-ku, Kawasaki, Kanagawa Prefecture Inside Fujitsu General Limited (72) Inventor Masayuki Kobayashi 1116, Suenaga, Takatsu-ku, Kawasaki, Kanagawa Prefecture Fujitsu General Limited (72) Inventor Hayato Denda 1116 Suenaga, Takatsu-ku, Kawasaki City, Kanagawa Prefecture Inside Fujitsu General Limited (56) References JP-A-7-64505 (JP, A) JP-A 8-307680 (JP, A) JP-A-5-114999 (JP, A) JP-A-7-288689 (JP, A) JP-A-8-204961 (JP, A) JP-A-7-121136 (JP, A) (JP, U) (58) Field surveyed (Int. Cl. ⁷ , DB name) G09G 3/28 G09G 3/36 G09G 5/10 G02F 1/133 575

Claims (5)

(57) [Claims] 1. A reproduction error addition circuit for adding a reproduction error generated in the past from an original pixel to an input n-bit original pixel video signal, and a diffusion output signal output from the reproduction error addition circuit is represented by m ( .Ltoreq.n-1) a bit conversion circuit for converting the signal into a bit signal and outputting the signal to the display panel, a corrected luminance level preset for luminance gradation correction of the display panel, and a diffusion output output from the reproduction error addition circuit. An error detection circuit that detects a difference from the signal, outputs the weighted weighted error signal, and a delay circuit that delays the error load output signal output from the error detection circuit by a predetermined pixel and outputs the error load output signal to the reproduction error addition circuit as a reproduction error. An input level detection circuit for detecting a luminance level of the input video signal, wherein a detection output of the input level detection circuit is equal to or more than a preset value. Sometimes, based on the pseudo noise signal, a noise signal exceeding at least 0 level and 0 and
Outputting a plurality of noise signals including a negative-level noise signal, and when the detection output is less than the set value, based on the pseudo-noise signal, 0 and the plurality of noise signals.
A pseudo-random pulse generation circuit that outputs a negative-level noise signal; and a correction addition circuit that adds a signal output from the pseudo-random pulse generation circuit to a signal in the error diffusion processing circuit. Pseudo pattern processing circuit. 2. The pseudo-random pulse generation circuit according to claim 1, wherein when a detection output of the input level detection circuit is equal to or more than a set value, three of + k, 0, and -k (k is a positive real number) based on a 2-bit pseudo noise signal. A noise signal of a three-level level is output, and when the detection output does not reach the set value, the noise signal of the three-level level of + k, 0, and -k is determined based on a 2-bit pseudo noise signal. 2. The pseudo-pattern processing circuit according to claim 1, wherein a noise signal of -k, 0 level is output. 3. The reproduction error adding circuit includes a vertical adding circuit and a horizontal adding circuit, and a correction adding circuit is inserted between the vertical adding circuit and the horizontal adding circuit. 3. The pseudo pattern processing circuit according to 1 or 2. 4. The pseudo-pattern processing circuit according to claim 1, wherein the reproduction error adding circuit comprises only one of the vertical direction adding circuit 31 and the horizontal direction adding circuit 32. 5. The pseudo-pattern processing circuit according to claim 1, wherein the display panel comprises a PDP or a liquid crystal display panel.