JP3232921B2 - Pseudo pattern processing circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a pseudo pattern processing circuit for efficiently removing a pseudo pattern in an error diffusion processing circuit in a display device such as a plasma display panel (PDP) or a liquid crystal display panel. .

[0002]

2. Description of the Related Art Recently, as a thin and lightweight display device, P
Attention has been paid to DP display devices. The drive system of this PDP display device is completely different from the conventional CRT drive system, and is a direct drive system using digitized video input signals. Therefore, the luminance gradation emitted from the panel surface is determined by the number of bits of the signal to be handled.

[0003] PDPs are AC type and DC having fundamental characteristics different from each other.
Type. Among them, AC-type PDPs have sufficient characteristics in terms of luminance and lifetime, but there are only reports on gradation display up to a maximum of 64 gradations at the prototype level. However, in the future, the address and display separation type driving method (ADS subfield method) will not be used.
A gradation method has been proposed.

In this AC driving method, as the number of gradations increases, the number of bits in an address period as a preparation period for lighting and emitting light in the panel within one frame period increases. And the maximum luminance decreases. As described above, the luminance gradation emitted from the panel surface is determined by the number of bits of the signal to be handled. Therefore, if the number of bits of the signal to be handled is increased, the image quality is improved, but the emission luminance is reduced, and conversely, the signal to be handled is reduced. If the number of bits is reduced, the light emission luminance increases, but the gradation display decreases and the image quality deteriorates.

Therefore, the applicant of the present invention has proposed a method as shown in FIG.
While reducing the number of bits of the output drive signal from the number of bits of the input signal, the grayscale error between the input signal and the light emission luminance is minimized, and even when video signals of the same level are continuously input, a pseudo pattern is generated. An error diffusion circuit 28 of a pseudo-halftone display device that can prevent occurrence of the error has been proposed.

In FIG. 2, on the output side of the load circuits 40 and 41 of the error detection circuit 35, a reproduction error E generated in the past by a pixel h lines before the original pixel A (i, j), for example, one line, is shown. The pixel is connected to the vertical direction addition circuit 31 via the h-line delay circuit 36 that outputs (i, j-1), and is a pixel that is d dots before the original pixel A (i, j), for example, one dot in the past. It is connected to a horizontal addition circuit 32 via a d-dot delay circuit 37 for outputting the generated reproduction error E (i-1, j).

[0007] The spread output signal obtained by incorporating the error by the vertical direction adder circuit 31 and the horizontal direction adder circuit 32 is sent to a bit conversion circuit 33, and the spread output signal quantized to n bits by the bit conversion circuit 33. With m (≦
n-1) bits and then output from the video output terminal 34 to the PDP.
Output as a drive signal.

In this state, when video signals of the same level are continuously input to the video signal input terminal 30, for example,
The 8-bit original pixel video signal is 55H, 55H,.
When the input is continuously made at the same level as H, the error load output values output from the load circuits 40 and 41 to the h-line delay circuit 36 and the d-dot delay circuit 37 become the same continuous values, respectively. There is a problem that the PDP displays a pseudo pattern that is a regular repeating pattern.

Therefore, in order to remove this pseudo pattern, the noise generated by a noise generating circuit 52 such as a pseudo random pulse generating circuit and the like and generated from a pseudo random pulse signal multiplied by ± K by an error load output multiplier 60 is further reduced. , Is added to the signal in the error diffusion circuit 28 via the correction addition circuit 50. Therefore, even if the levels of the input original pixel video signals are continuous and the same, the video output signal (drive signal) output from the video output terminal to the display panel (for example, PDP)
Fluctuates and does not become the same continuous value. Therefore, the generation of a pseudo pattern on the display panel is prevented (suppressed).
can do.

[0010]

When noise with a constant amplitude is added to eliminate a pseudo pattern by the above-described method, the regular pattern accompanying the error diffusion processing is diffused by the noise. However, when the video signal level is low, the noise is conspicuous.

An object of the present invention is to solve the problem that noise is conspicuous by adding a variable amplitude value of noise for eliminating a pseudo pattern in accordance with the input video signal level. Things.

[0012]

According to the present invention, there is provided a reproduction error addition circuit for adding a reproduction error generated in the past from an original pixel to an input video signal of an n-bit original pixel, and a reproduction error addition circuit. M (≦ n−1)
A bit conversion circuit 33 that converts the signal to a bit signal and outputs the signal to a display panel; and a difference between a corrected luminance level preset for luminance gradation correction of the display panel and a diffusion output signal output from the reproduction error addition circuit. An error detection circuit 35 for detecting, weighting and outputting the error load output signal, and a delay circuit for delaying the error load output signal output from the error detection circuit 35 by a predetermined pixel and outputting the same as a reproduction error to the reproduction error addition circuit. In the error diffusion circuit described above, a noise generation circuit 52 that generates a pseudo random pulse signal at a timing of a dot or a line unit, and multiplies an output signal of the noise generation circuit 52 by a factor of ± K (| K | <1). An error load output multiplier 60 to be output and a level of the input video signal are detected, and a coefficient of the error load output multiplier 60 is set according to the detected level. A level determining circuit 61 that, in the pseudo A pattern processing circuit, characterized in that the signal output from the error load output multiplier 60 formed by and a correction addition circuit 50 for adding to the video signal in the error diffusion circuit is there.

[0013]

The correction addition circuit 50 outputs the noise signal output from the noise generation circuit 52 and multiplied by ± K by the error load output multiplier 60 to the vertical addition circuit 31 for each dot or line.
Is added to the input signal at the output side. When the level of the input video signal changes The level of the input video signal is always detected by the level determination circuit 61. Then, in the range where the input level L is low, no noise is added, or noise multiplied by a coefficient corresponding to the input level L is added. If the input level L is above a certain value,
Add noise multiplied by a fixed factor.

When the levels of the input video signals are continuous and the same value Even if the levels of the original pixel video signals detected by the level determination circuit 61 are the same continuous values, the noise generation circuit 5
2 and a noise signal multiplied by. +-. K times by the error load output multiplier 60 makes continuous data fluctuate, thereby preventing a regular repeated pattern from being generated in the diffusion output. Therefore, it is possible to prevent (suppress) the occurrence of a pseudo pattern in the PDP.

[0015]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of a pseudo-pattern processing circuit according to the present invention will be described below with reference to FIG. The same parts as those in FIG. Reference numeral 30 denotes a video signal input terminal of an n-bit original pixel A (i, j). The video signal input terminal 30 passes through a vertical addition circuit 31, a correction addition circuit 50, a horizontal addition circuit 32, and The conversion circuit 33 performs processing for reducing the number of bits, and is connected to the video output terminal 34. The vertical direction adding circuit 31 and the horizontal direction adding circuit 32 constitute a reproduction error adding circuit.

Reference numeral 52 denotes a noise generating circuit which generates a pseudo random pulse signal at a timing of a dot or a line. The noise generation circuit 52 is composed of a primitive polynomial circuit and an M-sequence code generation circuit. The primitive polynomial circuit is composed of, for example, a 19th-order primitive polynomial circuit mainly composed of 19 flip-flop circuits and three addition circuits, and has a period (2 ¹⁹ -1) (that is, a period 524,287).
And outputs a random pulse signal of H (for example, 1) and L (for example, 0). Here, the period 52
4,287, the length of one cycle is 52 of the unit pulse period.
4,287 times as long (period). Such a noise signal has a repetition of a certain cycle, but since the cycle is sufficiently long, it can be regarded as a random pulse signal.

The noise generation circuit 52 has a function of ± K (| K |
<1) It is coupled to the correction addition circuit 50 via a correction coefficient circuit 60 for multiplying and outputting the multiplied coefficient. Further, a characteristic level determination circuit 61 of the present invention is interposed between the video signal input terminal 30 and the error load output multiplier 60. The level determination circuit 61 is for varying the amplitude value of the noise for eliminating the pseudo pattern according to the input video signal level, and is set, for example, as shown in the following table. Input level Error load output multiplier 60 L = 0-3 K = 0 L = 4-7 K = 0.1 L = 8-9 K = 0.2 L = 12-15 K = 0.3 L = 16- 19 K = 0.4 L = 20 to 23 K = 0.5 L = 24 to 27 K = 0.6 L = 28 or more Fixed to K = 0.7 Note that ± of ± K is from the noise generation circuit 52. Can be switched by ± of the noise. The input level L and the coefficient K of the error load output multiplier 60 change stepwise, but are not limited to the above specific example.

The other circuit configuration is the same as that of FIG. 2, and an error detection circuit 35 is connected to the output side of the horizontal addition circuit 32. The error detection circuit 35 stores the correction luminance level data for luminance gradation correction in advance.
An addition circuit 3 for calculating an OM 38 and a sum of a corrected luminance level set in the ROM 38 and a diffusion output signal output from the horizontal direction addition circuit 32 to output an error detection signal;
9 and a load circuit 4 for outputting an error load signal obtained by weighting the error detection signal output from the adder circuit 39 with a predetermined weight.
It consists of 0 and 41.

The load circuits 40 and 4 of the error detection circuit 35
The output side of 1 is connected to the vertical direction addition circuit 31 and the horizontal direction addition circuit 32 via an h line delay circuit 36 and a d dot delay circuit 37, respectively. The h-line delay circuit 36 delays the error load output signal output from the load circuit 40 by h lines, and outputs the original pixel A (i,
j), a reproduction error (eg, a reproduction error E (i, j-1) generated in the past by one line when h = 1) for a pixel h lines before is output to the d-dot delay circuit 3.
Numeral 7 is a signal for delaying the error load output signal output from the load circuit 41 by d dots.
The reproduction error for the pixel before the dot (for example, when d = 1, the reproduction error E (i−1,
j)) is output.

Next, the operation of the embodiment shown in FIG. 1 will be described. Density modulation is performed using two luminance gradations to create a visually pseudo gradation in a small area having a certain spread, thereby obtaining multiple gradations. This will be described in more detail. A (i, j): input pixel value of the current processing target A (i, j-1): input pixel value of one line before (when h = 1) A (i-1, j): one dot before Input pixel value (when d = 1) δv: Error load value of diffusion output pixel from the previous line δh: Error load value of diffusion output pixel from the previous line The signal and the data from the ROM 38 are summed by an adding circuit 39 to obtain an error output signal.

This error output signal is sent to the load circuits 40 and 41
, The weighted error load output signals δv and δh of Kv (<1) and Kh (= 1−Kv), respectively, and the one-line delay circuit 36 (when h = 1) and the one-dot delay circuit 37
(When d = 1), incorporated into the original pixel A (i, j) by the vertical direction addition circuit 31 and the horizontal direction addition circuit 32, and C (i, j) = A (i, j) + δv + δh. Become.

Note that C (i, j): the diffusion output pixel value of the current processing target δv = Kv × [f ｛C (i, j−1)｝ − Br] δh = Kh × [f ｛C (i− [1, j) {-Br] f {C (i, j)}: Corrected luminance for C (i, j) Br: Light emission luminance level.

The diffused output signal into which the error is incorporated and diffused is sent to the bit conversion circuit 33.
The spread output signal quantized by n bits at m is given by m (≦ n
-1) Convert to bits and output from video output terminal 34. In this way, the original video input signal is diffused by incorporating errors, and a signal having a smaller number of bits than the original video input signal can obtain a smooth response without lowering the light emission luminance.

Next, the correction addition circuit 50 outputs the noise signal output from the noise generation circuit 52 and multiplied by ± K by the error load output multiplier 60 on an output side of the vertical addition circuit 31 for each dot or line. It is added to the input signal. The case where the level of the original pixel video signal input to the video signal input terminal 30 changes and the case where the level is continuously the same will be described separately.

(1) When the level of the input video signal changes The level of the input video signal is always detected by the level determination circuit 61. For example, it is assumed that the input level L is divided into 128 steps, and if L = 0 to 3, K =
0, ie no noise is added. If L = 4-7, add noise multiplied by K = 0.1. Similarly, K = 0.2 when L = 8-9, K = 0.3 when L = 12-15, K = 0.4 when L = 16-19, L =
K = 0.5 for 20-23, K for L = 24-27
= 0.6, and noise fixed at K = 0.7 is added for L = 28 or more.

(2) When the Levels of the Input Video Signals are Continuous and the Same Value Even if the levels of the original pixel video signals detected by the level determination circuit 61 are the same continuous values, the noise generation circuit 5
2 and a noise signal multiplied by. +-. K times by the error load output multiplier 60 makes continuous data fluctuate, thereby preventing a regular repeated pattern from being generated in the diffusion output. Therefore, it is possible to prevent (suppress) the occurrence of a pseudo pattern in the PDP.

At this time, the noise generation circuit 52 generates a random pulse signal at a period of a predetermined length (for example, periods 524 and 287), and the number of appearances of H (for example, 1) and L (for example, 0) within this period. Are equal, the sum of the data when the correction addition is performed during the pulse number period of 524 and 287 is equal to the sum of the data when the correction addition is not performed, and the correction addition of the image data is performed. The amount is ± 0.

In the above embodiment, the reproduction error adding circuit is composed of the vertical direction adding circuit 31 and the horizontal direction adding circuit 32,
Although the correction addition circuit 50 is inserted between the vertical addition circuit 31 and the horizontal addition circuit 32, the present invention is not limited to this. For example, the reproduction error adding circuit may be constituted by only one of the vertical direction adding circuit 31 and the horizontal direction adding circuit 32. Further, the correction addition circuit 50 may be provided at an appropriate place where a noise signal can be added to the video signal in the error diffusion circuit 28. For example, in FIG. 1, the video signal input terminal 30 and the vertical direction addition circuit 31
During or between the output side of the horizontal addition circuit 32 and may be inserted a correction addition circuit 50.

In the above embodiment, the case where the display panel is a PDP has been described. However, the present invention is not limited to this, and can be applied to a case where a display panel other than the PDP (for example, a liquid crystal display panel) is used.

[0030]

As described above, the pseudo pattern processing circuit according to the present invention comprises a reproduction error adding circuit (for example, a vertical direction adding circuit 31 or a horizontal direction adding circuit 32), a bit conversion circuit 33, an error detecting circuit 35, and a delay circuit. Since the error detection circuit 35 detects and weights the sum of the corrected luminance level and the diffused output signal and outputs the result to the delay circuits 36 and 37, the error detection circuit 35 has a higher level than the original video input signal. With a signal of a small number of bits, the emission luminance does not decrease, and
A smooth response is obtained.

A noise generating circuit 52 for generating a pseudo-random pulse signal at a timing of a dot or a line unit, and ± K (|
K | <1) An error load output multiplier 60 for multiplying and outputting the coefficient, and a level for detecting the level of the input video signal and setting the coefficient of the error load output multiplier 60 according to the detected level. Since there are provided a judgment circuit 61 and a correction addition circuit 50 for adding a signal output from the error load output multiplier 60 to a video signal in the error diffusion circuit, a circuit for erasing a pseudo pattern is provided. By adding a variable value of the noise amplitude value according to the input video signal level, the problem that the noise is noticeable can be solved.

Further, the correction addition circuit 50 adds the noise signal generated by the noise generation circuit 52 and multiplied by ± K by the error load output multiplier 60 to the video signal in the error diffusion circuit 28, so that it is input. Even if the level of the original pixel video signal is continuous and the same value, it can fluctuate to the video output signal (drive signal) output from the video output terminal to the display panel (for example, PDP), and does not become the same continuous value. Therefore, it is possible to prevent (suppress) the occurrence of a pseudo pattern on the display panel.

[Brief description of the drawings]

FIG. 1 is a block diagram showing an embodiment of a pseudo pattern processing circuit according to the present invention.

FIG. 2 is a block diagram of an error diffusion circuit of a pseudo halftone display device already proposed by the present applicant.

[Explanation of symbols]

Reference numeral 30: video signal input terminal, 31: vertical direction addition circuit, 3
2: horizontal addition circuit, 33: bit conversion circuit, 34:
Video output terminal, 35: error detection circuit, 36: h line delay circuit, 37: d dot delay circuit, 38: ROM, 3
9 addition circuits, 40, 41 load circuits, 50 correction addition circuits, 52 noise generation circuits, 60 error load output multipliers, 61 level determination circuits.

──────────────────────────────────────────────────続 き Continued on the front page (72) Inventor Junichi Onodera 1116 Suenaga, Takatsu-ku, Kawasaki, Kanagawa Prefecture Inside of Fujitsu General Limited (72) Inventor Hayato Denda 1116, Suenaga, Takatsu-ku, Kawasaki, Kanagawa Fujitsu General Limited (56) References JP-A-7-288689 (JP, A) JP-A-5-167837 (JP, A) JP-A-5-323921 (JP, A) JP-A-2-116136 (JP, U) (58) Field surveyed (Int.Cl. ⁷ , DB name) G09G 3/20 641 G02F 1/133 575 G09G 3/28 G09G 3/36

Claims (5)

(57) [Claims] 1. A reproduction error addition circuit for adding a reproduction error generated in the past from an original pixel to an input n-bit original pixel video signal, and a diffusion output signal output from the reproduction error addition circuit is represented by m ( .Ltoreq.n-1) a bit conversion circuit 33 for converting the signal into a bit signal and outputting the signal to the display panel; a correction luminance level preset for luminance gradation correction of the display panel; and a diffusion output from the reproduction error addition circuit. An error detection circuit 3 which detects a difference from an output signal, weights the difference, and outputs the result.
5 and a delay circuit that delays the error load output signal output from the error detection circuit 35 by a predetermined number of pixels and outputs it as a reproduction error to the reproduction error addition circuit. A noise generation circuit 52 that generates a pseudo-random pulse signal;
The output signal of the noise generation circuit 52 is ± K (| K | <
1) An error load output multiplier 60 for multiplying and outputting the multiplied coefficient
A level determination circuit 61 for detecting a level of the input video signal and setting a coefficient of the error load output multiplier 60 according to the detected level;
And a correction addition circuit 50 for adding a signal output from the error diffusion circuit to a video signal in the error diffusion circuit. 2. A level judging circuit 61 sequentially and stepwise sets coefficients of an error load output multiplier 60 so that the level of a noise signal of a noise generating circuit 52 does not exceed the level of a detected input video signal. 2. The pseudo-pattern processing circuit according to claim 1, comprising: 3. The reproduction error adding circuit includes a vertical adding circuit 31 and a horizontal adding circuit 32, and a correction adding circuit 50 is inserted between the vertical adding circuit 31 and the horizontal adding circuit 32. A pseudo pattern processing circuit according to claim 1 or 2. 4. The pseudo-pattern processing circuit according to claim 1, wherein the reproduction error adding circuit comprises only one of the vertical direction adding circuit 31 and the horizontal direction adding circuit 32. 5. The pseudo-pattern processing circuit according to claim 1, wherein the display panel comprises a PDP or a liquid crystal display panel.