JP3324313B2 - Display driving method and apparatus - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method and apparatus for driving a display in which one dot is composed of a plurality of pixels and halftone display is performed by a plurality of pixels in one dot to obtain a high-density and fine image. It is about.

[0002]

2. Description of the Related Art Recently, as a thin and lightweight display device, P
DP (plasma display panel) has attracted attention. The driving method of this PDP is completely different from the conventional CRT driving method, and is a direct driving method using digitized video input signals. Therefore, the luminance gradation emitted from the panel surface is determined by the number of bits of the signal to be handled. PDP has AC drive type and DC with different basic characteristics.
Although there are two types of driving type, the DC driving type PDP has been reported to improve the luminance and life, which have already been issues, and is progressing toward practical use.

[0003] However, in the AC drive type PDP, sufficient characteristics have been obtained in terms of luminance and life, but as for gradation display, there has been only a report on a trial production level of up to 64 gradation display. However, recently, a method of 256 gradations by an address / display separation type driving method (ADS subfield method) has been proposed. FIGS. 8A and 8B show a drive sequence and a drive waveform of a PDP (plasma display panel) used in this method.

In FIG. 8A, one frame has a relative luminance ratio of 1, 2, 4, 8, 16, 32, 64, 128.
, And 256 gradations are displayed by the combination of the luminances of the eight screens. In FIG. 8 (b), each subfield has a refreshed 1
It consists of an address period for writing data for the screen and a sustain period for determining the luminance level of the subfield. In the address period, first, wall charges are initially formed on each pixel at the same time for the entire screen, and then a sustain pulse is applied to the entire screen to perform display. The brightness of the subfield is proportional to the number of sustain pulses and is set to a predetermined brightness. In this way, 256 gradation display is realized.

Since the address period is constant irrespective of the size of the sustain period, in the above-described AC driving method, the more the number of gradations is increased, the more the preparation period for lighting and emitting the panel within one frame period. Since the number of bits in the address period increases, the sustain period as the light emitting period becomes relatively short, and the maximum luminance decreases. As described above, the luminance gradation emitted from the panel surface is determined by the number of bits of the signal to be handled. Therefore, if the number of bits of the signal to be handled is increased, the image quality is improved, but the emission luminance is reduced, and conversely, the signal to be handled is If the number of bits is reduced, the light emission luminance increases, but the gradation display decreases and the image quality deteriorates.

The error diffusion process for minimizing the shading error between the input signal and the emission luminance while reducing the number of bits of the output drive signal from the number of bits of the input signal is a process for expressing a pseudo halftone. , Which is used when expressing gradation with a small number of gradations. FIG. 6 shows a conventional general error diffusion processing circuit. In this circuit, the video signal input terminal 30
, A video signal of an original pixel Ai, j of n (for example, 8) bits is input, passed through a vertical direction addition circuit 31 and a horizontal direction addition circuit 32, and further converted into a bit number m
The PDP emits light from the video output terminal 34 via the PDP driving circuit by performing a process of reducing the number of bits to (for example, 4) bits.

The error diffusion signal from the horizontal addition circuit 32 is compared with data stored in advance in the ROM 38 of the error detection circuit 35, and the sum is obtained by the adder 39 to be sent to the error load circuits 40 and 41. An h-line delay circuit 36 that outputs a pixel that is h lines ahead of the original pixel Ai, j, for example, a reproduction error Ej-1 that occurred one line in the past, and outputs the error detection output. Of the original pixel A
It is added to the horizontal addition circuit 32 via a d-dot delay circuit 37 that outputs a pixel d dots before i and j, for example, a reproduction error Ei-1 that occurred one dot in the past.
The coefficients in the error load circuits 40 and 41 are generally set so that the sum of all becomes 1.

As a result, the output terminal of the bit conversion circuit 33 instantaneously outputs a light emission luminance level represented by 4 bits as shown by a solid line staircase, as shown in FIG. Actually, the upper and lower emission luminance levels of the solid line are output alternately at a predetermined ratio, so that they are recognized in an averaged state and become a corrected luminance line of y = x like a dotted line.

[0009]

In the driving method shown in FIG. 8A, one frame is divided into eight subfields,
Although six gradations are used, the image quality is improved by increasing the number of gradations. However, although the image quality is improved, the light emission luminance is reduced.
Conversely, as shown in FIG. 7A, if one frame is composed of six subfields and the number of bits of a signal to be handled is reduced,
The emission luminance increases. As shown in FIG. 7B, if one frame is composed of four subfields and the number of bits of a signal to be handled is reduced, the tendency is further increased. The halftone display technology as described above creates a halftone by diffusing the brightness in each of the vertical and horizontal directions, and thus has a problem in that the resolution is reduced and a unique pattern appears.

SUMMARY OF THE INVENTION An object of the present invention is to provide a driving method and apparatus which do not cause a reduction in resolution even when the number of bits of a signal to be handled is reduced, and in which a unique pattern does not appear.

[0011]

According to the present invention, a halftone display section detects a luminance level of a quantized input original pixel video signal and selects a luminance pattern of a plurality of pixels in which one dot is set in advance. And a drive unit 43 having a low number of display gradations for displaying halftones in each pixel based on the pattern selected by the halftone display unit 42.

[0012]

One dot of an original pixel video signal input after quantization is composed of a plurality of pixels, for example, four pixels. Assuming that the video input level is at point a, which is a quarter from point A, it is determined by the luminance level determination circuit 44, and a pattern corresponding to point a is selected from the patterns of the pattern generation circuit 46.
The halftone display output at this time is a combination of three pixels for A and one pixel for B. Similarly, assuming that the point is located at a point b which is a half from the point A, the halftone display output is a combination of two pixels for A and two pixels for B, and three quarters from point A.
, The halftone display output is such that A is 1
Assuming that pixel and B are a combination of three pixels and are located at point d (point B), the halftone display output has no A,
B becomes 4 pixels. As described above, the halftone display output pattern corresponding to the video input level is selected from the pattern of four pixels per input dot, and the PDP 10 is displayed via the driving unit 43 according to this pattern.

[0013]

DESCRIPTION OF THE PREFERRED EMBODIMENTS The basic concept of the present invention is as follows.
Conventionally, the decrease in resolution in the halftone display technology is due to the fact that the diffusion area of the halftone display technology is wider than the required number of dots (resolution). This is because as long as the display driving method of required number of dots = number of pixels is adopted,
It is theoretically impossible to solve. However, at present, the size of the display is increasing, and accordingly, the size of one dot is also increasing. For example, the size of one dot of a 21-inch PDP is 0.66 mm square,
The size of one dot of DP is 1.08 mm square.

Therefore, in the present invention, a means for displaying one dot by a plurality of pixels is employed to realize a display configuration in which the required number of dots <the number of pixels, and an attempt is made to produce a halftone using the pixels in one dot. . As described above, if a halftone is created and displayed by the pixels within one dot, the halftone can be displayed without expanding the halftone display area beyond the necessary number of dots (resolution). For this reason, on the drive circuit side, it is possible to obtain a high-brightness and fine image with a halftone display technology that secures a necessary number of dots (resolution) while reducing the number of bits and increasing the emission luminance. is there.

Hereinafter, as an embodiment of the present invention, 4 dots per dot are used.
A display for displaying a pixel will be described with reference to the drawings. In FIG. 1, reference numeral 30 denotes an n-bit original pixel Ai,
A video signal input terminal of j, and a video of a required number of dots is transmitted to the video signal input terminal 30. For example, V
It is 640 horizontal x 480 vertical dots equivalent to GA. The video signal input terminal 30 is connected to the drive unit 43 via the halftone display unit 42 of the present invention, and is further connected to the PDP 10.

The halftone display section 42 includes a luminance level determining circuit 44 for determining the luminance level of the input video signal,
It comprises a pattern generating circuit 46 for storing and generating a pattern corresponding to the luminance in advance, and a pattern selecting circuit 45 for selecting a pattern of the pattern generating circuit 46 based on the output of the luminance level discriminating circuit 44. For example, a dither method is used as a halftone binary display method in the pattern generation circuit 46. The dither method includes an independent determinant and a conditional determinant.The independent determinant includes a random dither method and an organized dither method.The conditional determinant includes an error diffusion method and the like. There are an improved method, a method of allocating black pixels in a region, a method of controlling an average value and an outline, and a region adaptive processing method. The invention is not limited to these dither methods, and any halftone display method such as a density pattern method is selectively used. As will be described later, when one dot of the video input signal is displayed as a half-tone output as a four-pixel display that is equally divided vertically and horizontally, the driving unit 43 sets the number of display gradations so as to drive each pixel. The lower one is used.

In the above configuration, the video signal of the original pixel input to the video signal input terminal 30 is
2 is sent to the luminance level determination circuit 44. The luminance level determination circuit 44 determines the input level of the video input signal. Here, the video signal of the original pixel input to the video signal input terminal 30 is, as shown in FIG.
It is assumed that the number of bits of a signal to be handled is reduced by, for example, configuring the number of subfields or configuring one frame with four subfields as illustrated in FIG. Therefore, the luminance level has a step-like characteristic having a larger step than in the case of FIG.

FIG. 2 shows a characteristic diagram in which one frame is composed of four subfields, similarly to FIG. 7B. In addition, it is assumed that one dot of the video input signal is divided into two equal parts in the vertical and horizontal directions as a halftone output, thereby displaying four pixels.
In FIG. 2, the distance between the video input levels A and B is 4 points.
The points are equally divided, and points A, B, C, and D are each one-quarter, one-half, three-quarters, and B from point A.

(1) Assuming that the video input level from the video signal input terminal 30 is at a quarter of point a from the point A as shown in FIG. 3A, it is determined by the luminance level determination circuit 44. Then, the determination signal is sent to the pattern selection circuit 45.
In the pattern selection circuit 45, a pattern generation circuit 46
The pattern corresponding to the point a from the
Select from the following patterns. The halftone display output at this time is a combination of three pixels for A and one pixel for B.

(2) Assuming that the video input level from the video signal input terminal 30 is at a half point b from the point A as shown in FIG. 3B, it is determined by the luminance level determination circuit 44. Then, the determination signal is sent to the pattern selection circuit 45.
In the pattern selection circuit 45, a pattern generation circuit 46
The pattern corresponding to the point b from
Select from the following patterns. The halftone display output at this time is a combination of two pixels for A and two pixels for B. A,
Although A, B, and B are arranged as crosses in the figure, they can be arranged as appropriate such as horizontal and vertical.

(3) Assuming that the video input level from the video signal input terminal 30 is at point c, which is three quarters from point A, as shown in FIG. Then, the determination signal is sent to the pattern selection circuit 45.
In the pattern selection circuit 45, a pattern generation circuit 46
A pattern corresponding to the point c from
Select from the following patterns. The halftone display output at this time is a combination of one pixel for A and three pixels for B.

(4) Assuming that the video input level from the video signal input terminal 30 is at point d (point B) as shown in FIG. 3D, the brightness level is determined by the luminance level determination circuit 44, and the determination is made. The signal is sent to the pattern selection circuit 45. In the pattern selection circuit 45, a pattern corresponding to the point d from the pattern generation circuit 46 is selected from the patterns of the pattern generation circuit 46. In the halftone display output at this time, A disappears and B becomes four pixels.

As described above, the halftone display output pattern corresponding to the video input level is selected from the pattern having a configuration of four pixels per input dot, and the PDP 10 is displayed via the drive unit 43 according to this pattern.

In the above embodiment, as shown in FIG. 4A, one dot of the video input signal is displayed as a halftone output in a four-pixel display which is equally divided vertically and horizontally into two parts. However, the present invention is not limited to this. Instead, as shown in FIG. 4 (b), one dot of the video input signal can be displayed as a halftone output in six pixels divided into two equal parts vertically and three equal parts horizontally, or as shown in FIG. 4 (c). In addition, a three-pixel display in which one dot of a video input signal is equally divided into three in the horizontal direction as a halftone output may be used, and the vertical and horizontal distribution ratios can be arbitrarily selected.

[0025]

According to the present invention, one dot of an original pixel video signal which has been quantized and input is constituted by a plurality of pixels, and halftone display is performed by a plurality of pixels within one dot. This has the effect that the resolution does not decrease even if the number is reduced, and that a unique pattern does not appear.

[Brief description of the drawings]

FIG. 1 is a block diagram showing one embodiment of a display driving device according to the present invention.

FIG. 2 is an enlarged characteristic diagram illustrating a relationship between a correction luminance line and a light emission luminance level.

FIG. 3 is an explanatory diagram of the functions of pixel conversion and halftone display according to the present invention.

FIG. 4 is a diagram illustrating a plurality of embodiments of pixel conversion.

FIG. 5 is a characteristic diagram of a driving signal versus a light emission luminance level according to a conventional circuit.

FIG. 6 is a block diagram showing a conventional display driving device.

FIG. 7A is a driving sequence in a 64-gradation method, and FIG. 7B is a driving sequence in a 32-gradation method.

FIG. 8 is a drive sequence and a drive waveform diagram in a 256-gradation method.

[Explanation of symbols]

10 ... PDP (Plasma Display Panel), 3
0: video signal input terminal, 31: vertical direction addition circuit, 32
... Horizontal adder, 33 bit converter, 34 output terminal, 35 error detector, 36 h line delay circuit, 37 d dot delay circuit, 38 memory, 39 adder, 40 error load Circuit, 41 ... Error load circuit, 42
.., A halftone display section, 43, a drive section, 44, a luminance level discriminating circuit, 45, a pattern selection circuit,

──────────────────────────────────────────────────の Continued on the front page (51) Int.Cl. ⁷ Identification symbol FI G09G 3/28 G09G 3/28 K (72) Inventor Masayuki Kobayashi 1116 Suenaga, Takatsu-ku, Kawasaki City, Kanagawa Prefecture Inside Fujitsu General Limited ( 72) Inventor Hayato Denda 1116 Suenaga, Takatsu-ku, Kawasaki City, Kanagawa Prefecture Inside Fujitsu General Limited (72) Inventor Seiji Matsunaga 1116 Suenaga, Takatsu-ku, Kawasaki City, Kanagawa Prefecture Inside Fujitsu General Limited (56) References JP JP-A-5-224623 (JP, A) JP-A-58-123587 (JP, A) JP-A-2-81091 (JP, A) JP-A-5-323283 (JP, A) JP-A-63-109497 (JP) JP-A-8-234705 (JP, A) JP-A-6-180558 (JP, A) JP-A-4-356095 (JP, A) JP-A-57-144590 (JP, A) (58) Fields surveyed (Int.Cl. ⁷ G09G 3/20 641 G09G 3/20 642 G09G 3/28 G09G 3/36

Claims (4)

(57) [Claims] 1. Quantization is performed to form one frame from original pixels.
Inputs a video signal with a reduced number of subfields forming,
By forming one dot of this video signal with a plurality of pixels, a display having a larger number of output pixels than the number of input pixels is provided, and halftone display is performed by a combination of a plurality of display pixels corresponding to the one dot. Display driving method. 2. One frame is quantized to form one frame from original pixels.
Input a video signal with a reduced number of subfields
A video signal input terminal 30, a halftone display unit 42 for detecting a luminance level of the video signal input to the video signal input terminal 30 and selecting a predetermined one dot luminance pattern of a plurality of pixels; , it was used to halftone display in each pixel based on the pattern selected by the halftone display unit 42
Te, a display driving apparatus characterized by number of display gradations is formed by and a drive <br/> pivot portion 43 consisting of lower than inlet Chikarakai tone number. 3. A halftone display section 42 includes: a luminance level determining circuit 44 for determining a luminance level of an input video signal; a pattern generating circuit 46 for storing and generating a pattern corresponding to luminance in advance; The display driving device according to claim 2, further comprising a pattern selection circuit (45) for selecting a pattern of the pattern generation circuit (46) based on an output of the circuit (44). 4. A dither method is used as a halftone binarization display method in the pattern generation circuit 46. One dot of a video input signal is divided into two equal parts vertically and horizontally as a halftone output. The display drive according to claim 3, wherein
Motion device.