JPH09237060A - Intermediate tone display circuit of display device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To make a pattern of a lattice state inconspicuous by making halftone processing patterns opposite to each other when moving amount in one frame of an animation is an odd number. SOLUTION: Signals of patterns 1, 2 are switched whenever a frame synchronizing signal is inputted to a switching circuit 20, when the least significant bit of a (n) bit input video signal is '1', it is added to a signal of upper N-1 bits, outputted to a plasma display panel (PDP) 14, pseudo-intermediate tone display is performed. In this case, an odd number/even number discrimination circuit 34 discriminating whether the moving amount of one frame of an animation is an odd number dot or not and an AND circuit 30 in which opening and closing is controlled by this discriminated output is provided, when the moving amount of an animation is an odd number dot, the AND circuit 30 is closed and a frame synchronizing signal to the switching circuit 20 is cut off, a halftone processing pattern added to a n-1 bit signal succeeds a pattern of one side of patterns 1, 2, the pattern 1 is replaced by the pattern 2 for each frame of an animation, the halftone processing patterns are not matched with each other.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a digital display device having a non-linear gradation characteristic such as a PDP (plasma display panel) or an LCD (liquid crystal display panel), in which the least significant bit of an n-bit input video signal is set. The present invention relates to a halftone display circuit for performing halftone display by performing pseudo halftone processing.

[0002]

2. Description of the Related Art Recently, PDPs have attracted attention as thin and lightweight display devices. The driving method of this PDP is completely different from the conventional CRT driving method, and is a direct driving method using digitized video input signals. Therefore, the luminance gradation emitted from the panel surface is
It is determined by the number of bits of the signal to be handled.

PDPs are AC type and DC type which have different basic characteristics.
Type. In the AC type PDP, there was only a report on the gradation display up to a maximum of 64 gradations at the prototype level, but a future 256 gradation method using the address / display separation type driving method (ADS subfield method) has been proposed. I have.

One frame (or one field) in the ADS subfield method is composed of eight subfields having relative luminance ratios of, for example, 1, 2, 4, 8, 16, 32, 64, and 128. Display of 256 gradations is performed by a combination of screen luminances. Each subfield is composed of an address period in which data for one refreshed screen is written and a sustain period for determining a luminance level of the subfield. In the address period, first, wall charges are initially formed on each pixel at the same time for the entire screen, and then a sustain pulse is applied to the entire screen to perform display. The brightness of the subfield is proportional to the number of sustain pulses and is set to a predetermined brightness. In this way 2
56 gradation display is realized.

In the above-described AC driving method, as the number of gradations increases, the number of bits in an address period as a preparation period for lighting and emitting light in the panel within one frame period increases. The period becomes relatively short, and the maximum luminance decreases.

As described above, the luminance gradation emitted from the panel surface is determined by the number of bits of the signal to be handled. Therefore, if the number of bits of the signal to be handled is increased, the image quality is improved, but the emission luminance is reduced. If the number of bits of the signal to be handled is reduced, the light emission luminance increases, but the gradation display decreases and the image quality deteriorates.

A pseudo intermediate for reducing the number of bits of the output drive signal more than the number of bits of the input signal and not lowering the light emission brightness, and minimizing the difference between the input signal and the light emission brightness (for example, shading error). The toning process is used when expressing light and shade with a small number of gradations.

Conventionally, the halftone processing circuit of the display device as described above has been constructed, for example, as shown in FIG. That is, the upper (n-) of the n (eg, n = 8) -bit video signal input to the video signal input terminal 10 is input.
1) The bit is input to the adder circuit 12, and the adder circuit 1
The output side of 2 is connected to the PDP 14 as a display panel. FIG. 4 generated by the pattern 1 generation circuit 16
The signal of pattern 1 as shown in FIG. 2B and the signal of pattern 2 as shown in FIG. 2C generated by the pattern 2 generation circuit 18 are input to the switching circuit 20.

By controlling the switching of the switching circuit 20 by the frame synchronization signal input to the control signal input terminal 22, the signals of patterns 1 and 2 are switched and output for each frame, and this output signal is input with n bits. When the least significant bit of the video signal is "1", it is input to the adder circuit 12 through the AND circuit 24 which is opened, and the high order (n
-1) It was added to the bit signal and output to the PDP 14 for pseudo-halftone display.

As shown in FIG. 4B, the pattern 1 is P
Display screen of DP14 2x2 (when M = 2 and N = 2)
In the unit block UB divided in dot units, lighting dots D1 (displayed in a rectangular area without parallel diagonal lines in the figure) and non-lighting dots D0 (displayed in a rectangular area with parallel diagonal lines in the figure) are arranged alternately. Has been done. Pattern 2 is
As shown in FIG. 4C, the lighting dots and the non-lighting dots of pattern 1 are set in a reverse arrangement.

[0011]

However, FIG.
In the conventional example shown in (a), when the least significant bit of the video signal input to the input terminal 10 is "1", the signal added to the adder circuit 12 via the AND circuit 24 for pseudo halftone display is displayed. Since the pattern is switched for each frame between the pattern 1 shown in FIG. 4B and the pattern 2 shown in FIG. 4C, in the case of a still image or even in a moving image, the horizontal direction or the vertical direction in one frame. There is no problem when the amount of movement in the direction is an even number of dots, but the problem is that a grid pattern may be noticeable on the screen when the amount of movement in the horizontal or vertical direction in one frame in a moving image is an odd number of dots. was there.

For example, in the case of a still image SG, FIG.
As shown in (a), if the halftone processing pattern of frame 1 is pattern 1, the halftone processing pattern of frame 2 one frame after that becomes pattern 2.
Even if the patterns 1 and 2 are exchanged for each frame, the lattice-like pattern does not stand out. Further, in the case of the moving image DG as well, in the case where the amount of horizontal movement in one frame is 2 dots (the same applies when the number of dots is an even number), halftone processing of the moving image DG in frames 1 and 2 is performed as shown in FIG. Since the patterns do not match and are opposed to each other, the grid pattern is not conspicuous. However, when the amount of movement in the horizontal direction in one frame of the moving image DG is 1 dot (the same applies when the number of odd dots is the same), the halftone processing of the moving image DG in frames 1 and 2 is performed as shown in FIG. 5C. There is a problem in that the patterns match and the grid pattern becomes conspicuous.

The present invention has been made in view of the above problems, and in a display device such as a PDP or LCD, the amount of movement in one frame of a moving image in the horizontal direction or the vertical direction is an odd dot (for example, 1 dot). ), Or when the difference between the horizontal and vertical motion amounts in one frame of the moving image is an odd number of dots (for example, one dot), it is necessary to prevent the grid pattern from becoming conspicuous in the halftone processing. It is intended.

[0014]

The invention according to claim 1 is
The display screen of the display panel is M × N (M × N ≧ 2)
A signal of pattern 1 in which lit dots and unlit dots are alternately arranged in a unit block divided in dot units, and a signal of pattern 2 in which lit dots and unlit dots of pattern 1 are arranged in reverse are generated, The signals of patterns 1 and 2 are switched and output every time the frame synchronization signal is input to the switching circuit. When the least significant bit of the n-bit input video signal is "1", this output signal is higher than the input video signal. (N
-1) In a halftone display circuit of a display device that adds a bit signal and outputs the result to a display panel to display a pseudo halftone, a horizontal motion amount in one frame of a moving image on the display screen of the display panel is odd. It is provided with a motion amount determination circuit for determining whether or not it is a dot, and a gate circuit in which a frame synchronization signal is inserted in a line input to a switching circuit and opening / closing is controlled by a determination output of the motion amount determination circuit. It is characterized by that.

When the amount of horizontal movement in one frame of a moving image is an odd number of dots, the gate circuit is closed by the determination output (for example, "0") of the movement amount determination circuit.
The frame sync signal to the switching circuit is cut off. Therefore, even when the least significant bit of the n-bit input video signal is "1", the halftone processing pattern added to the signal of the upper (n-1) bits of this input video signal is a pattern for each frame. Since one pattern is continued without switching from one of 1 and 2 to the other, the halftone processing patterns before and after the movement of one frame do not match and are opposed to each other, and the grid pattern is not conspicuous.

If the amount of horizontal movement in one frame of a moving image is not an odd number of dots (for example, even dots or zero dots (for example, a still image)), it is determined by the determination output (for example, "1") of the movement amount determination circuit. Since the gate circuit is opened, the frame synchronization signal is input to the switching circuit and n
When the least significant bit of the bit input video signal is "1", the halftone processing pattern added to the signal of the upper (n-1) bits of this input video signal is switched between patterns 1 and 2 for each frame. The halftone processing patterns before and after moving by one frame do not match and are opposed to each other, so that the grid pattern is not conspicuous.

According to a second aspect of the present invention, the motion amount determination circuit according to the first aspect of the invention is replaced with a motion amount determination circuit which determines whether or not the vertical direction motion amount in one frame of a moving image is an odd dot. It has a different configuration. With this configuration, when the amount of movement in the vertical direction in one frame of a moving image is an odd number of dots, the gate circuit is closed by the determination output of the amount-of-motion determination circuit, and the frame synchronization signal to the switching circuit is cut off.
Therefore, the halftone processing pattern added to the signal of the upper (n-1) bits of the input video signal continues one pattern without switching from one of the patterns 1 and 2 to the other for each frame. The halftone processing patterns before and after moving by one frame do not match and are opposed to each other, so that the grid pattern is not conspicuous.

The invention according to claim 3 is the invention according to claim 1 or 2.
The motion amount determination circuit in the invention of 1) is configured by an odd number / even number determination circuit that determines whether the horizontal or vertical motion amount in one frame of a moving image is an odd dot, an even dot, or a zero dot.

According to a fourth aspect of the present invention, there is provided a pattern 1 in which a lighting dot and a non-lighting dot are alternately arranged in a unit block in which the display screen of the display panel is divided into M × N (M × N ≧ 2) dots. A signal and a signal of pattern 2 in which the lighted dots and non-lighted dots of pattern 1 are arranged in reverse are generated, and the signals of patterns 1 and 2 are switched and output every time the frame synchronization signal is input to the switching circuit. When the least significant bit of the n-bit input video signal is "1", this output signal is added to the upper (n-1) -bit signal of the input video signal and output to the display panel to generate a pseudo halftone. In the halftone display circuit of the display device for displaying, the difference between the horizontal and vertical movement amounts in one frame of the moving image on the display screen of the display panel is odd. And a gate circuit in which a frame synchronization signal is inserted into a line input to the switching circuit and whose opening and closing is controlled by the determination output of the motion amount difference determination circuit. It is characterized by being done.

When the difference between the horizontal and vertical motion amounts in one frame of a moving image that moves diagonally is an odd dot, the gate circuit is closed by the determination output (for example, "0") of the motion amount difference determination circuit. Therefore, the frame synchronization signal which is the switching control signal to the switching circuit is cut off. Therefore, even when the least significant bit of the n-bit input video signal is "1", the halftone processing pattern added to the signal of the upper (n-1) bits of this input video signal is a pattern for each frame. Since one pattern is continued without switching from one of 1 and 2 to the other, the halftone processing patterns before and after the movement of one frame do not match and are opposed to each other, and the grid pattern is not conspicuous.

According to a fifth aspect of the present invention, in the motion amount difference determination circuit according to the fourth aspect, the difference between the horizontal and vertical motion amounts in one frame of the moving image is an odd dot, an even number, or Odd number to determine if it is a zero dot
It is composed of an even number determination circuit.

[0022]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS One embodiment of the present invention will be described with reference to FIG. In FIG. 1, the same parts as those in FIG. In FIG. 1, 10 is a video signal input terminal, 1
Reference numeral 2 is an adder circuit for inputting the upper (n-1) bits of the n (for example, n = 8) bit video signal input to the input terminal 10 as one input signal, and 14 is coupled to the output side of the adder circuit 12. A PDP as a display panel, 16 is a pattern 1 generation circuit for generating and outputting a signal of pattern 1 as shown in FIG. 1B (same as FIG. 4B), 18
Is a pattern 2 generation circuit for generating and outputting a signal of pattern 2 as shown in FIG. 1C (same as FIG. 4C).

Reference numeral 20 is a switching circuit. This switching circuit 20 is
Each time the frame synchronization signal input to the control signal input terminal 22 is input, the pattern 1 signal and the pattern 2 signal are switched and output. An AND circuit 24 opens and closes when the least significant bit of the n-bit input video signal is "1" or "0", and the AND circuit 24 outputs the signal output from the switching circuit 20 to the adder circuit 12
To the switching circuit 20 when the least significant bit of the input video signal is "1" by outputting to or shutting off.
The signals of patterns 1 and 2 output from the above are added to the signal of the upper (n-1) bits of the input video signal and output to the PDP 14 for pseudo-halftone display.

Reference numeral 30 is an AND circuit as an example of a gate circuit. The AND circuit 30 is inserted in a line through which the frame synchronization signal input to the input terminal 22 is input to the switching circuit 20. Reference numeral 32 is an input terminal for inputting a signal (hereinafter, simply referred to as a motion amount signal) corresponding to a motion amount of a moving image on the display screen of the PDP 14. 34
Is an odd / even determination circuit as an example of a motion amount determination circuit.
Based on the motion amount signal input to, the horizontal or vertical motion amount in one frame of the moving image is an odd dot, an even dot, or a zero dot (for example, in the case of a slow moving moving image or a still image). It is configured to determine whether or not and output a determination signal (for example, "0" for odd dots, "1" for even dots or zero dots) to the AND circuit 30.

The operation of the embodiment shown in FIG. 1 will be described with reference to FIG. A: The case of a still image SG will be described. Based on the motion amount signal input to the input terminal 32, the odd number / even number determination circuit 34 determines that the amount of movement in the horizontal direction or the vertical direction in one frame of the moving image is zero dot, and the determination signal “1”.
Is output to the AND circuit 30, and the AND circuit 30 is opened to input the frame synchronization signal input to the input terminal 22 to the switching circuit 20.

Therefore, the switching circuit 20 switches the signal of pattern 1 output from the pattern 1 generation circuit 16 and the signal of pattern 2 output from the pattern 2 generation circuit 18 for each frame and outputs them to the AND circuit 24. . When the least significant bit of the n-bit video signal input to the input terminal 10 is "1", the AND circuit 24 is opened and the signals of patterns 1 and 2 are input to the addition circuit 12, and the input n is input.
The high-order (n-1) -bit signal of the bit video signal is added and output to the PDP 14.

Therefore, assuming that the halftone processing pattern of the frame 1 is the pattern 1 as shown in FIG. 2A, the still image SG displayed on the PDP 14 is the halftone of the frame 2 one frame later. The processing pattern is the pattern 2, and the patterns 1 and 2 are not replaced for each frame, so that the grid-like pattern is not conspicuous. In FIG. 2, ◯ represents the illuminated dot D1, and ● represents the non-illuminated dot D0.

B: The case where the amount of movement in the horizontal direction or the vertical direction in one frame of the moving image DG is an even dot will be described. Based on the motion amount signal input to the input terminal 32, the odd number / even number determination circuit 34 determines that the horizontal or vertical motion amount in one frame of the moving image is an even dot, and outputs a determination signal “1”. The AND circuit 30 outputs the signal to the circuit 30, and the AND circuit 30 is opened to input the frame synchronization signal input to the input terminal 22 to the switching circuit 20.

Therefore, as in the case of the still image SG of A, the switching circuit 20 switches the signal of pattern 1 and the signal of pattern 2 for each frame and outputs them to the AND circuit 24, and the n-bit video signal. When the least significant bit is "1", the AND circuit 24 is opened and the signals of patterns 1 and 2 are input to the addition circuit 12 and added to the upper (n-1) -bit signal of the input n-bit video signal. Then PDP
It outputs to 14.

Therefore, when the amount of horizontal movement in one frame of the moving picture DG displayed on the PDP 14 is 2 dots, the halftone processing pattern of the frame 1 is the pattern 1, as shown in FIG. 2B. Then, the halftone processing pattern of the frame 2 after the one frame becomes the pattern 2, and in the moving image DG, the patterns 1 and 2 are exchanged for each frame, and the grid pattern is not conspicuous.
The same applies to the case of even dots other than 2 dots. Further, the same operation is performed when the amount of vertical movement in one frame of the moving image DG is even dots.

C: A case where the amount of movement in the horizontal direction or the vertical direction in one frame in the moving image DG is an odd number of dots will be described. Based on the motion amount signal input to the input terminal 32, the odd number / even number determination circuit 34 determines that the amount of movement in the horizontal direction or the vertical direction in one frame of the moving image is an odd number even dot, and outputs a determination signal “0”. The frame synchronizing signal output to the AND circuit 30 and closed by closing the AND circuit 30 is blocked from being input to the switching circuit 20.

Therefore, the switching circuit 20 outputs either one of the pattern 1 signal output from the pattern 1 generation circuit 16 and the pattern 2 signal output from the pattern 2 generation circuit 18 (for example, the pattern 1 signal). ) Is continuously output to the AND circuit 24. N input to the input terminal 10
When the least significant bit of the bit video signal is "1",
The AND circuit 24 is opened to input one of the signals of patterns 1 and 2 (for example, the signal of pattern 1) to the adder circuit 12 and add it to the upper (n-1) -bit signal of the input n-bit video signal. Output to PDP14.

Therefore, when the amount of horizontal movement in one frame of the moving picture DG displayed on the PDP 14 is 1 dot, the halftone processing pattern of the frame 1 is the pattern 1 as shown in FIG. 2 (c). Then, the halftone processing pattern of the frame 2 after the one frame is also the pattern 1, and in the moving image DG, the patterns 1 and 2 are replaced for each frame, and the grid pattern is not conspicuous.
The same applies to odd-numbered dots other than one dot. The same operation is performed when the amount of vertical movement in one frame of the moving image DG is an odd number of dots.

In the above embodiment, the motion amount judging circuit is constituted by the odd number / even number judging circuit. However, the present invention is not limited to this, and the horizontal direction in one frame of the moving image on the display screen of the display panel. Alternatively, it may be a circuit that determines whether or not the amount of movement in the vertical direction is an odd dot.

In the above embodiment, the motion amount determination circuit determines whether or not the amount of movement in the horizontal direction or the vertical direction in one frame of the moving image on the display screen of the display panel is an odd dot, and the gate is output by this determination output. Although the opening and closing of the circuit is controlled so as to pass or block the input of the frame synchronization signal to the switching circuit, the present invention is not limited to this.

For example, instead of the odd / even determination circuit (an example of the motion amount determination circuit) 34 in FIG. 1, the difference between the horizontal and vertical motion amounts in one frame of a moving image on the display screen of the PDP 14 is an odd dot. Or even / zero dot odd / even determination circuit 34
a (an example of a motion amount difference determination circuit for determining whether or not it is an odd dot) is provided, and opening / closing of the AND circuit 30 is controlled by the determination output of the odd / even determination circuit 34a, and the frame synchronization signal is sent to the switching circuit 20. It is also possible to use the one that allows the input to be passed or blocked.

Next, the above-mentioned odd number / even number decision circuit 34a
1 will be described with reference to FIGS. 3A and 3B when the odd number / even number determination circuit 34 of FIG. 1 is provided. D: A case will be described in which the moving image DG moves diagonally and the difference between the horizontal and vertical movement amounts in one frame is an even dot. Odd / even determination circuit 34a
On the basis of the motion amount signal input to the input terminal 32, determines that the difference between the horizontal and vertical motion amounts in one frame of the moving image is an even dot, and outputs a determination signal “1” to the AND circuit 30. Then, the AND circuit 30 is opened and the frame synchronization signal input to the input terminal 22 is input to the switching circuit 20.

Therefore, as in the case of the B moving picture DG, the switching circuit 20 causes the pattern 1 signal and the pattern 2
Signal is switched to each frame and output to the AND circuit 24. When the least significant bit of the n-bit video signal is "1", the AND circuit 24 is opened and the signals of patterns 1 and 2 are input to the adding circuit 12. , PDP1 is added to the upper (n-1) -bit signal of the input n-bit video signal.
4 is output.

Therefore, when the amount of movement in the horizontal direction is 1 dot, the amount of movement in the vertical direction is 3 dots, and the difference between them is 2 dots in one frame of the moving picture DG displayed on the PDP 14, the difference is 2 (moving diagonally to the lower right). Case) is shown in FIG.
As shown in, if the halftone processing pattern of the frame 1 is the pattern 1, the frame 2 after the one frame is processed.
The halftone processing pattern of is the pattern 2, and in the moving image DG, the patterns 1 and 2 are replaced for each frame, and the grid-like pattern is not conspicuous. The same applies when the difference in the amount of motion is even dots other than 2 dots, and also when the amount of motion is zero dot (for example, when the amount of motion in one frame is small or in the case of a still image).

E: A description will be given of a case where the moving image DG moves in an oblique direction and the difference between the horizontal and vertical movement amounts in one frame is an odd number of dots. Based on the motion amount signal input to the input terminal 32, the odd / even determination circuit 34a determines that the difference between the horizontal and vertical motion amounts in one frame of the moving image is an odd dot, and the determination signal "0". To the AND circuit 30, and the AND circuit 30
Is closed to block the input of the frame synchronization signal input to the input terminal 22 to the switching circuit 20.

Therefore, the switching circuit 20 outputs either one of the pattern 1 signal output from the pattern 1 generation circuit 16 and the pattern 2 signal output from the pattern 2 generation circuit 18 (for example, the pattern 1 signal). ) Is continuously output to the AND circuit 24. N input to the input terminal 10
When the least significant bit of the bit video signal is "1",
The AND circuit 24 is opened to input one of the signals of patterns 1 and 2 (for example, the signal of pattern 1) to the adder circuit 12 and add it to the upper (n-1) -bit signal of the input n-bit video signal. Output to PDP14.

Therefore, when the amount of movement in the horizontal direction is 1 dot, the amount of movement in the vertical direction is 2 dots, and the difference between them is 1 dot in one frame of the moving image DG displayed on the PDP 14, the difference is 1 dot, as shown in FIG. 3B. As described above, assuming that the halftone processing pattern of the frame 1 is the pattern 1, the halftone processing pattern of the frame 2 one frame after that is also the pattern 1.
Therefore, in the moving image DG, the patterns 1 and 2 are not replaced for each frame, and the lattice-like pattern is not conspicuous.
The same applies when the difference in the amount of movement is an odd dot other than one dot.

In the above embodiment, the case where both M and N of M × N forming the unit block UB are 2 has been described, but the present invention is not limited to this, and these M and N are M × N. It may be an integer satisfying ≧ 2.

In the above embodiment, the case where the display panel is a PDP has been described, but the present invention is not limited to this, and the present invention can be applied to the case of a digital display panel (for example, a liquid crystal display panel).

[0045]

According to the present invention, the signals of patterns 1 and 2 are switched and output every time the frame synchronizing signal is input to the switching circuit, and the output signal is the least significant bit "1" of the n-bit input video signal. In the halftone display circuit of the display device for adding pseudo high halftone (n-1) -bit signals of the input video signal and outputting to the display panel, the horizontal direction in one frame of the moving image or A motion amount determination circuit that determines whether or not the amount of vertical movement is an odd dot, and a gate that is inserted into the line that inputs the frame synchronization signal to the switching circuit and whose opening and closing is controlled by the determination output of the motion amount determination circuit. And a circuit.

Therefore, when the amount of movement in the horizontal direction or the vertical direction in one frame of the moving image is an odd number of dots, the gate circuit is closed by the determination output (for example, "0") of the movement amount determination circuit, and the switching circuit is switched to. The frame synchronization signal, which is the switching control signal of, is cut off. Therefore, even when the least significant bit of the n-bit input video signal is "1", the halftone processing pattern added to the signal of the upper (n-1) bits of this input video signal is the pattern 1 for each frame. Since one pattern is continued without switching from one of 2 to the other, patterns 1 and 2 are switched for each frame in the moving image, and the halftone processing patterns do not match and are relative to each other, resulting in a grid pattern. Does not stand out.

Further, a motion amount difference determination circuit for determining whether or not the difference between the horizontal and vertical motion amounts in one frame of a moving image that moves diagonally is an odd dot, and a frame synchronization signal switching circuit. And a gate circuit whose opening / closing is controlled by the determination output of the motion amount difference determination circuit, the following effects can be achieved.

That is, when the difference in the amount of movement in the horizontal direction and the amount in the vertical direction in one frame of the moving image that moves diagonally is an odd dot, the gate circuit is closed by the determination output (for example, "0") of the movement amount difference determination circuit. Therefore, the frame synchronization signal which is the switching control signal to the switching circuit is cut off. Therefore, even when the least significant bit of the n-bit input video signal is "1", the high-order (n
-1) The halftone processing pattern added to the 1-bit signal continues one pattern without switching from one of the patterns 1 and 2 to the other for each frame. 2, the halftone processing patterns do not match and are opposed to each other, and the grid pattern is not conspicuous.

[Brief description of drawings]

FIG. 1 shows an embodiment of a halftone display circuit of a display device according to the present invention, in which (a) is a block diagram,
(B) is an explanatory view of pattern 1, and (c) is an explanatory view of pattern 2.

FIG. 2 is a diagram for explaining the operation in the case where the odd / even determination circuit 34 of FIG. 1 is a motion amount determination circuit that determines whether or not the horizontal or vertical motion amount in one frame of a moving image is an odd dot. , (A) is an explanatory diagram of a halftone processing pattern of a still image, (b) is an explanatory diagram of a halftone processing pattern of a moving image having a horizontal movement amount of 2 dots (an example of even dots), and (c) is a horizontal direction. It is explanatory drawing of the halftone process pattern of the moving image with the amount of movement of 1 direction (an example of an odd number dot).

FIG. 3 is a diagram illustrating an example of a motion amount determination circuit that determines whether the difference between the horizontal and vertical motion amounts in one frame of a moving image that moves diagonally in the odd / even determination circuit 34a in FIG. 1 is an odd dot. Explaining the action in the case, (a)
Is an explanatory diagram of a halftone processing pattern of a moving image in which the difference in the amount of movement between the horizontal direction and the vertical direction is 2 dots (an example of even dots)
FIG. 6B is an explanatory diagram of a halftone processing pattern of a moving image in which the difference in the amount of movement between the horizontal direction and the vertical direction is 1 dot (an example of an odd number dot).

FIG. 4 shows a conventional example, (a) is a block diagram,
(B) is an explanatory view of pattern 1, and (c) is an explanatory view of pattern 2.

5A and 5B are diagrams for explaining the operation of FIG. 4, in which FIG. 5A is an explanatory diagram of a halftone processing pattern of a still image, and FIG. 5B is of a moving image having a horizontal movement amount of 2 dots (an example of even dots). FIG. 3C is an explanatory diagram of a halftone processing pattern, and FIG. 7C is an explanatory diagram of a halftone processing pattern of a moving image having a horizontal movement amount of 1 dot (an example of an odd number dot).

[Explanation of symbols]

10 ... n-bit video signal input terminal, 12 ... addition circuit, 14 ... PDP (plasma display panel),
16 ... Pattern 1 generation circuit, 18 ... Pattern 2 generation circuit, 20 ... Switching circuit, 22 ... Frame sync signal input terminal, 24 ... AND circuit, 30 ... AND circuit (an example of gate circuit), 32 ... Motion amount signal Input terminals, 34 ... Odd / even determination circuit (an example of a motion amount determination circuit that determines whether or not the horizontal or vertical motion amount in one frame of a moving image is an odd dot), 34a ...
Odd / even determination circuit (an example of a motion amount determination circuit that determines whether or not the difference between the horizontal and vertical motion amounts in one frame of a moving image in an oblique direction is an odd dot),
D0 ... non-illuminated dot, D1 ... illuminated dot, DG ... moving image, M ... number of dots on one side of unit block UB,
N ... the number of dots on the other side of the unit block UB, SG ...
Still image, UB ... Unit block.

 ──────────────────────────────────────────────────続 き Continuing from the front page (72) Inventor Junichi Onodera 1116 Suenaga, Takatsu-ku, Kawasaki-shi, Kanagawa Prefecture Inside Fujitsu General Co., Ltd. 72) Inventor Seiji Matsunaga 1116 Suenaga, Takatsu-ku, Kawasaki City, Kanagawa Prefecture Inside Fujitsu General Co., Ltd.

Claims (5)

[Claims] 1. A display screen of a display panel is M × N.
(M × N ≧ 2) Pattern 1 in which lit dots and non-lit dots are alternately arranged in a unit block divided in dot units
And a signal of pattern 2 in which the lit dots and non-lit dots of pattern 1 are arranged in reverse, and the signals of patterns 1 and 2 are switched and output every time the frame synchronization signal is input to the switching circuit. Then, when the least significant bit of the n-bit input video signal is "1", this output signal is added to the upper (n-1) -bit signal of the input video signal and output to the display panel to generate a pseudo intermediate A halftone display circuit of a display device that performs a grayscale display; a motion amount determination circuit that determines whether or not a horizontal motion amount in one frame of a moving image on the display screen of the display panel is an odd dot; A gate circuit in which a signal is inserted into a line input to the switching circuit and whose opening and closing is controlled by a judgment output of the motion amount judging circuit. Halftone display circuit of the display device according to claim. 2. The display screen of the display panel is M × N.
(M × N ≧ 2) Pattern 1 in which lit dots and non-lit dots are alternately arranged in a unit block divided in dot units
And a signal of pattern 2 in which the lit dots and non-lit dots of pattern 1 are arranged in reverse, and the signals of patterns 1 and 2 are switched and output every time the frame synchronization signal is input to the switching circuit. Then, when the least significant bit of the n-bit input video signal is "1", this output signal is added to the upper (n-1) -bit signal of the input video signal and output to the display panel to generate a pseudo intermediate In a halftone display circuit of a display device that performs a grayscale display, a motion amount determination circuit that determines whether or not a vertical motion amount in one frame of a moving image on the display screen of the display panel is an odd dot, and the frame synchronization. A gate circuit in which a signal is inserted into a line input to the switching circuit and whose opening and closing is controlled by a judgment output of the motion amount judging circuit. Halftone display circuit of the display device according to claim. 3. A motion amount determination circuit as an odd / even determination circuit for determining whether the motion amount in one frame of a moving image is an odd dot, an even dot or a zero dot. Halftone display circuit of display device. 4. The display screen of the display panel is M × N.
(M × N ≧ 2) Pattern 1 in which lit dots and non-lit dots are alternately arranged in a unit block divided in dot units
And a signal of pattern 2 in which the lit dots and non-lit dots of pattern 1 are arranged in reverse, and the signals of patterns 1 and 2 are switched and output every time the frame synchronization signal is input to the switching circuit. Then, when the least significant bit of the n-bit input video signal is "1", this output signal is added to the upper (n-1) -bit signal of the input video signal and output to the display panel to generate a pseudo intermediate In a halftone display circuit of a display device that performs a grayscale display, a motion amount difference for determining whether a difference between a horizontal direction and a vertical direction in one frame of a moving image on the display screen of the display panel is an odd dot. A determination circuit and a gate circuit in which the frame synchronization signal is inserted into a line input to the switching circuit, and opening / closing is controlled by a determination output of the motion amount difference determination circuit. Halftone display circuit of the display device characterized by comprising comprises a. 5. A motion amount difference determination circuit that determines whether the difference between the horizontal and vertical motion amounts in one frame of a moving image is an odd dot, an even number, or a zero dot. The halftone display circuit of the display device according to claim 4.