EP1124216A2

EP1124216A2 - Method for driving display panel

Info

Publication number: EP1124216A2
Application number: EP00127839A
Authority: EP
Inventors: Masahiro c/o Pioneer Corporation Suzuki; Nobuhiko c/o Pioneer Corporation Saegusa
Original assignee: Pioneer Corp
Current assignee: Panasonic Corp
Priority date: 2000-02-10
Filing date: 2000-12-19
Publication date: 2001-08-16
Also published as: EP1124216A3; JP3734244B2; JP2001222250A

Abstract

A method of driving a display panel that is capable of displaying pictures while suppressing the occurrence of pseudo contour without causing flicker even when the vertical synchronization frequency of the input video signal is low. When each of a plurality of light emitting elements that constitute a display screen of the display panel are caused to emit light only for a light emitting period corresponding to the luminance level of the input video signal within the unit display period, with the unit display period comprised of a first drive period of the first half and a second drive period of the second half, each of the light emitting elements is driven to emit light continuously for a first part of the light emitting period in the first drive period, and driven to emit light continuously for the remaining part of the light emitting period in the second drive period.

Description

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to a method for driving a display panel comprising light emitting elements, that have only two states, i.e. light emitting and non-light emitting states, being arranged therein.

2. Description of Related Art

Recently, as the increase in screen size of display apparatuses, demands for display devices of a smaller depth are growing. Plasma display panels of alternating current discharge type are regarded as a promising technology for thin display devices.
In such a plasma display panel, since each discharge cell that is an element of the display screen has only two states: the states of light emitting and non-light emitting, the sub-field method is employed for rendering intermediate tones of luminance that correspond to an input video signal.
The sub-field method divides the period of displaying one field into a plurality of sub-fields, and achieves a desired level of luminance by setting the discharge cells in each sub-field to light emitting state or an non-light emitting state. With the sub-field method, in the case where a light emitting state in successive sub-fields and a non light emitting state in successive sub-fields interchange with each other between light emission patterns of similar luminance levels, a so-called problem of pseudo contour occurs. Thus measures are taken to prevent the sustained light emitting state and the sustained non-light emitting state from interchanging with each other between light emission patterns of similar luminance levels.
However, in the case where the input video signal has a low vertical synchronization frequency as in the case of a PAL system television signal, for example, the frequency may happen to be identical with the frequency of switching between the sustained light emitting state and the sustained non-light emitting state. When such a television signal is supplied as the video signal, there has been a problem that flicker is generated.

OBJECTS AND SUMMARY OF THE INVENTION

The present invention has been made to solve such problems as described above, and an object of the invention is to provide a method of driving a display panel that is capable of displaying pictures while suppressing the occurrence of pseudo contours without causing flicker even when the vertical synchronization frequency of the input video signal is low.
According to the display panel driving method of the present invention, the display panel is driven to provide a toned display by causing each light emitting element to emit light only for a period corresponding to the luminance level of the input video signal, within the unit display period, in the display panel having a display screen constituted by a plurality of light emitting elements. The unit display period is made by a first drive period of a first half and a second drive period of a second half. In the first drive period, the light emitting element is driven to emit light continuously for the first part of the light emitting period and, in the second drive period, the light emitting element is driven to emit light continuously for the remaining part of the light emitting period.

BRIEF DESCRIPTION OF THE DRAWINGS

Fig. 1 is a diagram schematically showing the structure of a plasma display apparatus.
Fig. 2 shows an example of light emission drive format based on the sub-field method.
Fig. 3 shows an example of light emission drive pattern.
Fig. 4 shows the structure of a plasma display apparatus which drives a plasma display panel according to the driving method of the present invention.
Fig. 5 shows the inner structure of a data conversion circuit 30.
Fig. 6 shows the data conversion characteristic of a first data conversion circuit 32.
Fig. 7 shows an example of data conversion table based on the data conversion characteristic shown in Fig. 6.
Fig. 8 shows an example of data conversion table based on the data conversion characteristic shown in Fig. 6.
Fig. 9 shows the inner structure of a tone multiplication processing circuit 33.
Fig. 10 is a drawing for explaining the operation of an error diffusion processing circuit 330.
Fig. 11 shows the inner structure of a dither processing circuit 350.
Fig. 12 shows the operation of a dither processing circuit 350.
Fig. 13 shows a first data conversion table used in a second data conversion circuit 34 when the input video signal has a vertical synchronization frequency that is not lower than a predetermined frequency, and a light emission drive pattern thereof.
Fig. 14 shows a second data conversion table used in the second data conversion circuit 34 when the input video signal has a vertical synchronization frequency that is lower than the predetermined frequency, and a light emission drive pattern thereof.
Fig. 15 shows an example of light emission drive format (based on the selective erasure address method) employed when the input video signal has a vertical synchronization frequency that is not lower than the predetermined frequency.
Fig. 16 shows an example of light emission drive format (based on the selective erasure address method) employed when the input video signal has a vertical synchronization frequency that is lower than the predetermined frequency.
Fig. 17 shows the timing of applying various drive pulses to PDP 10.
Fig. 18 shows another example of second data conversion table used in the second data conversion circuit 34 when the input video signal has a vertical synchronization frequency that is lower than the predetermined frequency, and the light emission drive pattern thereof.
Fig. 19 shows another example of light emission drive format (based on the selective erasure address method) employed when the input video signal has a vertical synchronization frequency that is lower than the predetermined frequency.
Fig. 20 shows another example of second data conversion table used in the second data conversion circuit 34 when the input video signal has a vertical synchronization frequency that is lower than the predetermined frequency, and the light emission drive pattern thereof.
Fig. 21 shows an example of light emission drive format (based on the selective writing address method) employed when the input video signal has a vertical synchronization frequency that is not lower than the predetermined frequency.
Fig. 22 shows an example of light emission drive format (based on the selective writing address method) employed when the input video signal has a vertical synchronization frequency that is lower than the predetermined frequency.
Fig. 23 shows the first data conversion table used in the second data conversion circuit 34 when driving according to the light emission drive format shown in Fig. 21, and the light emission drive pattern thereof.
Fig. 24 shows the second data conversion table used in the second data conversion circuit 34 when driving according to the light emission drive format shown in Fig. 22, and the light emission drive pattern thereof.
Fig. 25 shows a variation of the light emission drive format shown in Fig. 16.
Fig. 26 shows the second data conversion table used in the second data conversion circuit 34 when driving according to the light emission drive format shown in Fig. 25, and the light emission drive pattern thereof.
Fig. 27 shows a variation of the light emission drive format shown in Fig. 22.
Fig. 28 shows the second data conversion table used in the second data conversion circuit 34 when driving according to the light emission drive format shown in Fig. 27, and the light emission drive pattern thereof.
Fig. 29 shows an example of light emission drive pattern employed when dividing one field into 13 sub-fields and driving a toned display based on the selective erasure address method.
Fig. 30 shows an example of light emission drive pattern employed when dividing one field into 13 sub-fields and driving a toned display based on the selective writing address technique.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

Prior to a description of a preferred embodiment of the present invention, a prior art method of driving a display panel will be described below with reference to the accompanying drawings.
Fig. 1 shows the schematic structure of a plasma display apparatus which displays pictures with such a plasma display panel.
In Fig. 1, PDP 10 which is the plasma display panel has m column electrodes D₁ through D_m that serve as data electrodes and n row electrodes X₁ through X_n and row electrodes Y₁ through Y_n that cross the column electrodes. A pair of X and Y electrodes constitute the row electrode corresponding to one line of the screen. The column electrode D and the row electrodes X, Y are formed on two glass substrates that are disposed to oppose each other interposing a discharge space which is filled with a discharge gas formed in between. Formed at the intersect of a row electrode and a column electrode is a discharge cell that serves as a display element for one pixel.
The discharge cell operates by making use of electric discharge, and therefore has only two states of light emitting and non-light emitting. That is, the discharge cell can provide luminance of only two tones, minimum luminance (non-light emitting) and maximum luminance (light emitting). Therefore a drive device 100 drives the PDP 10, comprising the discharge cells arranged in a matrix, by the sub-field method to drive toned display in order to render luminance of an intermediate tone that corresponds to input video signal.
The sub-field method divides the display period of one field into, for example, eight sub-fields SF1 through SF8 as shown in Fig. 2. The number of times light should be turned on in the sub-field is assigned to each of the sub-fields SF1 through SF8. As a consequence, light emission is carried out a number of times that corresponding to the luminance level of the input video signal in the display period of one field, by choosing a proper combination of sub-fields where light is to be emitted and sub-fields where light is not to be emitted according to the input video signal. This causes an intermediate level of luminance to be perceived according to the total number of times light is emitted in the display period of one field.
Fig. 3 shows an example of the combination of sub-fields where light is to be emitted and sub-fields where light is not to be emitted (hereinafter referred to as a light emission drive pattern).
The drive device 100 selects one of nine different light emission drive patterns shown in Fig. 3, in accordance with the input video signal. Accordingly, various drive pulses are applied to the column electrodes D, and row electrodes X, Y of the PDP 10, to thereby emit light the number of times shown in Fig. 2 only in the sub-fields indicated by white circles in the light emission drive pattern that has been selected.
According to the nine light emission drive patterns shown in Fig. 3, pictures can be displayed with nine levels of intermediate luminance having the following proportions of luminance of light emitted.
{0, 1, 7, 23, 47, 82, 128, 185, 255}
At this time, in the light emission drive pattern shown in Fig. 3, once a discharge cell is turned to an non-light emitting state in one sub-field during the period of one field, subsequent sub-fields are controlled so that light is not emitted. That is, such a light emission drive pattern is rejected in which the state of sub-fields in which light is emitted occur successively (hereinafter referred to as the sustained light emitting state) as indicated by the white circles and the state of sub-fields in which light is not emitted occur successively (hereinafter referred to as the sustained non-light emitting state) interchange with each other between light emission patterns of similar luminance levels in the period of one field. This scheme suppresses the occurrence of pseudo contour that would take place in the boundary of two picture regions where the sustained light emitting state and the sustained non-light emitting state interchange with each other.
In the light emission drive pattern as shown in Fig. 3, the frequency of switching between the sustained light emitting state and the sustained non-light emitting state becomes equal to the vertical synchronization frequency that determines the period of displaying one field. As a result, there is a possibility of flicker occurring when the PAL system television signal wherein the vertical synchronization frequency is limited to 50Hz is supplied as the input video signal, as described previously.
Now a preferred embodiment of the present invention will be described below with reference to the accompanying drawings.
Fig. 4 schematically shows the structure of a plasma display apparatus which drives a plasma display panel according to the driving method of the present invention.
In Fig. 4, when the vertical synchronization frequency is detected from the input video signal, a sync detection circuit 1 generates and supplies a vertical synchronization detection signal V to a drive control circuit 2 and a vertical synchronization frequency detection circuit 3. When the horizontal synchronization signal is detected from the input video signal, the sync detection circuit 1 generates and supplies a horizontal synchronization detection signal H to the drive control circuit 2. The vertical synchronization frequency detection circuit 3 determines the vertical synchronization frequency of the input video signal by measuring the frequency of the vertical synchronization detection signal V, and supplies a vertical synchronization frequency signal VF that represents the frequency to the drive control circuit 2 and a data conversion circuit 30. An A/D converter 4 samples the input video signal thereby converting it into, for example, 8-bit pixel data D for each pixel in accordance with a clock signal supplied from the drive control circuit 2, and supplies the pixel data to the data conversion circuit 30.
Fig. 5 shows the inner structure of a data conversion circuit 30.
In Fig. 5, a first data conversion circuit 32 supplies a tone multiplication processing circuit 33 with converted pixel data D₁₁ that is generated by multiplying the pixel data D by (14 × 16)/255 according to the conversion characteristic shown in Fig. 6. In other words, the first data conversion circuit 32 converts the pixel data D that is capable of representing the levels of luminance for 256 tones, from 0 to 255, with eight bits, into the converted pixel data D_H that is capable of representing the levels of luminance for 255 tones, from 0 to 224, with eight bits. Specifically, the first data conversion circuit 32 converts the pixel data D into the converted pixel data D_H according to the conversion table shown in Fig. 7 and Fig. 8 based on the conversion characteristic shown in Fig. 6. The conversion characteristic is determined in accordance with the number of bits of the pixel data, the number of bits compressed in a tone multiplication process to be described later, and the number of displayed tones.
Thus the data are converted in the first data conversion circuit 32 in consideration of the number of displayed tones and the number of bits compressed in the tone multiplication, before carrying out the tone multiplication process that will be described later. With this data conversion, the input pixel data D is divided into a group of most significant bits (corresponding to multi-toned pixel data) and a group of least significant bits (data to be discarded: error data), and the tone multiplication process is carried out according to this signal. This makes it possible to prevent saturation of luminance from occurring due to the tone multiplication process and flattening of the display characteristic (that is, distortion of tone) that occurs when the display tone is not on the bit boundary.
Fig. 9 shows the inner structure of the tone multiplication processing circuit 33 that carries out the tone multiplication process.
As shown in Fig. 9, the tone multiplication processing circuit 33 is composed of an error diffusion processing circuit 330 and a dither processing circuit 350.
A data separation circuit 331 of the error diffusion processing circuit 330 separates the 8-bit converted pixel data D_H supplied from the first data conversion circuit 32 into error data consisting of the least significant two bits and display data consisting of the most significant six bits. An adder 332 adds the error data, delayed output of a delay circuit 334 and multiplied output of a coefficient multiplier 335, and supplies the sum to a delay circuit 336. The delay circuit 336 sends the sum supplied from the adder 332, with a delay time corresponding to the period of one clock cycle of the pixel data (hereinafter called the delay time D) being applied thereto, as delayed addition signal AD₁ to the coefficient multiplier 335 and the delay circuit 337. The coefficient multiplier 335 multiplies the delayed addition signal AD₁ by a predetermined coefficient K₁ (7/16, for example) and sends the product to the adder 332. The delay circuit 337 sends the delayed addition signal AD₁, with an additional delay time of (one horizontal scan period - delay time D × 4) applied thereto, as delayed addition signal AD₂ to a delay circuit 338. The delay circuit 338 sends the delayed addition signal AD₂, with further additional delay time of the delay time D applied thereto, as delayed addition signal AD₃ to a coefficient multiplier 339. The delay circuit 338 also sends the delayed addition signal AD₂, with a delay time of the delay time D × 2 applied thereto, as delayed addition signal AD₄ to a coefficient multiplier 340. The delay circuit 338 further sends the delayed addition signal AD₂, with a delay time equal to the delay time D × 3 applied thereto, as a delayed addition signal AD₅ to a coefficient multiplier 341. The coefficient multiplier 339 multiplies the delayed addition signal AD₃ by a predetermined coefficient K₂ (3/16, for example) and sends the product to the adder 342. The coefficient multiplier 340 multiplies the delayed addition signal AD₄ by a predetermined coefficient K₃ (5/16, for example) and sends the product to the adder 342. The coefficient multiplier 341 multiplies the delayed addition signal AD₅ by a predetermined coefficient K₄ (1/16, for example) and sends the product to the adder 342. The adder 342 adds up the products supplied from the coefficient multipliers 339, 340 and 341 and sends the sum to the delay circuit 334. The delay circuit 334 outputs the addition signal, with the delay time D applied thereto, to the adder 332. The adder 332 adds the error data, the delayed output from the delay circuit 334 and the multiplication output from the coefficient multiplier 335, and sends it to an adder 333 a carry-out signal C_o having a logical value of 0 when there is no carry over in the addition, or a logical value of 1 when there is carry over in the addition. The adder 333 adds the carry-out signal C_o to the display data comprising the most significant six bits of the converted pixel data D_H and outputs the sum as the 6-bit error diffusion processed pixel data ED.
Operation of the error diffusion processing circuit 330 having such a structure as described above will now be described below.
To determine the error diffusion processed pixel data ED for a pixel G(j, k) of the PDP 10 as shown in Fig. 10, for example, error data for each of a pixel G(j, k-1) located at the left of the pixel G(j, k), a pixel G(j-1, k-1) located at the upper left of the pixel G(j, k), a pixel G(j-1, k) located above the pixel G(j, k) and a pixel G(j-1, k+1) located at the upper right of the pixel G(j, k), are weighted by predetermined weighting factors K₁ through K₄ as follows.
Error data for the pixel G(j, k-1): Delayed addition signal AD₁
Error data for the pixel G(j-1, k+1): Delayed addition signal AD₃
Error data for the pixel G(j-1, k): Delayed addition signal AD₄
Error data for the pixel G(j-1, k-1): Delayed addition signal AD₅
Then the least significant two bits of the converted pixel data HD_P, namely the error data of the pixel G(j, k), is added to the sum obtained as described above. The carry-out signal C_o consisting of one bit thus obtained is added to the most significant six bits of the converted pixel data D_H, namely the display data of the pixel G(j, k), with the result of addition being taken as the error diffusion processed pixel data ED.
In the error diffusion processing circuit 330 having such a structure as described above, the most significant six bits and the least significant two bits of the converted pixel data D_H are used as the display data and the error data, respectively, and the error data weighted by the corresponding weighting factors for the peripheral pixels [G(j, k-1), G(j-1, k+1), G(j-1, k), G(j-1, k-1)] are added, with the result being reflected on the display data. This operation causes the luminance corresponding to the least significant two bits at the pixel G(j, k) to be represented alternatively by the peripheral pixels, thereby making it possible to provide a toned representation of luminance equivalent to 8-bit pixel data, by using 6-bit display data which is lower than 8-bit display data.
Simply adding the coefficient of error diffusion for each pixel may cause visual perception of noise caused by the error diffusion pattern, resulting in deteriorated picture quality. To counter this problem, the error diffusion coefficients K₁ through K₄ to be assigned to the four surrounding pixels may be changed from field to field.
The dither processing circuit 350 applies dither process to the error diffusion processed pixel data ED supplied from the error diffusion processing circuit 330. In the dither process, one intermediate display level is represented by a plurality of adjacent pixels. For example, to provide a toned display equivalent to that of eight bits by using the pixel data of the most significant six bits among the 8-bit pixel data, four vertically and horizontally adjacent pixels are grouped as a set, and four dither coefficients a through d of different values are added to the pixel data of corresponding pixels of the set. The dither process produces four different combinations of intermediate display levels from the four pixels. As a result, even when the pixel data comprises six bits, a number of tone levels four times larger, namely intermediate tones equivalent to those of eight bits, can be represented.
However, when the dither coefficients a through d of constant values are added to each pixel, visual perception of noise caused by the dither pattern may occur, resulting in deteriorated picture quality.
To counter this problem, in the dither processing circuit 350, the dither coefficients a though d to be assigned to the four pixels are changed from field to field.
Fig. 11 shows the inner structure of the dither processing circuit 350.
In Fig. 11, a dither coefficient generation circuit 352 generates four dither coefficients a, b, c and d for the four adjacent pixels [G(j, k), G(j, k+1), G(j+1, k), G(j+1, k+1)] as shown in Fig. 12 and sends the coefficients successively to the adder 351. The dither coefficient generation circuit 352 also changes the assignment of the dither coefficients a through d, that are generated in correspondence to the four pixels, from field to field as shown in Fig. 12.
Specifically, the dither coefficients a through d are generated cyclically and repetitively for the following assignments and are supplied to the adder 351.
In the first field:
Pixel G(j, k): Dither coefficient a
Pixel G(j, k+1): Dither coefficient b
Pixel G(j+1, k): Dither coefficient c
Pixel G(j+1, k+1): Dither coefficient d
In the second field:
Pixel G(j, k): Dither coefficient b
Pixel G(j, k+1): Dither coefficient a
Pixel G(j+1, k): Dither coefficient d
Pixel G(j+1, k+1): Dither coefficient c
In the third field:
Pixel G(j, k): Dither coefficient d
Pixel G(j, k+1): Dither coefficient c
Pixel G(j+1, k): Dither coefficient b
Pixel G(j+1, k+1): Dither coefficient a
In the fourth field:
Pixel G(j, k): Dither coefficient c
Pixel G(j, k+1): Dither coefficient d
Pixel G(j+1, k): Dither coefficient a
Pixel G(j+1, k+1): Dither coefficient b
The dither coefficient generation circuit 352 repetitively carries out the above operation for the first field through the fourth field. That is, when the operation of generating the dither coefficients for the fourth field is completed, the operation is repeated from the first field.
The adder 351 adds the dither coefficients a through d, that are assigned for each field as described above, to the error diffusion processed pixel data ED of the pixel G(j, k), pixel G(j, k+1), pixel G(j+1, k) and pixel G(j+1, k+1), respectively, that are supplied from the error diffusion processing circuit 330, and supplies the dither-added pixel data thus obtained to an upper bit extraction circuit 353.
In the first field shown in Fig. 12, for example, the following values are supplied successively to the upper bit extraction circuit 353 as the dither-added pixel data.
Error diffusion processed pixel data ED corresponding to pixel G(j, k) + dither coefficient a,
Error diffusion processed pixel data ED corresponding to pixel G(j, k+1) + dither coefficient b,
Error diffusion processed pixel data ED corresponding to pixel G(j+1, k) + dither coefficient c, and
Error diffusion processed pixel data ED corresponding to pixel G(j+1, k+1) + dither coefficient d.
The upper bit extraction circuit 353 extracts the four most significant bits of the dither-added pixel data, and supplies the extracted data as the multi-toned pixel data D_s to the second data conversion circuit 34 shown in Fig. 5.
The second data conversion circuit 34 converts the multi-toned pixel data D_s into 14-bit pixel drive data GD in accordance with a conversion table that corresponds to the vertical synchronization frequency of the input video signal indicated by the vertical synchronization frequency signal VF. For example, when NTSC system television signal having a vertical synchronization frequency of 60Hz or higher is supplied as the input video signal, the second data conversion circuit 34 converts the multi-toned pixel data D_s into pixel drive data GD in accordance with the first conversion table shown in Fig. 13. When PAL system television signal having vertical synchronization frequency lower than 60Hz is supplied as the input video signal, on the other hand, the multi-toned pixel data Ds is converted into pixel drive data GD in accordance with the second conversion table shown in Fig. 14.
A memory 5 shown in Fig. 4 stores the pixel drive data GD successively written therein according to the writing signal supplied from the drive control circuit 2. When the writing operation for the data of one picture frame (n rows, m columns) has been completed, the pixel drive data GD_11-nm of one screen frame are read successively from the memory 5 at the same bit digit for one line, and are sent to an address driver 6. In other words, the pixel drive data bits GD1_11-nm through GD14_11-nm in the memory 5 are determined for each bit digit of the pixel drive data GD_11-nm of one screen frame as follows.
DB1_11-nm: First bit of the pixel drive data GD_11-nm
DB2_11-nm: Second bit of the pixel drive data GD_11-nm
DB3_11-nm: Third bit of the pixel drive data GD_11-nm
DB4_11-nm: Fourth bit of the pixel drive data GD_11-nm
DB5_11-nm: Fifth bit of the pixel drive data GD_11-nm
DB6_11-nm: Sixth bit of the pixel drive data GD_11-nm
DB7_11-nm: Seventh bit of the pixel drive data GD_11-nm
DB8_11-nm: Eighth bit of the pixel drive data GD_11-nm
DB9_11-nm: Ninth bit of the pixel drive data GD_11-nm
DB10_11-nm: Tenth bit of the pixel drive data GD_11-nm
DB11_11-nm: Eleventh bit of the pixel drive data GD_11-nm
DB12_11-nm: Twelfth bit of the pixel drive data GD_11-nm
DB13_11-nm: Thirteenth bit of the pixel drive data GD_11-nm
DB14_11-nm: Fourteenth bit of the pixel drive data GD_11-nm
Then DB1_11-nm through DB14_11-nm are read off successively line by line according to a read signal supplied from the drive control circuit 2 and supplied to the address driver 6.
The drive control circuit 2 employs a light emission drive format that corresponds to the vertical synchronization frequency of the input video signal indicated by the vertical synchronization frequency signal VF. According to the light emission drive format that is employed, the drive control circuit 2 generates various timing signals for the control of the address driver 6, a first sustain driver 7 and a second sustain driver 8.
For example, when NTSC system television signal having a vertical synchronization frequency of 60Hz or higher is supplied as the input video signal, the drive control circuit 2 employs the light emission drive format shown in Fig. 15. When a signal having vertical synchronization frequency lower than 60Hz, such as a PAL system television signal, is supplied as the input video signal, on the other hand, the drive control circuit 2 employs the light emission drive format shown in Fig. 16.
In the light emission drive format shown in Fig. 15 and Fig. 16, the display period for one field (this includes also one frame hereinafter) is divided into 14 sub-fields SF1 through SF 14. And in each sub-field, pixel data writing process Wc where the pixel data is written for each discharge cell of the PDP 10 thereby to set the light emitting cells and non-light emitting cells, and light emission sustaining process Ic where only the cells to be light emitting are turned on to emit light repetitively for the period shown in the drawing, are carried out.- Also a total reset process Rc, where the amounts of charges on the walls of all discharge cells of the PDP 10 are initialized, is carried out in the first sub-field SF1, and erasure process E where charges on the walls of all discharge cells are eliminated is carried out in the last sub-field SF14.
In the light emission drive format shown in Fig. 16, the sub-fields SF1, SF3, SF5, SF7, SF9, SF11 and SF13 in the light emission drive format of Fig. 15 are executed in the first half of one field, while SF2, SF4, SF6, SF8, SF10, SF12 and SF14 are executed in the second half of the field. At this time, the erasure process E is carried out in the last sub-field SF13 of the first half, and the total reset process Rc is carried out in the first sub-field SF2 of the second half.
The address driver 6, the first sustain driver 7 and the second sustain driver 8 apply various drive pulses for achieving the processes described above to the electrodes of the PDP 10 at the timing determined by a timing signal supplied from the drive control circuit 2.
Fig. 17 shows the timing of various drive pulses applied by the drivers to the column electrodes D and the row electrodes X, Y in the total reset process Rc, the pixel data writing process Wc, the light emission sustaining process Ic and the erasure process E.
First, in the total reset process Rc, the first sustain driver 7 and the second sustain driver 8 apply such reset pulses RP_X and RP_Y as shown in Fig. 17 to the row electrodes X₁ through X_n and Y₁ through Y_n. As the reset pulses RP_X and RP_Y are applied, all discharge cells of the PDP 10 discharge to be reset, so that a predetermined amount of charges deposit uniformly on the wall of every discharge cell. Thus all the discharge cells are reset to the light emitting cells.
In the pixel data writing process Wc, the address driver 6 generates pixel data pulse group DP (for one line), that has a voltage corresponding to the logical value of the pixel drive data bit DB which has been supplied from the memory 5, and applies the pulses to the column electrode D_1-m. In the pixel data writing process Wc of the sub-field SF1, for example, the pixel drive data bit DB1_11-1m that corresponds to the first row is read from the memory 5. Accordingly the address driver 6 generates the pixel data pulse group DP consisting of the pixel data pulses of m pieces corresponding to the logical values of the DB1_11-1m and applies the pixel data pulse group DP to the column electrodes D_1-m. Then as the pixel drive data bit DB1_21-2m that corresponds to the second line is read from the memory 5, the address driver 6 generates the pixel data pulse group DP of m pieces corresponding to the logical values of the DB1_21-2m and applies the pixel data pulse group DP to the column electrodes D_1-m. Similarly in the pixel data writing process Wc for the sub-field SF1, pixel data pulse group DP corresponding to the first through nth lines are applied successively to the column electrodes D_1-m thereafter. The address driver 6 generates high voltage pixel data pulses when the logical value of the pixel drive data bit DB is "1", and generates low voltage pixel data pulses (0 volts) when the logical value is "0".
Also in the pixel data writing process Wc, the second sustaining driver 8 generates negative polarity scan pulse SP as shown in Fig. 17 at the same timing as the timing of applying the pixel data pulse group DP described above. The scan pulses are applied to the row electrodes Y₁ through Y_n successively. At this time, electrical discharge (selective erasure discharge) occurs only in the discharge cell located at the intersection of the row to which the scan pulse SP is applied and the column to which the pixel data pulse of high voltage is applied, thereby selectively eliminating the charge remaining on the wall of the discharge cell. The discharge cell that was initialized to the state of an light emitting cell in the total reset process Rc is changed to the state of an non-light emitting cell by this selective erasure discharge. On the other hand, electrical discharge does not occur in the discharge cells located on the column to which the pixel data pulse of low voltage is applied, and the discharge cell remains in the present state. Thus the non-light emitting cells remain in the state of non-light emitting cell, and the light emitting cells remain in the state of light emitting cell.
In the light emission sustaining process Ic of each sub-field, the first sustain driver 7 and the second sustain driver 8 repetitively apply sustaining pulses IP_X and IP_Y of positive polarity to the row electrodes X₁ through X_n and Y₁ through Y_n alternately, as shown in Fig. 17. Proportions of the length of periods during which the sustaining pulse IP is kept being applied in the light emission sustaining process Ic for the sub-fields SF1 through SF14 are set as follows.
SF1: 1
SF2: 3
SF3: 5
SF4: 8
SF5: 10
SF6: 13
SF7: 16
SF8: 19
SF9: 22
SF10: 25
SF11: 28
SF12: 32
SF13: 35
SF14: 39
Sustained discharge is carried out in the discharge cell where charges are formed on the wall thereof, namely the light emitting cells, every time the sustaining pulses IP_X and IP_Y are applied only. That is, only the discharge cells that were set as light emitting cells in the pixel data writing process Wc repeat to emit light through the sustained discharge during the period determined by the weighting factor of the sub-field described above, thus sustaining the light emitting state. The longer the time in which the light emitting state is sustained, the brighter the display is perceived by the human eyes.
In the erasure process E, the second sustain driver 8 generates such an erasure pulse EP of negative polarity as shown in Fig. 17 and applies the pulse to the row electrodes Y₁ through Y_n. Application of the erasure pulse EP causes erasure discharge to occur in all discharge cells of the PDP 10, so that the charges remaining on the walls of all discharge cells disappear. That is, the erasure discharge forces all the discharge cells of the PDP 10 to turn into non-light emitting cells.
With the driving operation described above, only the discharge cells that were set as light emitting cells by the pixel data writing process Wc in each sub-field repeat to emit light in the light emission sustaining process Ic immediately after the process Wc during the period determined by the weighting factor of the sub-field as described above. Whether a discharge cell is set as an light emitting cell or non-light emitting cell is determined by the pixel drive data GD shown in Fig. 13 or Fig. 14.
The foregoing description can be summed as follows. When a bit of the pixel drive data GD consisting of first through fourteenth bits has logical value "1", selective erasure discharge occurs in the pixel data writing process Wc of the sub-field corresponding to the bit digit. This selective erasure discharge sets the discharge cell to the non-light emitting cell state. When a bit of the pixel drive data GD has logical value "0", on the other hand, selective erasure discharge does not occur in the pixel data writing process Wc of the sub-field corresponding to the bit digit. Thus discharge cells in the non-light emitting cell state remain in the non-light emitting cell state, and the discharge cells in the light emitting cells state remain in the light emitting cell state. A discharge cell can be changed from the non-light emitting cell state to the light emitting cell state only by the total reset process Rc.
The first through fourteenth bits of the pixel drive data GD shown in Fig. 13 correspond to the sub-fields SF1 through SF14 shown in Fig. 15, respectively.
Consequently, when driving according to the light emission drive format shown in Fig. 15 by using the pixel drive data GD shown in Fig. 13, all discharge cells are first initialized as the light emitting cells in the sub-field SF1. The light emitting cell state is maintained until the selective erasure discharge occurs in the sub-fields indicated by black circles in Fig. 13. In the light emission sustaining process Ic for each of the sub-fields (indicated by white circles) that are present while the light emitting cell state is maintained, light is emitted for a period determined by the weighting factor of the sub-field. In this driving operation, the number of times the state is switched from the sustained light emitting state where light is emitted in consecutive sub-fields to the sustained non-light emitting state where light is not emitted in consecutive sub-fields is one in the display period of one field. Here, sum of the periods of time during which light was emitted in the light emission sustaining process Ic of the sub-fields SF1 through SF14 relates to the luminance.
The first through fourteenth bits of the pixel drive data GD shown in Fig. 14 correspond to the sub-fields SF1 through SF14 shown in Fig. 16 as follows, respectively.
1^st bit of GD: SF1
2nd bit of GD: SF3
3rd bit of GD: SF5
4^th bit of GD: SF7
5^th bit of GD: SF9
6^th bit of GD: SF11
7^th bit of GD: SF13
8^th bit of GD: SF2
9^th bit of GD: SF4
10^th bit of GD: SF6
11^th bit of GD: SF8
12^th bit of GD: SF10
13^th bit of GD: SF12
14^th bit of GD: SF14
In the light emission drive format shown in Fig. 16, total reset process Rc is executed not only,in the sub-field SF1 but also in the sub-field SF2.
Consequently, when driving according to the light emission drive format shown in Fig. 16 by using the pixel drive data GD shown in Fig. 14, the discharge cells are first initialized as the light emitting cells in the sub-field SF1. The light emitting cell state is maintained until the selective erasure discharge occurs in the sub-fields indicated by the black circles in Fig. 14. Then in the light emission sustaining process Ic of each of the sub-fields (indicated by white circles) that are present while the light emitting cell state is maintained, light is emitted for a period determined by the weighting factor of the sub-field. After the selective erasure discharge has occurred, the discharge cells turn to non-light emitting cells. Then the discharge cells are initialized to light emitting cells again in the sub-field SF2, and maintain the light emitting cell state until the selective erasure discharge occurs in the sub-fields indicated by the black circles. Then in the light emission sustaining process Ic for the sub-fields (indicated by the white circles) subsequent to the sub-field SF2 that are present while the light emitting cell state is maintained, light is emitted for a period determined by the weighting factor of the sub-field. In this driving operation, the number of times the state is switched, from the sustained light emitting state where light is emitted in consecutive sub-fields to the sustained non-light emitting state where light is not emitted in consecutive sub-fields, is two at maximum in the display period of one field. Here, sum of the periods of time during which light was emitted in the light emission sustaining process Ic of the sub-fields SF1 through SF14 relates to the luminance of light emission in one field.
As a result, when driving the toned display according to the light emission drive format shown in Fig. 15 or Fig. 16 by using the pixel drive data GD shown in Fig. 13 or Fig. 14 as described above, pictures can be displayed with intermediate tones of luminance of 15 levels as follows.
{0: 1: 4: 9: 17: 27: 40: 56: 75: 97: 122: 150: 182: 217: 256}
Combination of such a driving operation with 15 tone levels and the multi-tone processing in the tone multiplication processing circuit 33 described previously makes it possible to achieve a visual effect equivalent to 256 tone levels of luminance.
In the operation of toned display described above, the selective erasure discharge to change the state of the discharge cells is carried out only once in the period from the time of executing the total reset process Rc to the execution of the next total reset process Rc as indicated by the black circles in Fig. 13 and Fig. 14. With this operation, the sub-fields in which light is emitted continue (sustained light emitting state), while sub-fields in which light is not emitted continue (sustained non-light emitting state). There is no light emission drive pattern in which the sustained light emitting state and the sustained non-light emitting state are switched alternately. As a result, since no case occurs where two picture regions wherein the sustained light emitting state and the sustained non-light emitting state are switched alternately in the period of one field appear in one picture frame, occurrence of the pseudo contour that would take place in the boundary of two picture regions can be suppressed.
Also the present invention employs a toned display operation as the display period of one field is divided into the first drive period (SF1, SF3, SF5, SF7, SF9, SF11, SF13) of the first half and the second drive period (SF2, SF4, SF6, SF8, SF10, SF12, SF14) of the second half as shown in Fig. 14 and Fig. 16. Meanwhile, in the first drive period, light is emitted continuously for a period of time corresponding to the luminance level (first tone to fifteenth tone) of the input video signal, beginning at the start of the first drive period. In the second drive period, on the other hand, light is emitted continuously for a period of time corresponding to the luminance level (first tone to fifteenth tone) of the input video signal, beginning at the start of the second drive period. With this driving operation, therefore, the number of times the state is switched from the sustained light emitting state where light is emitted in consecutive sub-fields to the sustained non-light emitting state where light is not emitted in consecutive sub-fields is two at maximum in the display period of one field. Also the time interval between the start of light emission in the first drive period to the start of light emission in the second drive period is about one half the display period of one field. Therefore, since the frequency of switching between the sustained light emitting state and the sustained non-light emitting state is about twice the vertical synchronization frequency that determines the display period of one field, flicker does not occur even when the PAL system television signal of which vertical synchronization frequency is limited to 50Hz is supplied as the input video signal.
In the light emission drive pattern shown in Fig. 14, the selective erasure discharge is carried out only once in the period from the execution of the total reset process Rc to the next execution of the total reset process Rc. However, when the amount of charges remaining in the discharge cells is small, the selective erasure discharge may not occur normally even when the scan pulse SP and the high-voltage pixel data pulse are, for example, applied simultaneously.
For this reason, the second conversion table shown in Fig. 18 may be employed instead of that shown in Fig. 14 for use in the second data conversion table 34, to thereby reliably cause the selective erasure discharge. When the pixel drive data GD that are converted in accordance with the second conversion table are used, the selective erasure discharge occurs in two consecutive sub-fields as indicated by the black circles in Fig. 18. With this operation, even when the charges on the walls in the discharge cells cannot be eliminated normally by the first selective erasure discharge, the charges on the walls can be eliminated normally by the second selective erasure discharge.
In the light emission drive format shown in Fig. 16, the sub-fields SF1, SF3, SF5, SF7, SF9, SF11 and SF13 are executed in the first half of one field while SF2, SF4, SF6, SF8, SF10, SF12 and SF14 are executed in the second half thereof, although the present invention is not limited to this scheme.
Fig. 19 shows a variation of the light emission drive format shown in Fig. 16 devised in consideration of the facts described above.
In the light emission drive format shown in Fig. 19, sub-fields SF1, SF4, SF5, SF8, SF9, SF12 and SF13 are executed successively in the first half of one field while SF2, SF3, SF6, SF7, SF10, SF11 and SF14 are executed successively in the second half thereof.
Fig. 20 shows the second data conversion table used in the second data conversion circuit 34 when the light emission drive format shown in Fig. 19 is employed, and the light emission drive pattern thereof.
The embodiment described above is a case of employing the so-called selective erasure address method wherein all discharge cells are set to the light emitting cell state by forming charges on the walls of all discharge cells, and then the charges are eliminated selectively according to the pixel data for the purpose of writing the pixel data.
However, the present invention may also be applied to a case of employing the so-called selective writing address method wherein the charges are formed on the wall selectively according to the pixel data for the purpose of writing the pixel data.
Fig. 21 and Fig. 22 show the light emission drive format used when employing the selective writing address method. Fig. 23 shows the first data conversion table used in the second data conversion circuit 34 when the light emission drive format shown in Fig. 21 is employed, and the light emission drive pattern thereof. Fig. 24 shows the second data conversion table used in the second data conversion circuit 34 when the light emission drive format shown in Fig. 22 is employed, and the light emission drive pattern thereof.
According to the light emission drive format shown in Fig. 21, toned display is driven in the order of sub-fields from SF14 to SF1, contrary to the case of the light emission drive format shown in Fig. 15. In this case, the total reset process Rc', where charges remaining on walls of all the discharge cells are eliminated at the same time thereby initializing all discharge cells to the non-light emitting cell state, is carried out only in the first sub-field SF14. Then the pixel data writing process Wc and the light emission sustaining process Ic are carried out in each sub-field. At this time, selective writing discharge for forming charges on the wall occurs only in the pixel data writing process Wc' of the sub-fields (indicated by black circles) that correspond to digits having logical value of "1" in the pixel drive data GD shown in Fig. 23. The discharge cells where the selective writing discharge has occurred are set to light emitting cells. As a consequence, in the light emission sustaining process Ic of the sub-fields indicated by the black circles or white circles in Fig. 23, light is emitted for a period of time corresponding to the weighting factor of the sub-field.
In the light emission drive format shown in Fig. 22, sub-fields SF13, SF11, SF9, SF7, SF5, SF3 and SF1 are executed successively in the first half of one field while SF14, SF12, SF10, SF8, SF6, SF4 and SF2 are executed successively in the second half thereof. In this case, the total reset process Rc' described above is carried out similarly in the first sub-field SF13 of the first half and in the first sub-field SF14 of the second half. Then the pixel data writing process Wc' described above and the light emission sustaining process Ic are carried out in each sub-field. That is, only in the light emission sustaining process Ic of the sub-fields marked with the black circle and the white circle in Fig. 24, light is emitted for a period of time corresponding to the weighting factor of the sub-field. In this driving operation, switching from the sustained non-light emitting state to the sustained light emitting state is carried out twice in the display period of one field, similarly to the light emission drive pattern shown in Fig. 14.
In the case where there is no possibility of flicker occurring because of the vertical synchronization frequency of the input video signal being equal to or higher than the predetermined frequency (60Hz), the drive control circuit 2 controls the operation according to the light emission drive format shown in Fig. 21 by using the pixel drive data GD shown in Fig. 23. When there is a possibility of flicker occurring because of the vertical synchronization frequency of the input video signal being lower than the predetermined frequency (60Hz), the drive control circuit 2 controls the operation according to the light emission drive format shown in Fig. 22 by using the pixel drive data GD shown in Fig. 24. That is, when the vertical synchronization frequency of the input video signal is lower than the predetermined frequency (60Hz), switching from the sustained non-light emitting state to the sustained light emitting state is carried out up to twice in the display period of one field as shown in Fig. 24.
In the light emission drive format shown in Fig. 16, the sub-fields having odd numbers are executed in the first half of one field and the sub-fields having even numbers are executed in the second half, although this order may be reverted.
Fig. 25 shows a variation of the light emission drive format (selective erasure address) shown in Fig. 16 devised in consideration of the facts described above.
In the light emission drive format shown in Fig. 25, the sub-fields SF2, SF4, SF6, SF8, SF10, SF12 and SF14 wherein light is to be emitted a number of times in proportions of [3: 8: 13: 19: 25: 32: 39] in the respective light emission sustaining process Ic are executed successively in the first half of one field. In the second half of the one field, the sub-fields SF1, SF3, SF5, SF7, SF9, SF11 and SF13 wherein light is to be emitted a number of times in proportions of [1: 5: 10: 16: 22: 28: 35] in the respective light emission sustaining process Ic are executed successively.
Fig. 26 shows the second data conversion table used in the second data conversion circuit 34 when the light emission drive format shown in Fig. 25 is employed, and the light emission drive pattern thereof.
Fig. 27 shows a variation of the light emission drive format (selective writing address) shown in Fig. 22.
In the light emission drive format shown in Fig. 27, the sub-fields SF14, SF12, SF10, SF8, SF6, SF4 and SF2 wherein light is to be emitted a number of times in proportions of [39: 32: 25: 16: 13: 5: 3] in the respective light emission sustaining process Ic are executed successively in the first half of one field. In the second half of the one field, the sub-fields SF13, SF11, SF9, SF7, SF5, SF3 and SF1 wherein light is to be emitted a number of times in proportions of [35: 28: 22: 19: 10: 8: 1] in the respective light emission sustaining process Ic are executed successively.
Fig. 28 shows the second data conversion table used in the second data conversion circuit 34 when the light emission drive format shown in Fig. 25 is employed, and the light emission drive pattern thereof.
While one field is divided into 14 sub-fields and the PDP 10 is driven to provide a toned display in the embodiment described above, the number of sub-fields is not limited to 14.
Fig. 29 and Fig. 30 show examples of light emission drive pattern employed in case one field is divided into 13 sub-fields and the PDP 10 is driven to provide toned display.
Fig. 29 shows the light emission drive pattern when the selective erasure address method is employed for writing the pixel data. In the light emission drive pattern shown in Fig. 29, the sub-fields SF1, SF3, SF5, SF7, SF9, SF11 and SF13 wherein light is to be emitted a number of times in proportions of [1: 5: 10: 16: 22: 28: 35] in the respective light emission sustaining process Ic are executed successively in the first half of one field. In the second half of the one field, the sub-fields SF2, SF4, SF6, SF8, SF10 and SF12 wherein light is to be emitted a number of times in proportions of [3: 8: 13: 19: 25: 32] in the respective light emission sustaining process Ic are executed successively.
Fig. 30 shows the light emission drive pattern when the selective writing address method is employed for writing the pixel data. In the light emission drive pattern shown in Fig. 30, the sub-fields SF13, SF11, SF9, SF7, SF5, SF3 and SF1 wherein light is to be emitted a number of times in proportions of [35: 28: 22: 16: 10: 5: 1] in the respective light emission sustaining process Ic are executed successively in the first half of one field. In the second half of the one field, the sub-fields SF12, SF10, SF8, SF6, SF4 and SF2 wherein light is to be emitted a number of times in proportions of [32: 25: 19: 13: 8: 3] in the respective light emission sustaining process Ic are executed successively.
According to the present invention, as described in detail above, the frequency of switching from the sustained non-light emitting state to the sustained light emitting state (or from the sustained light emitting state to the sustained non-light emitting state) in the display period of one field can be set higher than the vertical synchronization frequency. As a consequence, pictures in which pseudo contour is suppressed can be displayed without causing flicker even when the PAL system television signal wherein the vertical synchronization frequency is limited to 50Hz is supplied.

Claims

A display panel drive method for driving toned display of a display panel having a display screen formed from a plurality of light emitting elements by causing each of said light emitting elements to emit light for a light emission period that corresponds to the luminance level of the input video signal in the unit display period;
wherein said unit display period comprises a first drive period of a first half and a second drive period of a second half, and wherein each of said light emitting elements is caused to emit light continuously during a first part of said light emission period in said first drive period, and caused to emit light continuously during a remaining part of said light emission period in said second drive period.
A display panel drive method as described in claim 1 wherein time interval between the start of emitting light in said first drive period and the start of emitting light in said second drive period is about one half of said unit display period.
A display panel drive method as described in claim 1 wherein said unit display period is divided into a plurality of divided display periods with all of said light emitting elements being initialized to either the light emitting cell state or an non-light emitting cell state, only during one of said divided display period that comes first in the first drive period;

a state of each of said light emitting elements is changed, in one of said divided display periods in said first drive period, from the non-light emitting cell state to an light emitting cell state or from the light emitting cell state to an non-light emitting cell state in accordance with said input video signal;

only those among said light emitting elements that are in the light emitting cell state are caused to emit light for a period of time determined by a weighting factor of said divided display period, in each of said divided display periods in said first drive period;

all of said light emitting elements are initialized to either the light emitting cell state or an non-light emitting cell state, only during the first divided display period in the second drive period;

a state of each of said light emitting elements is changed, in one of said divided display periods in said second drive period, from the non-light emitting cell state to an light emitting cell state or from the light emitting cell state to an non-light emitting cell state in accordance with said input video signal; and

only those among said light emitting elements that are in the light emitting cell state are caused to emit light for a period of time determined by the weighting factor of said divided display period, in each of said divided display periods in said second drive period.
A display panel drive method for driving toned display of a display panel, having a display screen formed from a plurality of light emitting elements, by causing each of said light emitting elements to emit light for a light emission period that corresponds to the luminance level of the input video signal in the unit display period; comprising

a first drive sequence for causing each of said light emitting elements to emit light continuously during said light emission period within said unit display period; and

a second drive sequence, in which said unit display period comprises a first drive period of a first half and a second drive period of a second half, for causing each of said light emitting elements to emit light continuously during a first part of said light emission period in said first drive period, and to emit light continuously during a remaining part of said light emission period in said second drive period;

wherein either said first drive sequence or said second drive sequence is selectively executed according to the vertical synchronization frequency of said input video signal.
A display panel drive method as described in claim 4 wherein the time interval between the start of emitting light in said first drive period and the start of emitting light in said second drive period is about one half of said unit display period.
A display panel drive method as described in claim 4 wherein said first drive sequence is executed when the vertical synchronization frequency of said input video signal is equal to or higher than a predetermined frequency, while said second drive sequence is executed when the vertical synchronization frequency of said input video signal is lower than said predetermined frequency.
A display panel drive method as described in claim 4 wherein said unit display period is divided into a plurality of divided display periods, with all of said light emitting elements being initialized to either a light emitting cell state or a non-light emitting cell state, only during the first divided display period in said first drive period;

a state of each of said light emitting elements is changed, in one of said divided display periods in said first drive period, from the non-light emitting cell state to the light emitting cell state or from the light emitting cell state to the non-light emitting cell state in accordance with said input video signal;

only those among said light emitting elements that are in the light emitting cell state are caused to emit light for a period of time determined by the weighting factor of said divided display period, in each of said divided display periods in said first drive period;

all of said light emitting elements are initialized to either the light emitting cell state or the non-light emitting cell state, only during the first divided display period in said second drive period;

the state of said light emitting elements is changed, in one of said divided display periods in said second drive period, from the non-light emitting cell state to the light emitting cell state or from the light emitting cell state to the non-light emitting cell state in accordance with said input video signal; and

only those among said light emitting elements that are in the light emitting cell state are caused to emit light for a period of time determined by the weighting factor of said divided display period, in each of said divided display periods in said second drive period.
A method for driving a display panel having a display screen formed from a plurality of light emitting elements; wherein

a display period of one field of input video signal comprises N sub-fields that are allocated to a first drive period of a first half of said display period of one field and a second drive period of a second half thereof, so as to provide display with N+1 intermediate levels of luminance from the first through (N+1)st tones;

in the case where said number N is an even number,

said light emitting elements are not caused to emit light in any of said sub-fields for said first tone; said light emitting elements are caused to emit light only in the first sub-field during either one of said first drive period and said second drive period for the second tone; said light emitting elements are caused to emit light only in the first sub-field during the other one of said first drive period and said second drive period, in addition to the sub-fields in which light is emitted for the second tone, for the third tone; said light emitting elements are caused to emit light only in the sub-field that is disposed at the second position during either one of said first drive period and said second drive period, in addition to the sub-fields in which light is emitted for the third tone, for the fourth tone; said light emitting elements are caused to emit light in the last sub-field during either one of said first drive period and the second drive period, in addition to the sub-fields in which light is emitted for the (N-1)st tone, for the Nth tone; and said light emitting elements are caused to emit light in the last sub-field during the other one of the first drive period and the second drive period, in addition to the sub-fields in which light is emitted for the Nth tone, for the (N+1)st tone; while

in the case where said number N is an odd number,

said light emitting elements are not caused to emit light in any of said sub-fields for said first tone; said light emitting elements are caused to emit light only in the first sub-field during either one of the first drive period and the second drive period for the second tone; said light emitting elements are caused to emit light only in the first sub-field during the other one of the first drive period and the second drive period, in addition to the sub-fields in which light is emitted for the second tone, for the third tone; said light emitting elements are caused to emit light in the sub-field that is disposed at the second position during either one of the first drive period and the second drive period, in addition to the sub-fields in which light is emitted for the third tone, for the fourth tone; said light emitting elements are caused to emit light in the last sub-field during the other one of the first drive period and the second drive period, in addition to the sub-fields in which light is emitted for the (N-1)st tone, for the Nth tone; and said light emitting elements are caused to emit light in the last sub-field during either one of the first drive period and the second drive period, in addition to the sub-fields in which light is emitted for the Nth tone, for the (N+1)st tone.
A method for driving a display panel having a display screen formed from a plurality of light emitting elements; wherein

with the display period of one field of input video signal being divided into N sub-fields that are allocated to a first drive period of the first half of said display period of one field and a second drive period of the second half, so as to provide display with N+1 intermediate levels of luminance from the first through (N+1)st tones;

in the case where said number N is an even number,

said light emitting elements are not caused to emit light in any of said sub-fields for said first tone; said light emitting elements are caused to emit light only in the last sub-field during either one of the first drive period and the second drive period for the second tone; said light emitting elements are caused to emit light only in the last sub-field during the other one of the first drive period and the second drive period, in addition to the sub-fields in which light is emitted for the second tone, for the third tone; said light emitting elements are caused to emit light only in the sub-field that is disposed immediately before the last sub-field during either one of the first drive period and the second drive period, in addition to the sub-fields in which light is emitted for the third tone, for the fourth tone; said light emitting elements are caused to emit light in the first sub-field during either one of the first drive period and the second drive period, in addition to the sub-fields in which light is emitted for the (N-1)st tone, for the Nth tone; and said light emitting elements are caused to emit light in the first sub-field during the other one of the first drive period and the second drive period, in addition to the sub-fields in which light is emitted for the Nth tone, for the (N+1)st tone; while

in the case where said number N is an odd number,

said light emitting elements are not caused to emit light in any of said sub-fields for said first tone; said light emitting elements are caused to emit light only in the last sub-field during either one of the first drive period and the second drive period for the second tone; said light emitting elements are caused to emit light only in the last sub-field during the other one of the first drive period and the second drive period, in addition to the sub-fields in which light is emitted for the second tone, for the third tone; said light emitting elements are caused to emit light in the sub-field that is disposed immediately before the last sub-field during either one of the first drive period and the second drive period, in addition to the sub-fields in which light is emitted for the third tone, for the fourth tone; said light emitting elements are caused to emit light in the first sub-field during the other one of the first drive period and the second drive period, in addition to the sub-fields in which light is emitted for the (N-1)st tone, for the Nth tone; and said light emitting elements are caused to emit light in the first sub-field during either one of the first drive period and the second drive period, in addition to the sub-fields in which light is emitted for the Nth tone, for the (N+1)st tone.
A method for driving a display panel having a display screen formed from a plurality of light emitting elements; wherein

with the display period of one field of input video signal comprises N sub-fields so as to provide display with N+1 intermediate levels of luminance from the first tone through the (N+1)st tone;

said light emitting elements are caused to emit light in the other one of the sub-field in addition to the sub-fields in which light is emitted for the (n-1)st tone, for the nth tone (1≤n≤N+1), while time interval between the start of emitting light in the sub-fields in which light is emitted for the (n-1)st tone or the sub-fields in which light is emitted for the (n+1)st tone and the start of emitting light in the sub-fields where light is emitted for the mth tone (2≤m≤N) is about one half the length of the display period of one field.