JPH09218662A - Driving method of luminous image display panel - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a luminous display panel capable of suppressing generation of spurious contour. SOLUTION: Each field is configured by dividing N-th subfield having a biggest weight in the bit digit of a picture element data into N-th divided subfields of 2n pieces, dividing (N-1)-th subfield into (N-1)th divided subfields of 2n piece, dividing (N-2)-th subfield into (N-2)-th divided subfields of n pieces, dividing (N-3)-th subfield into (N-3)-th divided subfields of n pieces, and arranging in an adjacent relation a pair of the divided subfields of the above Nth divided subfields and (N-1)-th divided subfields arrayed in an adjacent relation to each other and one of the pair of (n-2)th divided subfields and (N-3)th divided subfields arrayed in an adjacent relation to each other to constitute each field.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for driving a self-luminous image display panel such as a plasma display panel and an EL panel.

[0002]

2. Description of the Related Art As a spontaneous image display panel, for example, a plasma display utilizes a discharge phenomenon.
It is not possible to control the amount of light emission continuously. Therefore, light emission is performed in pulses, and the brightness is expressed by the number of pulses, that is, the frequency of light emission. Visually, the higher the number of times of light emission per unit time, that is, the higher the light emission frequency, the brighter the image appears, and thus the gradation can be expressed.

In a plasma display, a method called a subfield method is used to express a natural image. This is that the grayscale is expressed by displaying the digitized video signal data dot-sequentially on a pixel-by-pixel basis, and by repeatedly displaying the weight of each bit of each pixel in a frame-sequential manner on a bit-plane basis. . The video signal data is digitized by 8 bits for each pixel to generate pixel data bits D8, D7, ... D1 weighted corresponding to the luminance component. At this time, D8, D7,
... D1.

Here, as shown in FIG. 1A, one field is divided into eight subfields SF8 to SF1 and pixel data bits D8 and D8 are provided in each subfield.
7, ... D1 is assigned, and light emission according to the assigned pixel data bit is executed for each subfield.
In this case, to complete one image, the screen for D8, D
Screen for 7 ... Finally, a screen for D1 and a total of 8 frame sequential scans are required.

For example, if the value of the pixel data bit D8 corresponding to the subfield SF8 is logic "1", that is, the light emission logical value, the pixel emits light 128 times in the subfield SF8. Further, when the value of the pixel data bit D8 is "0", that is, the extinction logic value, light emission by the subfield SF8 is not executed. Similarly, if the value of the pixel data bit D7 corresponding to the subfield SF7 is a logic "1", that is, a light emission logical value, the pixel emits 64 times in the subfield SF7, but the pixel of "0" emits light. do not do.

As described above, the number of times of light emission is 128, 64, 32, 16, 8, 8, 4, 2, 1 in order as shown in FIG.
Becomes When the frame sequential scanning is performed 8 times in total, each pixel has 8
It is visually perceived with the brightness equivalent to the total number of pulsed lights in the sub-fields. That is, any gradation from zero to 255 can be expressed. Figure 1 (C)
8-bit unit pixel data (1, 1, 1, 1, 1, 1,
1, 1), (1, 0, 0, 0, 0, 0, 0, 0) and (0, 0, 0, 0, 0, 0, 0, 1) within each subfield period Shows the light emitting period.

By the way, the subfield method is an excellent method as a technique capable of expressing multi-gradation even in a single-gradation display capable of expressing only two gradations of 1 and 0.
There is an urgent need to solve the image quality problem of "false contours." The false contour generation phenomenon comes from the characteristics of vision,
The signal level of the flat image is 128, 64, 3 above.
This is a phenomenon in which striped false contours, such as an image in which gradation is lost, are visually recognized along the vicinity of crossing the n-th power boundary such as 2, 16. Especially noticeable when a flat object moves. However, when the image is completely stationary, that is, when the still image stored in the video memory is displayed, the false contour is not detected. It is a feature of false contours that is perceived only in the moving parts of the image and around this level. If the signal level fluctuates due to noise contained in the image signal even when stationary, a false contour is detected around the level as in the case of motion.

The reason why the false contour is generated in the gradation expression method by the subfield method will be described with reference to FIG.
In the n field of FIG. 2, the pixels in the right part from the j + 1th column have a brightness of “10000000” or more, and the pixels in the left part from the jth column are “01111”.
The brightness is 111 "or less. Then, this image is moving to the left of the screen at a speed of 3 columns (3 pixels) per field. Accordingly, the continuous portion (" 0111111 "
The boundary portion between pixels having a brightness of 1 ”or less and pixels having a brightness of“ 10000000 ”or more) is also the j-th pixel in the n + 1 field.
-3rd column, j + 6th column, n + 3 in the n + 2 field
In the field, move to the j-9th column.

Here, in the n-th field, the light emission period (D8) is provided in the second half of the vertical scanning period from the j + 1th column to the right column, while in the first half period of the vertical scanning period from the jth column to the left column. During the light emission period (D7, D6, D
5) is provided. Subsequently, in the (n + 1) th field, the light emitting period (D8) is provided in the second half of the vertical scanning period in the column from the j-2th column to the right column, while in the vertical scanning period from the j-3th column to the left column. The light emission period (D7, D6, D5) is provided in the first half period. Subsequently, in the (n + 2) th field, the light emission period (D8) is provided in the latter half of the vertical scanning period in the column from the j-5th column to the right column, while in the vertical scanning period from the j-6th column to the left column. The light emission period (D7, D6, D5) is provided in the first half period.
Then, in the (n + 3) th field, the light emission period (D8) is generated in the second half of the vertical scanning period in the right column from the j-8th column.
On the other hand, the light emitting period (D7, D6, D5) is provided in the first half of the vertical scanning period in the left column from the j-9th column.
Is provided.

Therefore, between the nth field and the n + 1th field, from the jth column to the jth-2nd column, and between the n + 1th field and the n + 2 field, the jth-3rd column to the j-5th column. Further, between the n + 2 field and the n + 3 field, a non-light emitting period occurs in which the band-like movement is performed from the j-6th column to the j-8th column. Therefore, when the line of sight is moved as indicated by arrow S in FIG. 2 on such a screen, the jth column in the n field, the j-3th column in the n + 1 field, and the j-6th column in the n + 2 field. , N + 3
The "gap" (indicated by the broken-line area P) occurring in each part of the j-9th column in the field will be sequentially followed. Therefore, the false contour as a black line is strongly visually recognized concentrated on such a portion. This is a false contour due to movement. If the direction of movement is reversed, it will be visible as a white line. Moreover, even if the order of subfields is reversed in time, it is visually recognized as a white line.

Here, a technique aiming at avoiding such a false contour generation phenomenon is already known from Japanese Patent Laid-Open No. 4-211294. This technique attempts to prevent the occurrence of false contours by changing the order of arrangement of subfields. For example, by arranging the subfields corresponding to the lower bits before and after the subfield corresponding to the most significant bit, it is possible to reduce the luminance change particularly at the level of the most significant bit and to generate the false contour. Is suppressed.

However, according to an experiment conducted by the inventor of the present application, the false contour can be visually recognized not only when the level of the most significant bit is changed but also when the luminance of a subfield corresponding to a bit lower than that is generated. found. Therefore,
It was confirmed that the above-mentioned conventional example does not sufficiently prevent the false contour.

[0013]

SUMMARY OF THE INVENTION Therefore, an object of the present invention is to provide a driving method of a light emitting display panel which can sufficiently suppress the generation of false contours.

[0014]

In order to achieve the above-mentioned object, in the method for driving a self-luminous display panel according to the present invention, each N (N is N) corresponding to the brightness of each pixel of each field of the video signal. A method for driving a self-luminous image display panel for performing light emission display for one field in a plurality of subfields that emit light for a time corresponding to weighting of each bit digit of pixel data of (natural number) bits. Out of the Nth, the weighting of the bit digit is the largest
The No. subfield is divided into 2n (n is a natural number of 2 or more) Nth subfields, and the (N-1) th subfield having the next largest weight after the Nth subfield is divided into 2n. The (N-1) th subfield is divided into n (N-1) th subfields, and the (N-2) th subfield having the next largest weight after the (N-1) th subfield is divided into n (N) th subfields. -2) divided into sub-fields,
-(2) th subfield, which has the largest weighting (N)
-3) subfield is divided into n (N-3) th subfields, and the Nth subfield and the (N-1) th subfield are arranged adjacent to each other. And a second divided subfield pair in which the (N-2) th divided subfield and the (N-3) th divided subfield are arranged adjacent to each other. And adjacent to each other to form each field.

[0015]

BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of the present invention will be described below with reference to the drawings starting from FIG. In FIG. 3, the video signal processing circuit 1 outputs an R video signal corresponding to a red image component, a G video signal corresponding to a green image component, and a B video signal corresponding to a blue image component from the supplied composite video signal, respectively. After separation and extraction, these are supplied to the A / D converter 3. The sync separation circuit 5 extracts horizontal and vertical sync signals from the composite video signal and supplies them to the timing pulse generation circuit 6. The timing pulse generation circuit 6 generates various timing pulses based on these horizontal and vertical synchronizing signals. The A / D converter 3 synchronizes with the timing pulse supplied from the timing pulse generation circuit 6, and synchronizes with the R video signal, the G video signal, and the B video signal.
Each video signal is converted into 8-bit pixel data consisting of unit pixel data corresponding to each pixel, and this is sequentially supplied to the frame memory 8.

The write / read pulse generating circuit 20 generates a write pulse and a read pulse in accordance with the timing pulse supplied from the timing pulse generating circuit 6 and supplies them to the memory control circuit 9 and at the same time. The read pulse is supplied to each of the memory control circuit 9, the output device 10, and the write / erase control circuit 21. The memory control circuit 9
A memory write signal and a memory read signal synchronized with each of the write pulse and the read pulse are generated and supplied to the frame memory 8. The frame memory 8 sequentially takes in the 8-bit pixel data supplied from the A / D converter 3 in response to the memory write signal. Further, the frame memory 8 sequentially reads the pixel data stored in the frame memory 8 in accordance with the memory read signal and supplies the pixel data to the output device 10 in the next stage.

The write / erase control circuit 21 outputs a reset pulse, a scan pulse, a sustain pulse, and an erase pulse, which will be described later, at a timing synchronized with the read pulse supplied from the write / read pulse generation circuit 20. Timing signals to be generated are generated and these are supplied to the row electrode drive pulse generation circuit 11. The row electrode drive pulse generation circuit 11 responds to each timing signal supplied from the write / erase control circuit 21 to reset pulse for resetting the residual charge amount to an initial state, scan pulse for writing pixel data, A sustain pulse for maintaining the discharge light emission state and an erase pulse for stopping the discharge light emission are generated to generate P
Row electrode Y of DP (plasma display panel) 12
1, Y2, Y3 ... Yn-1, Yn and X1, X2, X3 ... Xn-1,
Supply to Xn.

The output device 10 weights the pixel data supplied from the frame memory 8 in accordance with the magnitude of the luminance component of the pixel data bits D8, D7 ...
Each D1 is separated and extracted, and these are supplied to the pixel data pulse generation circuit 13. At this time, the pixel data bit D8 corresponds to the highest brightness component, and the lower the bit digit, the lower the high brightness component. The luminance component ratio corresponding to each of the pixel data bits D1 to D8 is

[Equation 1] {D1: D2: D3: D4: D5: D6: D7: D8} = {1: 2: 4: 8:
16: 32: 64: 128}.

The pixel data pulse generation circuit 13 generates a pixel data pulse having a voltage value corresponding to the logic "1" or "0" of the pixel data bit supplied from the output device 10 and outputs it to the column electrode. D1, D2, D3 ... Dm
-1, applied to Dm. One pixel is formed at the intersection of each of the column electrode and the row electrode. Here, when a scan pulse is applied to the row electrode from the row electrode drive pulse generation circuit 11 while the pixel data pulse is applied to the column electrode, light emission occurs, and a charge corresponding to the applied pixel data pulse is generated. Are written in the PDP 12. After that, when the sustain pulse is applied from the row electrode drive pulse generating circuit 11, the above-mentioned light emitting state is maintained for a time corresponding to the number of pulses to which the sustain pulse is applied. Visually,
The brightness corresponding to the time during which the light emitting state is maintained, that is, the sustain light emitting time is felt.

In order to obtain the brightness corresponding to each data bit as described above, when the row electrode drive pulse generation circuit 11 executes the light emission based on the pixel data bit D1, only one sustain pulse is supplied to the row. It is applied to the electrodes (subfield SF1). Further, when light emission based on the pixel data bit D2 is executed, two sustain pulses are continuously applied to the row electrode (subfield SF2). Further, when the row electrode drive pulse generation circuit 11 executes light emission based on the pixel data bit D3, four continuous sustain pulses are applied to the row electrode (subfield SF3). Further, when light emission based on the pixel data bit D4 is executed, eight sustain pulses are continuously applied to the row electrode (subfield S
F4).

Further, when light emission based on the pixel data bit D5 is performed, only 16 sustain pulses are applied to the row electrodes within one field period (subfield S).
F5). Further, the row electrode drive pulse generation circuit 11 applies only 32 sustaining pulses to the row electrode within one field period when executing light emission based on the pixel data bit D6 (subfield SF6). Further, when light emission based on the pixel data bit D7 is executed, only 64 sustain pulses are applied to the row electrode within one field period (subfield SF7). Further, when the light emission based on the pixel data bit D8 is executed, only 128 sustain pulses are applied to the row electrode within one field period (subfield SF8). At this time, the number of sustain pulses corresponds to the light emission time of each subfield.

Here, in the present invention, one field
Within the subfield SF8.
Field DSF8₁~ DSF8_FourIt is divided into four and arranged. Yo
The split subfield DSF8₁~ DSF8_FourEach one
The number of times of sustaining light emission handled is 32. Also, 1 field
Within the subfield SF7.
Field DSF7₁~ DSF7_FourIt is divided into four and arranged. Yo
The split subfield DSF7₁~ DSF7_FourEach one
The number of times of sustaining light emission handled is 16. Furthermore, 1 feel
Subfield SF6, the subfield
Field DSF6₁And DSF6_TwoDivided into two
You. Therefore, the divided subfield DSF6 ₁And DSF
6_TwoThe number of sustain emission times that each is responsible for is 16. Furthermore,
Within one field, the subfield SF5
Split subfield DSF5₁And DSF5_TwoDivided into two
Place it. Therefore, the divided subfield DSF5₁Over
And DSF5_TwoThe number of times of sustaining light emission for each is 8.

FIG. 4 shows these divided subfields DSF.
5 is a diagram showing a drive format during one field period in which 5 to DSF8 and subfields SF1 to SF4 are arranged. FIG. Note that W shown in each subfield in FIG. 4 indicates a light emission time corresponding to the number of sustain pulses applied in each subfield.

As shown in FIG. 4, among the subfields SF1 to SF8, the subfields SF5 to SF8 in which the weight of the pixel data bit is large are 1
It is further divided and arranged within the field period. That is, as described above, the light emission by the sub-field SF8 needs to be carried out for a time period W = 128 in one field period, but in the present invention, this is performed by each W as shown in FIG. The divided subfields DSF8 _{1 to} DSF8 ₄ that emit light over a time period of 32 are divided into four. Similarly, subfield S
Regarding the light emission by F7, W =
This needs to be done for 64 hours, which is shown in FIG.
As shown in FIG. 4, _{4 in} each of the divided sub-fields DSF7 _{1 to} DSF7 ₄ which emit light for the time of W = 16.
It is divided. Further, regarding the light emission by the sub-field SF6, it is necessary to perform the light emission for W = 32 in one field period. However, as shown in FIG. 4, each light emission is performed for the time W = 16. The divided subfields DSF6 ₁ and DSF6 ₂ are divided into two. Further, the light emission by the sub-field SF5 also needs to be carried out for a time period W = 16 in one field period, which is as shown in FIG.
Each is divided into two by the divided sub-fields DSF5 ₁ and DSF5 ₂ which emit light for a time of W = 8.

Further, in the present invention, as shown in FIG. 4, in one field, the divided subfields DSF7 and DSF8 are arranged adjacent to each other to form a divided subfield pair.
Similarly, the divided subfields DSF5 and DSF6 are also arranged adjacent to each other to form a divided subfield pair.

With this arrangement, a subfield that controls light emission with a large weight, that is, a subfield that controls light emission corresponding to a high-luminance component is divided, and within the block in which the divided subfields are arranged. Inevitably, at least one of the divided subfields adjacent to each divided subfield corresponds to a bit whose weight is different by one digit.

Therefore, according to this arrangement, the difference in emission time between adjacent subfields is reduced, and the false contour caused by this difference can be sufficiently suppressed. Here, since light emission by the subfields SF1 to SF4 corresponding to the bit with a low weight is visually inconspicuous, the false contour is not divided. These sub-fields SF1 to SF4 are executed in the central section on the time axis during one field period, as shown in FIG. These subfields SF1 to SF1
Before and after SF4, the divided subfields as described above are arranged.

The PD is processed by the method as shown in FIG.
When P12 was driven to emit light, the occurrence of false contours was suppressed, and the display quality was improved. In addition to the embodiment shown in FIG. 4, for example, in the drive patterns shown in FIGS. 5 to 9, the occurrence of false contours can be suppressed as in the above embodiment. Further, the number of pixel data bits is not limited to 8 bits as described above.
Also, the number of divisions as described above is not limited to four and two.

In short, first, the Nth subfield in which the weight of the bit digit of the pixel data bit is the largest and the (N-1) th subfield in which the weighting is one digit lower than the Nth subfield. 2n each (n is 2
The above natural number) Nth divided subfield and 2n
And the (N-2) th subfield and the (N-) th subfield.
Each 3rd subfield is divided into n (N-2) th divided subfield and n (N-3) th divided subfield. Here, in one field, the Nth subfield and the (N-1) th subfield are divided.
The second divided subfields are arranged adjacent to each other to form a first divided subfield pair, and two sets of the first divided subfield pair and the (N-2) th divided subfield and the ( It is only necessary to arrange the (N-3) th divided subfield adjacent to each other and one of the second divided subfield pairs.

Further, it is sufficient to arrange each of the sub-fields that are not divided in this way in the central section on the time axis of one field. Of the subfields SF1 to SF4 which are not divided, the subfield SF1 and the subfield SF4 may be arranged at the beginning and the end of one field period as shown in FIG.

The row electrode drive pulse generation circuit 11 and the pixel data pulse generation circuit 13 each subfield and divided subfield in order to perform the light emission drive of the PDP 12 in the form as shown in FIGS. 4 to 10 described above. Inside, application of each of the reset pulse, the scan pulse, the sustain pulse, the erase pulse, and the drive pulse such as the pixel data pulse is performed.

11 and 12 are diagrams showing the application timing of each drive pulse in one subfield according to the present invention. FIG. 11 shows the timing when one field to be driven to emit light is an odd field, while FIG. 12 is a diagram to show the timing when one field to be driven to emit light is an even field.

In FIGS. 11 and 12, first,
The row electrode drive pulse generation circuit 11 applies reset pulses R _x and R _Y to the row electrodes X and Y of the PDP 12 at the same time to initialize the residual charges of the PDP 12. Next, the pixel data pulse generation circuit 13 sequentially applies the data pulse DP corresponding to each row to the column electrode D. At the same timing as the application timing of the data pulse DP, the row electrode drive pulse generation circuit 11 causes the scan pulse S
P is sequentially applied to the row electrodes Y ₁ to Y _n in two rows simultaneously.
In this case, when one field to be emission driving is even fields, as is shown in FIG. 12, only applies a scanning pulse SP alone to the row electrodes Y _1, the row electrode Y ₁ and later ₂ scan pulses SP for the row electrodes Y _{2 to} Y _n
Simultaneous row application is performed. Pixel data is written in the row to which the scanning pulse SP is applied. At this time, the time from the application of the scan pulse SP to the row electrode Y ₁ to the application of the scan pulse SP to the row electrode Y _n is the writing time of the pixel data consumed in one subfield. .

When the scanning pulse SP is applied to the row electrode Y _n , the row electrode drive pulse generation circuit 11 causes the row electrodes X and Y to be formed.
The sustain pulses I _X and I _Y are alternately applied to. Light emission occurs each time such a sustain pulse is applied. By applying the sustain pulse, the W shown in FIGS.
When the sustain light emission is completed by the amount of, the row electrode drive pulse generation circuit 11 applies the erase pulse DP to the row electrode X of the PDP 12 to stop the light emission.

As described above, in the driving pulse applying method, the writing of the pixel data is performed simultaneously for two rows, thereby reducing the writing time of the pixel data consumed in one subfield by half. Is there. Therefore, as shown in FIGS. 4 to 10, the number of subfields (including divided subfields) in one field is smaller than that when one field is simply divided into eight subfields to perform light emission driving. Even if it is doubled, the time spent writing the pixel data can be made the same.

As described above, while subfields having a large weight are divided and separated, 2 shown in FIGS.
By using the simultaneous row writing method, it is possible to secure a sufficient writing time of pixel data and improve the image quality of a moving image.

[0037]

As is apparent from the above, in the driving method of the self-luminous display panel according to the present invention, the Nth subfield and the (N-1) th subfield in which the weight of the bit digit of the pixel data bit is the largest. Each sub-field,
It is divided into 2n (n is a natural number of 2 or more) Nth divided subfields and 2n (N-1) th divided subfields, and is divided into (N-2) th subfield and (N-2) th subfield. Each of the (N-3) th subfields is divided into the nth (N-2) th divided subfield and the nth (N-) th subfield.
3) Each of the divided subfields is divided, and the Nth divided subfield and the (N-1) th divided subfield are arranged adjacent to each other in one field to form a divided subfield pair. Two sets of subfield pairs and one of the divided subfield pairs in which the (N-2) th divided subfield and the (N-3) th divided subfield are arranged adjacent to each other are adjacent to each other. Arrange.

Therefore, in the block in which the divided subfields are arranged, at least one of the divided subfields adjacent to each divided subfield always corresponds to a bit whose weight is different by one digit. Therefore, the difference in emission time between adjacent divided subfields is reduced, and the false contour caused by this difference can be sufficiently suppressed.

[Brief description of drawings]

FIG. 1 is an explanatory diagram showing a light emitting period of each subfield and a correspondence relationship between unit pixel data and a light emitting period.

FIG. 2 is a diagram showing an example of a state in which a false contour is generated.

FIG. 3 is a block diagram showing a plasma display panel and a driving apparatus thereof for executing a driving method according to the present invention.

FIG. 4 is a diagram showing an example of a light emission drive format during one field period according to the method for driving a self-luminous display panel of the present invention.

FIG. 5 is a diagram showing an example of a light emission drive format during one field period according to the method for driving a self-luminous display panel of the present invention.

FIG. 6 is a diagram showing an example of a light emission drive format during one field period according to the method for driving a self-luminous display panel of the present invention.

FIG. 7 is a diagram showing an example of a light emission drive format during one field period according to the method for driving a self-luminous display panel of the present invention.

FIG. 8 is a diagram showing an example of a light emission drive format during one field period according to the method for driving a self-luminous display panel of the present invention.

FIG. 9 is a diagram showing an example of a light emission drive format during one field period according to the method for driving a self-luminous display panel of the present invention.

FIG. 10 is a diagram showing an example of a light emission drive format during one field period according to the method for driving a self-luminous display panel of the present invention.

FIG. 11 is a diagram showing drive pulse application timing in an odd field.

FIG. 12 is a diagram showing drive pulse application timing in an even field.

[Description of Signs of Main Parts]

 11 row electrode drive pulse generation circuit 12 prosma display panel 13 pixel data pulse generation circuit

Claims (9)

[Claims] 1. A plurality of sub-fields, each of which emits light for a time corresponding to weighting of each bit digit of N (N is a natural number) bit pixel data according to the brightness of each pixel of each field of a video signal. A method of driving a self-luminous image display panel for performing light-emission display for one field by using 2n (n is 2 or more) of the Nth subfields in which the weighting of the bit digit is the largest among the subfields. (N-th) sub-field divided into Nth sub-fields, and the (N-)
The (1) th subfield is divided into 2n numbered (N-1) th subfields, and the (N-2) th subfield having the highest weighting next to the (N-1) th subfield. Is divided into n (N−2) th subfields, and the (N−3) th subfield having the next largest weighting is divided into nth (N−2) th subfield. (N
-3) divided into sub-fields, the N-th divided sub-field and the (N-1) -th divided sub-field are arranged adjacent to each other, two first divided sub-field pairs; Each of the (N-2) th divided subfields and one of the second divided subfield pairs in which the (N-3) th divided subfields are arranged adjacent to each other. A method for driving a self-luminous image display panel, comprising: 2. The method for driving a self-luminous image display panel according to claim 1, wherein the second divided subfield pair is arranged between two of the first divided subfield pairs in one field. . 3. In one field, two of said first divided subfield pairs are arranged adjacent to each other, and immediately after that, said second divided subfield pairs are arranged. Driving method for luminescent image display panel. 4. The method for driving a self-luminous image display panel according to claim 1, wherein a subfield having a smaller weighting of the bit digit is arranged in a central section on the time axis of the one field. 5. The method for driving a self-luminous image display panel according to claim 1, wherein N = 8 and n = 2. 6. The Nth subfield is equally divided into 2n Nth division subfields, and the (N-1) th subfield is divided.
Numbered subfield is equally divided into 2n numbered (N-1) th divided subfields, and said (N-2) th subfield is equally divided into n numbered (N-2) th divided subfields. , The (N−3) th subfield to the nth (N−th)
3. The method for driving a self-luminous image display panel according to claim 1, wherein the sub-fields are equally divided into No. 3) subfields. 7. A plurality of sub-fields, each of which emits light for a time corresponding to weighting of each bit digit of N (N is a natural number) bits of pixel data according to the brightness of each pixel of each field of the video signal. A method of driving a self-luminous image display panel for performing light-emission display for one field, wherein the subfield is divided by a larger number of divisions as the weighting of the bit digit is larger, and the plurality of divided subfields are divided. One of a plurality of subfields including m subfields with different weighting
Drive in a self-luminous image display panel, characterized in that at least one subfield adjacent to each subfield is arranged so as to correspond to a bit different by one digit in each block. Method. 8. The method for driving a self-luminous image display panel according to claim 7, wherein a subfield having a smaller weighting of the bit digit is arranged in a central section on the time axis of the one field. 9. A plurality of row electrodes and a plurality of column electrodes arranged in a direction orthogonal to each of the row electrodes, each bit of pixel data corresponding to the luminance of each image of each field of the video signal. A method for driving a self-luminous image display panel that performs light emission display for one field in a plurality of subfields that emit light for a time corresponding to digit weighting, wherein the bit digit weighting in the subfields is performed. At least one subfield including a large subfield is divided into a plurality of divided subfields, and each of the divided subfields is arranged at a predetermined interval within the period of the one field. Sometimes two consecutive row electrodes
Two lines of the pixel data are simultaneously written in a line-sequential manner as a scanning unit, while two consecutive row electrodes shifted by one row electrode are driven in a line-sequential manner as two line-sequential pixel data when driving an even field. A method for driving a self-luminous image display panel, which is characterized by performing simultaneous row writing.