JPH0437962A - Image reducing device - Google Patents

Abstract

PURPOSE:To prevent the deterioration of picture quality by producing a thinning pattern to attain an even thinning operation based on a reduction ratio and writing the image data into a frame memory with the use of a write clock produced from the thinning pattern. CONSTITUTION:A thinning pattern generating circuit 1 produces a thinning pattern based on an input reduction ratio in order to attain an even thinning operation. A write clock generating circuit 2 thins the basic clocks based on the thinning pattern produced by the circuit 1 and gives an output to a rewrite control circuit 3. The circuit 3 thins the video data and writes the image data into a frame memory 4 based on the write clock received from the circuit 2. As a result, the picture elements or the lines to be thinned are never unnecessarily continuous and the deterioration of picture quality can be prevented.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to an image reduction device in digital image processing equipment.

2. Description of the Related Art A conventional image reduction device is shown in FIG. The deflection circuit a5 deflects the input clock based on the parameter N determined from the reduction ratio and the mode a.

The method of mabiki is as follows. There are two modes, A and B, and in A mode, the blindness rate is 1/
When the clock becomes N, only the first clock is ignored, the other N-1 clocks are ignored, and this pattern is repeated. In the case of B mode, the spread rate is (N-1)/N, and N
-1 clock is not turned, the last clock is turned, and this pattern is repeated. The same operation is performed for the deflection circuit b6 based on the inter-parameter mode b. The basic clock input to the deflection circuit a5 is varied and input to the deflection circuit b6. Here, the basic clock is a clock corresponding to a pixel for horizontal reduction, and a clock corresponding to a horizontal line for vertical reduction. The write control circuit 7 multiplies the video data using the clock further multiplied by the multiplier circuit b6, and writes it into the frame memory 8. Note that an example of determining the parameters N and M is shown in FIG. The reduction ratio of the circuit is determined by multiplying the reduction ratios of the blind circuit a and the blind circuit S.

Problems to be Solved by the Invention In the circuit shown in FIG. 4, the blinding circuit a5 and the blinding circuit b
Since each of the pixels 6 and 6 performs independent deflection, pixels or lines are unnecessarily continuously deflected.

An example is shown in FIG. Since the reduction ratio is 10/16, which is greater than 1/2, when the clock is multiplied in a negative manner, it is not necessary to multiply two clocks in succession. However, as shown by the arrow in FIG. 6, there are cases where two clocks are periodically scattered in succession, and the discontinuity in that portion leads to deterioration of image quality.

SUMMARY OF THE INVENTION The present invention is intended to solve the problems of conventional images, and it is an object of the present invention to provide an image reduction device that performs -like scaling.

Means for Solving the Problems In order to achieve this object, the image reduction device of the present invention has a frame memory for storing image data, and a reduction rate that generates a reduction pattern having a minimum number of consecutive correction clocks. a write clock generation circuit that generates a write clock based on the overlap pattern and basic clock from the write clock generation circuit; and writing video data to the frame memory using the clock from the write clock generation circuit. It has a write control circuit that controls.

Effect: With this configuration, a pattern is generated that varies the reduction ratio in a negative manner, and the image is written to the frame memory using a write clock created based on that pattern, so the pixels or lines that are varied are unnecessarily continuous. This prevents image quality from deteriorating.

EXAMPLES Hereinafter, examples of the present invention will be described with reference to the drawings.

FIG. 1 shows the configuration of an image reduction device in an embodiment of the present invention. In FIG. 1, 1 is a diagonal pattern generation circuit that generates a clock diagonal pattern according to the reduction ratio, 2 is a write clock generation circuit that generates a basic clock based on the diagonal pattern, and 3 is a frame memory 4.
This is a write control circuit that controls writing of video data to. Next, the operation will be explained. The deflection pattern generation circuit 1 generates a deflection pattern that realizes --like deflection based on the input reduction ratio. An example of this pattern generation method will be shown later. The write clock generation circuit 2 winds a basic clock based on the winding pattern from the winding pattern generation circuit 1 and outputs it to the write control circuit 3. The write control circuit 3 reads the video data and writes the image data into the frame memory 4 in accordance with the write clock from the write clock generation circuit 2.

FIG. 2 shows an example of write clock generation in the write clock generation circuit 2. In the example where the deflection pattern length is 16 bits, when it is 0, the length is normally deflected, and when it is 1, it is not deflected. A write clock is generated by repeating this pattern.

Next, an example of a method of generating a deflection pattern in the deflection pattern generation circuit 1 will be explained. A flowchart is shown in FIG. In an example where an M-bit diagonal pattern is generated, the reduction rate is expressed as N/M.

First, if M-N≧N, calculate (M-N) ten N,
Find the quotient X1 and the remainder Ll. Next, a block BLl is generated in which 1 is followed by X×1 0s. Furthermore, N blocks BLI are connected to generate a pattern PATI. Here, if L1=0, PATI is output as a diagonal pattern. If L1≠0, the quotient X2 of N+L1 is further determined.

Next, for PATI, BLI increases φ by 1 for every X2 blocks.
Output each Ll and FAT2 as a pattern. Even in the case of M-N<N, a spiral pattern can be generated in the same manner according to the flowchart shown in FIG. An example using actual numerical values in a 16-bit diagonal pattern is shown below.

(M-N) 2N= (16-8) ÷8=1・
...φBL1=10 PAT1=1010101010101010(M-N
) ÷N=(1'6-3) ÷3=4...IBL
1=10000 PAT1=10000100001000ON+L1=
3÷1=3 FAT2=100001000010000ON÷(M
-N)=10÷(16-10)=1...4BL1=
10 PAT1 = 101010101010 (M-N) ÷ L1 depth (16-10) ÷ 4; 1...2P
AT2=1011011011011010 Effects of the Invention As described above, the present invention generates a deflection pattern that realizes --like deflection from the reduction ratio, and writes image data to the frame memory using a write clock created based on the deflection pattern. The scattered pixels or lines are not unnecessarily continuous, and deterioration of image quality can be prevented.

[Brief explanation of drawings]

FIG. 1 is a diagram showing the configuration of an image reduction device according to an embodiment of the present invention, FIG. 2 is a diagram showing an example of write clock generation by the write clock generation circuit in FIG. 1, and FIG. FIG. 4 is a diagram showing the configuration of a conventional image reduction device; FIG. 5 is a diagram showing a method for determining parameters N and M in FIG. 4; The figure is a diagram showing an example of write clock generation in FIG. 4. 1...Mabiki pattern generation circuit, 2...
・Write clock generation circuit, 3...Write control circuit, 4...Name of frame memory agent Patent attorney Shigetaka Awano Haka1jll! i
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Claims (1)

[Claims] a frame memory in which image data is written and stored; a bias pattern generation circuit that generates a write clock bias pattern with a clock number corresponding to the image reduction ratio and that minimizes the number of consecutive bias clocks; and the bias pattern generator. An image reduction device comprising: a write clock generation circuit that generates a write clock in response to a deflection pattern from the circuit; and a write control circuit that controls writing of image data to the frame memory using the clock from the write clock generation circuit.