JP2894649B2 - Image processing circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an image processing circuit having an interpolation operation for enlarging or reducing an image.

[0002]

2. Description of the Related Art Conventionally, (1) nearest neighbor interpolation, (2) linear interpolation, (3) cubic interpolation, and the like have been known and put to practical use as data interpolation methods for enlarging image data. However, in high-speed processing requiring real-time image processing, the nearest neighbor interpolation method and the linear interpolation method are widely used in consideration of the circuit scale, cost merit, and the like.

Hereinafter, a conventional example will be described with reference to the drawings.

FIGS. 5 to 9 relate to a conventional example, FIG. 5 is an explanatory diagram for explaining the nearest neighbor interpolation method, and FIG. 6 is an explanatory diagram for explaining an image enlargement process by the nearest neighbor interpolation method and the linear interpolation method. 7
FIG. 8 is an explanatory diagram illustrating a linear interpolation method, FIG. 8 is a block diagram illustrating a configuration of an image processing circuit, and FIG. 9 is an explanatory diagram illustrating image processing in a conventional image processing circuit.

In the nearest neighbor interpolation method, as shown in FIG. 5, enlargement processing is realized by continuing the same pixel data a plurality of times. This method has a very small circuit scale and can be easily realized, but is not suitable for a high magnification or a magnification expressed as a fraction. For example, if the original image shown in FIG. 6A is magnified four times, the image is enlarged as shown in FIG. 6B and the image becomes mosaic, so that the image is degraded. Further, in the case of 4/3 magnification, the image is enlarged as shown in FIG. 6C, and the image is distorted.

In the linear interpolation method, as shown in FIG. 7, for pixel data d1 and d2 of arbitrary two points D1 and D2, pixel data i of a pixel I obtained by interpolation is obtained by setting the distance between I and D1 to x. , I and D2 as y, the line segments ID1, ID2
D1 and d2 are weighted to the reciprocal ratio of the distance, and are obtained by the following equation.

I = d 1 · y / (x + y) + d 2 · x / (x + y) where y = a 1, x = a 2, x + y = b, i = d 1 · a 1 / b + d 2 · a 2 / b (b = a1 + a2) (1) That is, for example, d1 = 5, d2 = 15, x: y = 2:
Assuming that 3, i becomes i = 5.3 / (2 + 3) + 15.2 / (2 + 3) = 9 from equation (1).

The enlargement by this method is described in detail in Japanese Patent Application Laid-Open No. 63-002044 previously filed by the present applicant.

With this method, when the original image shown in FIG. 6A is enlarged four times, if the data word length can be made sufficiently long in the course of the operation, a smooth image as shown in FIG. 6D can be obtained. Can be Further, even for 4/3 magnification, if the data word length is sufficiently long, a smooth image as shown in FIG. 6E can be obtained.

[0010]

However, in a practical circuit requiring high speed, the data word length cannot be made sufficiently long from the viewpoint of circuit size and cost. Will occur.
One example will be described below.

FIG. 8 is a block diagram showing the configuration of a circuit for realizing the interpolation enlargement method according to the equation (1).

The input image data transferred to the image memory 101 is written into the image memory 101 at a predetermined timing by a memory read (R) / write (W) controller 102. Next, data necessary for interpolation expansion is stored in the memory R
/ W controller 102 sequentially selects and distributes to two latches 104 and 105 via switch 103. The data is synchronized by the latches 104 and 105, and a look-up table circuit (hereinafter, LUT)
(Abbreviated as). LUT10
In steps 6 and 107, the coefficient is multiplied by the output from the coefficient generator 108 and output to the adder 109. The adder 109 adds these data and outputs the result as interpolation enlarged data.

In the conventional example having such a circuit configuration, in order to perform the interpolation enlargement method represented by the above equation (1), × 0/4, × 1/4, × 1 2/4,
A LUT of x3 / 4 and x4 / 4 is prepared.

However, if the data word length is limited to 8 bits, the data of each LUT must be rounded to the nearest decimal point. As a method of rounding a decimal part, generally, rounding down, rounding up, and rounding are often used.
Table 1 shows data of x 1/4, d x 3/4, d x 1/4 + d x 3/4.

[0015]

[Table 1]

The sum of Table 1, that is, d × １ ／ + d × 3
As is clear from the column of / 4, if a rounding error has not occurred in the input data d, it should be d × + d × 3/4 = d. However, any rounding method does not always return to the original data.

In the case of rounding up, when d = 255, d.times.1 / 4 + d.times.3 / 4 = 256, and overflow occurs without being contained in 8-bit data. This also occurs, for example, in the case of rounding when the coefficient is 1/2.

An example of the case where the LUT is used to enlarge by a factor of four according to the equation (1) will be described with reference to FIG. Here, the details of the interpolation enlargement method are described in the above-mentioned JP-A-63-002044.
No particular explanation is given.

FIG. 9A shows the pixel position in the horizontal direction and the data level in the vertical direction. Using this as the original image, the image is enlarged four times.

FIG. 9 shows the result of using the LUT by truncation.
(B) The result of using the LUT by truncation is shown in FIG.
(C), the result using the rounded LUT is shown in FIG.
(D). Therefore, the image processing circuit using each LUT has a disadvantage that interpolation cannot be performed smoothly.

The present invention has been made in view of the above circumstances, and can reduce an arithmetic error without increasing a data word length, and realize an image processing circuit capable of realizing a reduction in circuit scale, simplification, and cost reduction. It is intended to provide.

[0022]

An image processing circuit according to the present invention is an image processing circuit for obtaining interpolation data by a product-sum operation of image data of at least two pixels. First multiplying means for rounding up the result to an effective data length and outputting the result, at least one second multiplying means for rounding down the result of the product operation of the interpolation coefficient and the input pixel data to an effective data length and outputting the result, 1
An adder is provided for adding the output of the multiplier and the output of the second multiplier and outputting the result.

[0023]

The first multiplying means rounds up the result of the product operation of the interpolation coefficient and one input pixel data to an effective data length for the input of at least two pixel data and outputs the result. The result of the product operation of the interpolation coefficient and the remaining input pixel data is truncated to an effective data length by the multiplying means and output, and the output of the first multiplying means and the output of the second multiplying means are added by the adding means. Output.

[0024]

Embodiments of the present invention will be described below with reference to the drawings.

FIGS. 1 to 4 relate to an embodiment of the present invention. FIG. 1 is a block diagram showing a conceptual configuration of an image processing circuit.
Is a block diagram showing a circuit configuration of the image processing circuit, and FIG.
FIG. 4 is a diagram illustrating a memory map showing a configuration of a memory of the UT.

As shown in FIG. 1, the image processing circuit 1 of this embodiment multiplies two original pixel data D1 and D2 by multiplying the result of a product operation with an interpolation coefficient to an effective data length and outputs the result. Means 2, a multiplication means 3 for truncating the result of the product operation of the interpolation coefficient to an effective data length and outputting the result, a coefficient generation means 4 for outputting a coefficient to the multiplication means 2 and 3, and a multiplication means 2 and 3. And an adding means 5 for adding outputs. (Note that, as described later, when the multiplying means 2 and 3 are LUTs using a memory, the multiplying means may be configured as a single memory.) The circuit of such an image processing circuit 1 As shown in FIG. 2, the configuration includes a first LUT 2a as the multiplying means 2, an LUT 3a as the multiplying means 3, a coefficient generator 4a as the coefficient generating means 4, and an adder 5a as the adding means 5. For example, in the conventional image processing circuit shown in FIG. 8, the output of the latch 104 is input to the first LUT 2a as the original pixel data D1, and the output of the latch 105 is the second LUT 3 as the original pixel data D2.
a. Also, the first LUT2
a and the second LUT 3a are configured by, for example, a memory map as shown in FIG.

Next, the operation of the image processing circuit 1 configured as described above will be described.

The original pixel data D1 is input to the LUT 2a, and the original pixel data D2 is input to the LUT 3a. In synchronization with the timing of this input, the coefficient generator 4a
Outputs a desired coefficient to each of the LUT 2a and the LUT 3a. The LUT 2a and LU
T3a selects a table of coefficients. At this time, when one LUT selects a table by rounding down, the other LUT selects a table by rounding up. The method of selecting the coefficient is set to be 1 when both coefficients are added.

When a table is selected in this way,
The LUTs 2a and 3a output the table and data corresponding to the values of the input original pixel data D1 and D2 to the adder 5a. The adder 5a includes an LUT 2a, an LU
These two data from T3a are added and output as interpolation data.

By the image processing circuit 1 of this embodiment, for example, when the above-mentioned original image of FIG.
A smooth enlarged image as shown in FIG. 4 can be obtained.

In other words, by performing an operation of rounding up the result of the product operation of the input of the two original pixel data and the interpolation coefficient on one side and cutting off the other on the other side, the operation error can be reduced without increasing the data word length. This makes it possible to obtain a smooth enlarged image at low cost and with a small circuit scale.

[0032]

As described above, according to the present invention, the image processing circuit according to the present invention is configured such that the first multiplying means applies an interpolation coefficient and 1 to at least two pixel data inputs.
The result of the product operation of the two input pixel data is rounded up to the effective data length and output. The result of the product operation of the interpolation coefficient and the remaining input pixel data is rounded down to the effective data length by the second multiplication means. Since the output of the first multiplication means and the output of the second multiplication means are added and output by the addition means, the calculation error can be reduced without increasing the data word length, and the circuit scale can be reduced and simplified. This has the effect that cost reduction can be realized.

[Brief description of the drawings]

FIG. 1 is a configuration diagram illustrating a conceptual configuration of an image processing circuit according to an embodiment.

FIG. 2 is a block diagram illustrating a circuit configuration of an image processing circuit according to one embodiment.

FIG. 3 is a memory map showing a configuration of a memory of an LUT according to one embodiment.

FIG. 4 is an explanatory diagram illustrating a result of image processing according to one embodiment.

FIG. 5 is an explanatory diagram illustrating a nearest neighbor interpolation method according to a conventional example.

FIG. 6 is an explanatory diagram for explaining an image enlargement process by a nearest neighbor interpolation method and a linear interpolation method according to a conventional example.

FIG. 7 is an explanatory diagram illustrating a linear interpolation method according to a conventional example.

FIG. 8 is a block diagram illustrating a configuration of an image processing circuit according to a conventional example.

FIG. 9 is an explanatory diagram illustrating image processing in a conventional image processing circuit according to a conventional example.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 ... Image processing circuit 2 ... Multiplication means 2a ... 1st LUT 3 ... Multiplication means 3a ... 2nd LUT 4 ... Coefficient generation means 4a ... Coefficient generator 5 ... Addition means 5a ... Adder

────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Masahito Goto 2-43-2 Hatagaya, Shibuya-ku, Tokyo Inside O-Limpus Optical Co., Ltd. (72) Inventor Akinobu Ukubo 2-43-2 Hatagaya, Shibuya-ku, Tokyo No. Within Olympus Optical Co., Ltd. (72) Inventor Yuta Nakagawa 2-43-2 Hatagaya, Shibuya-ku, Tokyo Inside Olympus Optical Co., Ltd. (72) Akihiro Miyashita 2-34-2 Hatagaya, Shibuya-ku, Tokyo No. Olympus Optical Co., Ltd. (56) References JP-A-3-138777 (JP, A) (58) Fields investigated (Int. Cl. ⁶ , DB name) G06T 3/40 G09G 5/36 520 H04N 1/387 101-1/393

Claims (1)

(57) [Claims] At least an image processing circuit for obtaining interpolation data by a product-sum operation of image data of two or more pixels, wherein a result of a product operation of an interpolation coefficient and input pixel data is rounded up to an effective data length and output. 1 multiplying means, at least one second multiplying means for rounding down a result of a product operation of an interpolation coefficient and input pixel data to an effective data length and outputting the result, an output of the first multiplying means, and a second multiplying means And an adding means for adding and outputting the output of the image processing circuit.