JPS61194862A - Lead frame and manufacture thereof - Google Patents

Lead frame and manufacture thereof

Info

Publication number
JPS61194862A
JPS61194862A JP60035829A JP3582985A JPS61194862A JP S61194862 A JPS61194862 A JP S61194862A JP 60035829 A JP60035829 A JP 60035829A JP 3582985 A JP3582985 A JP 3582985A JP S61194862 A JPS61194862 A JP S61194862A
Authority
JP
Japan
Prior art keywords
lead
portions
lead frame
cutting line
adjacent
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP60035829A
Other languages
Japanese (ja)
Inventor
Yoshiharu Koizumi
祥治 小泉
Katsuyuki Tanaka
克幸 田中
Miki Imai
三喜 今井
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Shinko Electric Industries Co Ltd
Original Assignee
Shinko Electric Industries Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Shinko Electric Industries Co Ltd filed Critical Shinko Electric Industries Co Ltd
Priority to JP60035829A priority Critical patent/JPS61194862A/en
Publication of JPS61194862A publication Critical patent/JPS61194862A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/48Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495Lead-frames or other flat leads
    • H01L23/49541Geometry of the lead-frame
    • H01L23/49548Cross section geometry
    • H01L23/49551Cross section geometry characterised by bent parts
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item

Landscapes

  • Physics & Mathematics (AREA)
  • Geometry (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Wire Bonding (AREA)
  • Lead Frames For Integrated Circuits (AREA)

Abstract

PURPOSE:To form a multi-pin lead frame in which almost no interval exists by a method wherein each lead is bent so as to have a step between an adjacent lead and itself. CONSTITUTION:A large number of internal leads 18 surround a stage 12 radially and are connected to an outside frame 16 by external ends of external leads 20 which extend outward. The tip part of the internal lead 18 is separated from an adjacent internal lead 18 by a cut line 24 over a predetermined range and at the same time bent at suitable positions of the lead so as to have a step between the adjacent internal lead 18 and itself. With these steps, ends of the internal leads 18 are prevented from contacting each other at the cut line 24 parts so that required dielectric strength is maintained.

Description

【発明の詳細な説明】 (産業上の利用分野) 本発明は半導体装置に用いるリードフレームおよびその
製造方法に関するものである。
DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a lead frame used in a semiconductor device and a method for manufacturing the lead frame.

(背景技術およびその問題点) 近年半導体素子は高密度化の一途を辿っており、これに
用いるリードフレームも多ピン化を余儀なくされている
(Background Art and Problems Therewith) In recent years, semiconductor devices have been becoming more and more densely packed, and the lead frames used therefor have been forced to have a larger number of pins.

このようなリードフレームの多ピン化には種々の問題点
がある。
There are various problems with increasing the number of pins in such a lead frame.

すなわち、半導体素子が高密度化しても半導体素子自体
は大型化するものではなく、半導体製造技術の進歩向上
により、むしろ高密度化に伴って小型化する傾向にある
That is, even if semiconductor elements become denser, the semiconductor elements themselves do not become larger; rather, due to advances in semiconductor manufacturing technology, they tend to become smaller as the density increases.

そしてまた、半導体素子とのワイヤーボンディングの信
頼性を確保したり、抜・れ等の防止のため一定の機械的
強度を確保する必要上、リード幅は一定幅以上を確保す
る必要がある。
Furthermore, it is necessary to ensure the lead width to be at least a certain width in order to ensure the reliability of wire bonding with the semiconductor element and to ensure a certain mechanical strength to prevent pull-outs and the like.

以上の事情から、リードフレームの多ビン化を図るには
、リード間隔を狭めるか、あるいは第8図の(a)から
(b)に示すように、リード先端で構成する窓辺を大き
く設定する他ない。
Given the above circumstances, in order to increase the number of bins in a lead frame, it is necessary to narrow the lead spacing or to make the window formed by the lead tips larger, as shown in Figure 8 (a) to (b). do not have.

ところで、リードフレームの製造はプレス加工によるも
のがほとんどであるが、このプレス加工において、リー
ド間隔を狭めるには限界がある。
Incidentally, most lead frames are manufactured by press working, but there is a limit to how narrow the lead spacing can be in this press working.

すなわちポンチの座屈防止のため、打ち抜き加工による
抜き幅は一般に材厚程度が限界とされるからである。し
たがって、例えば材厚が0.25mmのものであれば、
抜き幅は0.25mm以下にすることは難かしい。この
ように、リード間隔を狭めるにも加工上の制約があるの
である。なおリードフレームの製造には、化学的エツチ
ングによる方法も採用されているが、リード間隔はやは
り材厚程度以下とすることは困難とされている。
That is, in order to prevent buckling of the punch, the width of the punching process is generally limited to the thickness of the material. Therefore, for example, if the material thickness is 0.25 mm,
It is difficult to reduce the punching width to 0.25 mm or less. In this way, there are processing constraints to narrowing the lead spacing. Note that chemical etching is also used to manufacture lead frames, but it is still difficult to make the lead spacing less than the thickness of the material.

また、第8図(1))のように窓辺を大きくすれば多ピ
ン化は可能であるが、半導体装置の小型化という要請に
反するばかりか、リード先端と半導体素子との間のボン
ディング距離が長くなり、ポジディングワイヤー間の接
触事故を招来する原因となりかねない。
Furthermore, as shown in Figure 8 (1)), it is possible to increase the number of pins by increasing the window size, but this not only goes against the demand for miniaturization of semiconductor devices, but also reduces the bonding distance between the lead tip and the semiconductor element. This may result in a contact accident between the positive wires.

なお、第9図に示すように、リード間隔をできるだけ狭
めて加工し、リード先端を一本おきに異なった高さに配
設することによって、多ピン化とリード間の充分な絶縁
耐圧を維持したリードフレームが知られているが(特開
昭59−27558号)、この場合にも上記のプレス加
工や化学的エツチング加工による方法では、リード間隔
を狭めるには限界があることは上述の通りであり、多ビ
ン化にも限界がある。
As shown in Figure 9, by processing the leads to make them as narrow as possible and arranging every other lead tip at a different height, we can maintain a large number of pins and maintain sufficient dielectric strength between the leads. A lead frame is known (Japanese Unexamined Patent Publication No. 59-27558), but as mentioned above, there is a limit to narrowing the lead spacing using the above-mentioned methods such as pressing or chemical etching. Therefore, there is a limit to increasing the number of bins.

(発明の概要) 本発明は上記問題点を解消すべくなされたものであり、
多ピン化の要請に応えることのできるリードフレームお
よびその効果的な製造方法を提供することを目的とし、
次の構成を備える。
(Summary of the invention) The present invention has been made to solve the above problems,
Our aim is to provide a lead frame that can meet the demands for increased pin count and an effective method for manufacturing it.
It has the following configuration.

すなわち、半導体素子とボンディングワイヤーで接続さ
れる多数本のリード部が、接続すべき半導体素子周辺に
密に位置するよう形成されるリードフレームにおいて、 前記リード部は、少なくとも前記ボンディングワイヤー
が接続される先端部から所定長部分が、互いに隣接する
リード部とは切断線によって分離されているとともに、
少なくとも該切断線によって分離されている部分が互い
に隣接するリード部相互間で段差を有するように曲折さ
れて成ることを特徴とする。
That is, in a lead frame in which a large number of lead parts connected to a semiconductor element by bonding wires are formed so as to be closely located around the semiconductor element to be connected, the lead parts are connected to at least the bonding wires. A predetermined length portion from the tip portion is separated from adjacent lead portions by a cutting line, and
At least the portion separated by the cutting line is bent so as to have a step between adjacent lead portions.

また、半導体素子とボンディングワイヤーで接続される
多数本のリード部が、接続すべき半導体素子周辺に密に
位置するよう形成されるリードフレームの製造方法にお
いて 前記リード部となる部分が、少なくとも前記ボンディン
グワイヤーが接続される先端部から所定長部分が互いに
隣接するリード部となる部分とほぼV字状の切れ込みが
形成された薄肉部で繋がるように予備切断線を形成する
予備成形工程と、該予備成形工程で形成された予備切断
線の谷線で切断してリード部を分離するプレス工程と、
該分離されたリード部を、少なくとも前記切断線によっ
て分離されている部分が互いに隣接するリード部相互間
で段差が形成されるように曲折すするプレス工程とを有
することを特徴とする。
Further, in a method for manufacturing a lead frame in which a large number of lead portions connected to a semiconductor element by bonding wires are formed so as to be closely located around a semiconductor element to be connected, the portions that become the lead portions are connected to at least the bonding wires. a pre-forming step in which a pre-cutting line is formed so that a predetermined length portion from the tip end to which the wire is connected is connected to a portion that will become the adjacent lead portion through a thin portion in which a substantially V-shaped cut is formed; a pressing process in which the lead portion is separated by cutting along the valley line of the preliminary cutting line formed in the molding process;
The method is characterized by comprising a pressing step of bending the separated lead portions so that at least the portion separated by the cutting line forms a step between adjacent lead portions.

以上のようにリードが切断線によって分離されるから、
リード間隔の狭い多ビンのリードフレームが提供される
Since the leads are separated by the cutting line as described above,
A multi-bin lead frame with narrow lead spacing is provided.

またあらかじめ予備切断線を形成し、次いで予備切断線
の谷線で切断分離するから、プレス金型に無理がかから
ず、線状の極めて狭いリード間隔のリードフレームを製
造することができる。
Further, since a preliminary cutting line is formed in advance and then cutting and separation is performed along the valley line of the preliminary cutting line, strain is not placed on the press mold, and a linear lead frame with an extremely narrow lead interval can be manufactured.

(実施例) 以下図面に基づき本発明の好適な一実施例を説明する。(Example) A preferred embodiment of the present invention will be described below based on the drawings.

第1図は本発明に係るリードフレーム10を示す。図に
おいて12は半導体素子を搭載するステージ部であり、
ステージサポートパー14によって外枠16に連結され
ている。
FIG. 1 shows a lead frame 10 according to the present invention. In the figure, 12 is a stage section on which a semiconductor element is mounted;
It is connected to the outer frame 16 by a stage support par 14.

18は多数本の内部リード部であり、ステージ部12を
放射状に囲むとともに、外方に延出する外部リード部2
0外端で外枠16に連結する。
Reference numeral 18 denotes a large number of internal lead parts, which surround the stage part 12 in a radial manner and extend outward.
0 is connected to the outer frame 16 at the outer end.

2zは外部リード部20同志を連結するタイバーであり
、樹脂封止型半導体装置に用いられるときは、樹脂の流
れ出しを防止する、いわゆるダムバーを兼ねる。
2z is a tie bar that connects the external lead parts 20 together, and when used in a resin-sealed semiconductor device, it also serves as a so-called dam bar to prevent resin from flowing out.

本発明において特徴的なことは、内部リード部18の先
端部が所定範囲に亘って、隣接する内部リード部18と
は切断線24によって分離されるとともに、第2図から
明らかなように、互いに隣接する内部リード部18相互
間で段差を有するように、リードの適所で曲折されてい
る点にある。
The characteristic feature of the present invention is that the tip end of the internal lead part 18 is separated from the adjacent internal lead part 18 by a cutting line 24 over a predetermined range, and as is clear from FIG. This is because the leads are bent at appropriate locations so that there is a step difference between adjacent internal lead portions 18.

このように段差を設けたのは、上記切断線24の部位で
内部リード部18端縁が互いに接触するのを回避し、所
定の絶縁耐圧を維持するためである。
The reason for providing such a step is to prevent the edges of the internal lead portions 18 from coming into contact with each other at the cutting line 24 and to maintain a predetermined dielectric strength voltage.

上記の切断線24は後記するようにその幅はほとんど零
である。これによって内部リード部18の多ピン化が達
成される。
The width of the above cutting line 24 is almost zero, as will be described later. This allows the internal lead portion 18 to have a large number of pins.

第3図は他の実施例を示す。FIG. 3 shows another embodiment.

本実施例においては、上述のタイバー22は設けられず
、外枠16と外部リード部2oとの間でリードが曲折さ
れて、前述の段差を形成するようにしている。これによ
って、内部リード部18のみならず、外部リード部2o
にも隣接するもの同志間で段差を有するリードフレーム
が形成される。
In this embodiment, the above-mentioned tie bar 22 is not provided, and the leads are bent between the outer frame 16 and the external lead portion 2o to form the above-mentioned step. As a result, not only the internal lead portion 18 but also the external lead portion 2o
Also, a lead frame having a step difference between adjacent ones is formed.

本実施例は、タイバーを有さないため樹脂封止型半導体
装置用には適さないが、サーディツプ型半導体装置用の
変形タイプとして用いうる。
Although this embodiment is not suitable for resin-sealed semiconductor devices because it does not have tie bars, it can be used as a modified type for cerdip-type semiconductor devices.

上記各実施例におけるリード間の段差の形成は、第4図
(a)、(b)、(0)に示すように、一本置きの二つ
のリード群の一方のみを下方あるいは上方に曲折しても
よいし、両群を曲折するようにしてもよい。
In each of the above embodiments, the step between the leads is formed by bending only one of the two groups of every other lead downward or upward, as shown in FIGS. 4(a), (b), and (0). Alternatively, both groups may be bent.

次に第5図(a)、(b)、(C)に基づいてリードフ
レームの製造方法について述べる。
Next, a method for manufacturing a lead frame will be described based on FIGS. 5(a), (b), and (C).

まず同図(a)の帯状材30に、第1図に示したリード
フレーム10の抜きパターンに応じて所定のプレス抜き
加工を施す。このプレス抜き加工は複数回に分けて所定
部分ずつ順次加工するのでもよい。
First, the strip material 30 shown in FIG. 1A is subjected to a predetermined press punching process according to the punching pattern of the lead frame 10 shown in FIG. This press punching process may be divided into a plurality of times and sequentially processed at predetermined portions.

次に、前記の切断線24に対応する部分を、同図(b)
に示すような断面形状、すなわちほぼV字状となる予備
切断線が形成されるよう所要形状のプレス金型を用いて
予備成形を行う。この予備成形は片面側からのみ行って
もよい。しかしいずれにしても、この予備成形によって
互いに隣接する内部リード部18が予備切断線の谷の薄
肉部で繋がった状態に形成される。この予備成形は、複
数回に分けて行うことができるが、成形時の応力が一部
に集中しないように、例えば、予備成形パターンの中心
に対する両対称位置を同時に加工するようにする。
Next, the part corresponding to the above-mentioned cutting line 24 is cut as shown in FIG.
Preforming is performed using a press die having a desired shape so that a pre-cutting line having a cross-sectional shape as shown in FIG. This preforming may be performed only from one side. However, in any case, by this preforming, the inner lead portions 18 that are adjacent to each other are formed in a state in which they are connected at the thin wall portion of the valley of the preliminary cutting line. This preforming can be performed in multiple steps, but in order to prevent stress during forming from concentrating on one part, for example, both symmetrical positions with respect to the center of the preform pattern are processed simultaneously.

なお、前記の抜き加工とこの予備成形とは工程順が逆と
なってもよい。
Note that the process order of the punching process and the preforming process may be reversed.

次に同図(Q)に示すように、プレス金型を用いて、上
記予備成形によって形成された予備切断線の谷の薄肉部
の切離しを行うと同時に、分離された内部リード部18
が一本置きに段差ができるようにプレス加工を行う。こ
の分離工程と段差形成工程とは別工程であってもよい。
Next, as shown in FIG. 3(Q), a press mold is used to cut out the thin walled portion of the valley of the pre-cut line formed by the preforming, and at the same time, the separated inner lead portion 18
Pressing is performed so that every other piece has a step. The separation step and step forming step may be separate steps.

本発明方法は上記の同時工程と、別工程との両者を含む
ものである。
The method of the present invention includes both the above-mentioned simultaneous steps and separate steps.

以上のようにして所要のリードフレームの成形が行える
In the manner described above, the required lead frame can be formed.

なお同図(C)に示すように、分離された内部リード部
18間には絶縁スペーサ32を介挿してもよい。
Note that, as shown in FIG. 3C, an insulating spacer 32 may be inserted between the separated internal lead portions 18.

第6図は半導体素子34と内部リード部18間をワイヤ
ーボンディングした状態を示すが、ワイヤーボンディン
グ時には、第7図に示すように交互に段差に形成された
内部リード部18下面を支持するボンディング治具36
を用いて、内部IJ−ド部18を変形させることなく行
うことができる。
FIG. 6 shows a state in which wire bonding is performed between the semiconductor element 34 and the internal lead portion 18. During wire bonding, bonding tools are used to support the lower surface of the internal lead portion 18, which are formed in alternating steps, as shown in FIG. Ingredients 36
This can be done without deforming the internal IJ-doping section 18 using the above.

(発明の効果) 以上のように本発明によれば、リード間隔が、はとんど
零であるから、多ビンのリードフレームを提供しえ、半
導体素子の高密度化に対処することができる。また抜き
落し部分が少なくなるから材料の無駄がなくなる。さら
には同数本のリードであれば、リード先端を半導体素子
により近接配置しうるから、ボンディングワイヤーが短
かくてすみ、接触事故が少なくなるなど半導体装置とし
た場合の信頼性が向上する。
(Effects of the Invention) As described above, according to the present invention, since the lead spacing is almost zero, it is possible to provide a multi-bin lead frame and cope with the increase in the density of semiconductor devices. . Also, since there are fewer parts to remove, there is no waste of material. Furthermore, with the same number of leads, the tips of the leads can be placed closer to the semiconductor element, which reduces the need for shorter bonding wires, reduces contact accidents, and improves reliability when used as a semiconductor device.

また本発明方法によれば、あらかじめ予備切断線を形成
し、次いで予備切断線の谷線で切断するから、プレス金
型に無理がかからず、線状の極めて狭いリード間隔のリ
ードフレームを製造することができる。またさらには、
密度の高い内部パターン部において、細かな抜きくずが
発生せず、抜きくずが材料の裏面側に入り込むことに原
因する打痕の発生を抑止することができ、また抜きくず
がポンチに詰まることもないから、ポンチ欠けが生ずる
こともない。
Furthermore, according to the method of the present invention, a preliminary cutting line is formed in advance and the cutting is then performed along the valley line of the preliminary cutting line, so that no strain is placed on the press mold, and a linear lead frame with extremely narrow lead spacing can be manufactured. can do. Furthermore,
In the dense internal pattern area, small chips are not generated, and it is possible to prevent the occurrence of dents caused by chips entering the back side of the material, and also prevent chips from clogging the punch. Because there is no punch, there is no chance of chipping.

【図面の簡単な説明】 第1図は本発明に係るリードフレームの一例を示す説明
図、第2図はその内部リード部の段差の状態を示す断面
図、第3図は他の実施例を示す説明図、第4図(a)、
(b)、(C)はリードの曲折方向例を示す説明図、第
5図(&)、(b)(C)は製造工程を示す説明図、第
6図はワイヤーボンディングを施した場合の説明図、第
7図はボンディング治具を示す説明図、第8図(a)。 (b)は従来の多ピン化を図る場合の説明図、第9図は
リードに段差を設けた従来例の説明図である。 10・・・リードフレーム、12・ ・・ステージ部、
14・・・ステージサポートバー、16・・・外枠、1
8・・・内部リード部、20・・・外部リード部、22
・・・タイバー、24・・切断線、30・・・帯状材、
32・・・絶縁スペーサー、34・・・半導体素子、3
6・・・ボンディング治具。
[BRIEF DESCRIPTION OF THE DRAWINGS] Fig. 1 is an explanatory diagram showing an example of a lead frame according to the present invention, Fig. 2 is a cross-sectional view showing the state of the level difference in the internal lead part, and Fig. 3 is an explanatory diagram showing an example of the lead frame according to the present invention. An explanatory diagram showing FIG. 4(a),
(b) and (C) are explanatory diagrams showing an example of the bending direction of the lead, Figures 5 (&), (b) and (C) are explanatory diagrams showing the manufacturing process, and Figure 6 is an explanatory diagram showing an example of the bending direction of the lead. An explanatory diagram, FIG. 7 is an explanatory diagram showing a bonding jig, FIG. 8(a). (b) is an explanatory diagram of a conventional example in which the number of pins is increased, and FIG. 9 is an explanatory diagram of a conventional example in which a step is provided in the lead. 10... Lead frame, 12... Stage part,
14... Stage support bar, 16... Outer frame, 1
8... Internal lead part, 20... External lead part, 22
... tie bar, 24 ... cutting line, 30 ... strip material,
32... Insulating spacer, 34... Semiconductor element, 3
6... Bonding jig.

Claims (1)

【特許請求の範囲】 1、半導体素子とボンディングワイヤーで接続される多
数本のリード部が、接続すべき半導体素子周辺に密に位
置するよう形成されるリードフレームにおいて、 前記リード部は、少なくとも前記ボンディ ングワイヤーが接続される先端部から所定長部分が、互
いに隣接するリード部とは切断線によつて分離されてい
るとともに、少なくとも該切断線によつて分離されてい
る部分が互いに隣接するリード部相互間で段差を有する
ように曲折されて成るリードフレーム。 2、半導体素子とボンディングワイヤーで接続される多
数本のリード部が、接続すべき半導体素子周辺に密に位
置するよう形成されるリードフレームの製造方法におい
て 前記リード部となる部分が、少なくとも前 記ボンディングワイヤーが接続される先端部から所定長
部分が互いに隣接するリード部となる部分とほぼv字状
の切れ込みが形成された薄肉部で繋がるように予備切断
線を形成する予備成形工程と、 該予備成形工程で形成された予備切断線の 谷線で切断してリード部を分離するプレス工程と、 該分離されたリード部を、少なくとも前記 切断線によつて分離されている部分が互いに隣接するリ
ード部相互間で段差が形成されるように曲折するプレス
工程と を有することを特徴とするリードフレーム の製造方法。
[Scope of Claims] 1. A lead frame in which a large number of lead portions connected to a semiconductor element by bonding wires are formed so as to be closely located around the semiconductor element to be connected, wherein the lead portion is connected to at least the A predetermined length portion from the tip to which the bonding wire is connected is separated from adjacent lead portions by a cutting line, and at least the portion separated by the cutting line is adjacent to the lead portion. A lead frame that is bent so that there are steps between each other. 2. In a method for manufacturing a lead frame in which a large number of lead parts connected to a semiconductor element by bonding wires are formed so as to be closely located around the semiconductor element to be connected, the part that becomes the lead part is at least connected to the bonding wire. a preforming step of forming a preliminary cutting line so that predetermined length portions from the tip portions to which the wires are connected are connected to mutually adjacent portions that will become lead portions through a thin portion in which a substantially V-shaped cut is formed; a pressing step of separating the lead portions by cutting along the trough line of the preliminary cutting line formed in the molding step; A method for manufacturing a lead frame, comprising: a pressing step of bending so that a step is formed between the parts.
JP60035829A 1985-02-25 1985-02-25 Lead frame and manufacture thereof Pending JPS61194862A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP60035829A JPS61194862A (en) 1985-02-25 1985-02-25 Lead frame and manufacture thereof

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP60035829A JPS61194862A (en) 1985-02-25 1985-02-25 Lead frame and manufacture thereof

Publications (1)

Publication Number Publication Date
JPS61194862A true JPS61194862A (en) 1986-08-29

Family

ID=12452845

Family Applications (1)

Application Number Title Priority Date Filing Date
JP60035829A Pending JPS61194862A (en) 1985-02-25 1985-02-25 Lead frame and manufacture thereof

Country Status (1)

Country Link
JP (1) JPS61194862A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6047467A (en) * 1995-10-12 2000-04-11 Vlsi Technology, Inc. Printed circuit board layout to minimize the clock delay caused by mismatch in length of metal lines and enhance the thermal performance of microelectronics packages via conduction through the package leads

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5593245A (en) * 1979-01-05 1980-07-15 Nec Corp Lead frame
JPS55120155A (en) * 1979-03-09 1980-09-16 Nec Kyushu Ltd Semiconductor lead frame

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5593245A (en) * 1979-01-05 1980-07-15 Nec Corp Lead frame
JPS55120155A (en) * 1979-03-09 1980-09-16 Nec Kyushu Ltd Semiconductor lead frame

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6047467A (en) * 1995-10-12 2000-04-11 Vlsi Technology, Inc. Printed circuit board layout to minimize the clock delay caused by mismatch in length of metal lines and enhance the thermal performance of microelectronics packages via conduction through the package leads

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