JPH05109957A - Manufacture of resin-sealed-type semiconductor device and lead frame - Google Patents
Manufacture of resin-sealed-type semiconductor device and lead frameInfo
- Publication number
- JPH05109957A JPH05109957A JP6766992A JP6766992A JPH05109957A JP H05109957 A JPH05109957 A JP H05109957A JP 6766992 A JP6766992 A JP 6766992A JP 6766992 A JP6766992 A JP 6766992A JP H05109957 A JPH05109957 A JP H05109957A
- Authority
- JP
- Japan
- Prior art keywords
- lead frame
- resin
- die pad
- semiconductor device
- divided
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/93—Batch processes
- H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
- H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/491—Disposition
- H01L2224/4912—Layout
- H01L2224/49171—Fan-out arrangements
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
- Lead Frames For Integrated Circuits (AREA)
Abstract
Description
【０００１】[0001]
【産業上の利用分野】本発明は、種類の異なる２個の半
導体素子を１組として一体に樹脂封止したシングルエン
ドタイプ（ＴＯ形）の樹脂封止型半導体装置を実施対象
とした半導体装置の製造方法、およびこれに用いるリー
ドフレームに関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention is directed to a semiconductor device for implementing a single-end type (TO type) resin-sealed semiconductor device in which two different types of semiconductor elements are integrally resin-sealed. And a lead frame used therefor.
【０００２】[0002]
【従来の技術】頭記した樹脂封止型半導体装置の製造方
法として、リードフレームのパターンを、ダイパッドの
相互間にあらかじめダイパッドの幅寸法よりも大きな間
隔を空けるようにして成形した２組のリードフレームを
用意し、それぞれの組のリードフレームごとに異種の半
導体チップをダイパッドにマウントして半導体素子を組
立てた後に、一方のリードフレームのダイパッドが他方
のリードフレームのダイパッドの間に入って一つおきに
並ぶように２組のリードフレームを重ね合わせ、この状
態で隣り合う２個の半導体素子を１組としてモールド加
工により一体に樹脂封止し、しかる後にリードフレーム
の各連結部を切り離して半導体装置を構成するようにし
た製造方法が本発明と同一出願人より特開平１−２５１
６４９号として提案されて公知である。2. Description of the Related Art As a method of manufacturing the above-mentioned resin-encapsulated semiconductor device, two sets of leads are formed by forming a pattern of a lead frame in advance with a gap larger than the width dimension of the die pad between the die pads. Prepare a frame, mount different types of semiconductor chips for each set of lead frames on the die pad to assemble semiconductor elements, and then insert the die pad of one lead frame into the die pad of the other lead frame. Two sets of lead frames are superposed so as to be lined up every other, and in this state, two adjacent semiconductor elements are integrally set and resin-molded integrally by molding, and thereafter, each connecting portion of the lead frame is cut off to form a semiconductor. A manufacturing method for constructing a device is disclosed in Japanese Patent Application Laid-Open No. 1-251 by the same applicant as the present invention.
It is proposed and known as No. 649.
【０００３】[0003]
【発明が解決しようとする課題】ところで、前記提案の
製造方法に用いるリードフレームは材料取り効率が極め
て悪く、このことが製造コスト高を招く大きな原因とな
っている。すなわち、各組のリードフレームにはダイパ
ッド，リードを単位パターンとして各パターンの相互間
にはダイパッド１個分に相応した大きな隙間が空いてい
る。一方、周知のようにリードフレームは銅などの金属
箔を所定のパターン形状にエッチング，ないしプレスし
て加工されるものであり、前記のようにリードフレーム
のパターンに大きな隙間が空いていると、この空白部分
がデッドスペースとなって材料のロスが多くなる。By the way, the lead frame used in the above-mentioned manufacturing method has extremely poor material-taking efficiency, which is a major cause of high manufacturing cost. That is, each set of lead frames has a die pad and a lead as a unit pattern, and a large gap corresponding to one die pad is provided between the patterns. On the other hand, as is well known, the lead frame is processed by etching or pressing a metal foil such as copper into a predetermined pattern shape, and if the lead frame pattern has a large gap as described above, This blank portion becomes a dead space, resulting in a large loss of material.
【０００４】本発明は上記の点にかんがみなされたもの
であり、その目的は頭記した樹脂封止型半導体装置を対
象に、リードフレームの材料取り効率を改善して製造コ
ストの低減化が図れるようにしたリードフレーム、およ
びそのリードフレームを使用した半導体装置の製造方法
を提供することにある。The present invention has been made in view of the above points, and an object thereof is to improve the material taking efficiency of the lead frame and reduce the manufacturing cost for the resin-sealed semiconductor device described above. An object of the present invention is to provide a lead frame and a method for manufacturing a semiconductor device using the lead frame.
【０００５】[0005]
【課題を解決するための手段】上記課題を解決するため
に、本発明のリードフレームにおいては、ダイパッド，
該ダイパッドの一端より引出したリード，ダイパッドの
他端に接続したタブを単位パターンとした多数のパター
ンをタイバーと組合わせて一対のサイドレールの間に定
ピッチ間隔置きに配列し、かつ隣り合う単位パターンの
向きを交互に反転形成させて構成するものとする。In order to solve the above-mentioned problems, in the lead frame of the present invention, a die pad,
A plurality of patterns, each of which has a unit pattern of a lead drawn from one end of the die pad and a tab connected to the other end of the die pad, are combined with a tie bar at regular intervals between a pair of side rails, and adjacent units are arranged. The direction of the pattern is alternately inverted and formed.
【０００６】一方、前記構成のリードフレームを用いて
組立てる本発明の半導体装置の製造方法は、前記したリ
ードフレームを各単位パターンごとにタブを切断してダ
イパッドの向きが同じ二つのグループに分割して切り離
し、かつそれぞれの分割リードフレームごとに異種の半
導体チップをダイパッドにマウントして半導体素子を組
立てた後に、各分割リードフレームの向きを揃えてダイ
パッドが定ピッチ間隔に並ぶようにサイドレール，タイ
バーを重ね合わせ、この状態で隣り合う２個の半導体素
子を１組としてモールド加工により一体に樹脂封止し、
しかる後にリードフレームの各連結部を切断するものと
する。On the other hand, in the method of manufacturing a semiconductor device of the present invention in which the lead frame having the above-mentioned structure is assembled, the lead frame is divided into two groups having the same die pad orientation by cutting tabs for each unit pattern. After assembling the semiconductor elements by separating different semiconductor chips on the die pad for each divided lead frame and assembling the semiconductor elements, side rails and tie bars are aligned so that the divided lead frames are aligned at regular pitch intervals. Are stacked, and in this state, two adjacent semiconductor elements are treated as a set and integrally molded by resin molding,
After that, each connecting portion of the lead frame is cut.
【０００７】また、前記の製造方法において、分割リー
ドフレームを上下に重ね合わせた状態で各分割リードフ
レームのダイパッドが同一面上に並ぶようにするための
手段として、上側に並ぶ分割リードフレームについては
ダイパッドとリードとの間の連結部を下向きに曲げ加工
し、該ダイパッドとサイドレール，タイバーとの間に凹
段差を形成する方法、あるいは、上側に並ぶ分割リード
フレームのダイパッドが凹段部に、下側に並ぶ分割リー
ドフレームのダイパッドが凸段部に配列するように、各
分割リードフレームのタイバー，サイドレールに沿って
定ピッチ置きに互いに嵌まり合う凹凸段差を形成する方
法などの実施態様がある。In the manufacturing method described above, as a means for aligning the die pads of the divided lead frames on the same plane in the state where the divided lead frames are vertically stacked, the divided lead frames arranged on the upper side are A method of forming a concave step between the die pad and the side rails and the tie bar by bending the connecting portion between the die pad and the lead downward, or the die pad of the divided lead frame arranged on the upper side in the concave step portion, Embodiments such as a method of forming uneven steps to be fitted with each other at a constant pitch along the tie bars and side rails of each divided lead frame so that the die pads of the divided lead frames arranged on the lower side are arranged in a convex step portion, is there.
【０００８】[0008]
【作用】まず、上記構成のリードフレームにおいては、
２グループの単位パターンが互いに向きを逆にして交互
に入り組むようなパターンに形成されているので、各単
位パターンの間にデッドスペースとなる空白部分の発生
がなく、その分だけ高い材料取り効率が確保できる。First, in the lead frame having the above structure,
Since the unit patterns of the two groups are formed in a pattern in which the directions are opposite to each other and are interdigitated with each other, there is no blank portion that becomes a dead space between the unit patterns, and the material taking efficiency is correspondingly high. Can be secured.
【０００９】また、前記リードフレームを採用して、リ
ードフレームをダイパッドの向きが同じ同士のグループ
に二分割することにより、従来の製造方法と同様にそれ
ぞれの分割リードフレーム上に半導体素子を別々な組立
ラインで組立て、さらに各分割リードフレームの向きを
揃えてダイパッドが定ピッチ間隔に並ぶようにサイドレ
ールを重ね合わせた上で、隣合う２個の半導体素子を１
組としてトランスファモールド加工により同一パッケー
ジで一体に樹脂封止できる。なおこの場合に、上側に並
ぶ分割リードフレームについてはダイパッドとリードと
の間の連結部を下向きに曲げ加工し、該ダイパッドとサ
イドレール，タイバーとの間に凹段差を形成する方法、
あるいは、上側に並ぶ分割リードフレームのダイパッド
が凹段部に、下側に並ぶ分割リードフレームのダイパッ
ドが凸段部に配列するように、各分割リードフレームの
タイバー，サイドレールに沿って定ピッチ置きに互いに
嵌まり合う凹凸段差を形成する方法を採用することによ
り、各単位パターンのダイパッドが同一面上に並ぶこと
になるので、その後に行うモールド加工がやり易くな
る。Further, by adopting the lead frame and dividing the lead frame into two groups having the same die pad orientation, semiconductor elements are separated on each divided lead frame as in the conventional manufacturing method. After assembling on an assembly line, the divided lead frames are aligned in the same direction, the side rails are overlapped so that the die pads are arranged at regular pitch intervals, and then two adjacent semiconductor elements are combined into one.
As a set, they can be integrally resin-sealed in the same package by transfer molding. In this case, regarding the divided lead frames arranged on the upper side, a method of bending the connecting portion between the die pad and the lead downward to form a concave step between the die pad and the side rails and tie bars,
Alternatively, place the fixed lead pitches along the tie bars and side rails of each divided lead frame so that the die pads of the divided lead frames arranged on the upper side are arranged in the concave step portion and the die pads of the divided lead frame arranged in the lower side are arranged in the convex step portion. By adopting the method of forming the concave-convex steps that fit together with each other, the die pads of each unit pattern are arranged on the same surface, which facilitates the subsequent molding process.
【００１０】[0010]
【実施例】以下本発明の実施例を図面に基づいて説明す
る。まず、図１は頭記した樹脂封止型半導体装置の製造
に用いるリードフレームを示すものである。図におい
て、１，２はリードフレームの両端に並ぶサイドレー
ル、１ａ，２ａは各サイドレール１，２に定ピッチ間隔
おきに穿孔した位置決め穴、３は第１グループに属する
ダイパッド、４は第２のグループに属するダイパッド、
５は各グループのダイパッド３，４ごとにその一端から
引出したリード、６はリード５と反対側端に連結したタ
ブ、７はタイバー、８はダイパッド３，４に穿孔したね
じ止め用の穴である。Embodiments of the present invention will be described below with reference to the drawings. First, FIG. 1 shows a lead frame used for manufacturing the above-mentioned resin-encapsulated semiconductor device. In the figure, 1 and 2 are side rails arranged at both ends of the lead frame, 1a and 2a are positioning holes formed in the side rails 1 and 2 at regular pitch intervals, 3 is a die pad belonging to the first group, and 4 is a second die pad. Die pad belonging to the group
5 is a lead drawn from one end of each die pad 3, 4 of each group, 6 is a tab connected to the opposite end of the lead 5, 7 is a tie bar, 8 is a hole for screwing drilled in the die pad 3, 4. is there.
【００１１】すなわち、前記したリードフレームのパタ
ーンは、ダイパッド３ないし４と、各ダイパッドの一端
より引出したリード５，ダイパッドの他端に接続したタ
ブ６を単位パターンとして、多数の単位パターンがタイ
バー７と組合わせて一対のサイドレール１，２の間にま
たがって定ピッチ間隔に並ぶように形成されており、か
つ隣り合う単位パターンの間ではリード５，タブ６を含
めてダイパッド３と４の向きが逆向きになっている。な
お，図１（ａ）で示すように、特に第１グループに属す
るダイパッド３については、ダイパッド３とその両端に
連なるリード５，タブ６の根元部分に下向きの曲げ加工
を施し、ダイパッド３とリード５との間にリードの板厚
に相応した凹段差ｄを与えてダイパッド３が一段低く沈
むように成形されている。That is, the above-described lead frame pattern is composed of the die pads 3 to 4, a lead 5 drawn out from one end of each die pad, and a tab 6 connected to the other end of the die pad as a unit pattern, and a large number of unit patterns are formed by tie bars 7. The pair of side rails 1 and 2 are formed so as to extend side by side at a constant pitch, and between the adjacent unit patterns, the orientation of the die pads 3 and 4 including the leads 5 and the tabs 6 is included. Is in the opposite direction. As shown in FIG. 1A, particularly for the die pad 3 belonging to the first group, the die pad 3 and the root portions of the leads 5 and the tabs 6 connected to both ends of the die pad 3 are bent downward to form the die pad 3 and the lead pad. 5, the die pad 3 is formed so as to be lowered one step lower by providing a concave step d corresponding to the thickness of the lead.
【００１２】次に上記構成になるリードフレームを用い
て実施する樹脂封止型半導体装置の製造方法について述
べる。なお、ここで製造される製品は、図５で示すよう
に同一の樹脂封止形パッケージ９の中に種類の異なる２
個の半導体素子１０，１１が一体に樹脂封止されたもの
である。また、かかる複合形の半導体装置については、
その使用用途などが特開平１−２５１６４９号公報に記
載されている。Next, a method of manufacturing a resin-sealed semiconductor device, which is carried out by using the lead frame having the above structure, will be described. The products manufactured here have different types in the same resin-sealed package 9 as shown in FIG.
The individual semiconductor elements 10 and 11 are integrally resin-sealed. Further, regarding such a composite type semiconductor device,
The usage and the like are described in JP-A-1-251649.
【００１３】まず、図１に示したリードフレームについ
て、最初の工程では図中の点線に沿って各単位パターン
ごとにダイパッド３，４とタブ６との間を切断してリー
ドフレームを２分割する。これにより図２（ａ),（ｂ）
で示すような２組の分割リードフレーム１２，１３が得
られる。次の工程では、各分割リードフレーム１２，１
３に対し、それぞれ別な組立ラインで図３（ａ),（ｂ）
のようにチップを実装して半導体素子を組立てる。すな
わち、分割リードフレーム１２に対しては、各ダイパッ
ド３に例えばプレーナ型トランジスタチップ１４を、分
割リードフレーム１３に対しては各ダイパッド４にメサ
型トランジスタチップ１５をマウントし、さらにリード
５との間にワイヤボンディングを施して内部結線する。First, regarding the lead frame shown in FIG. 1, in the first step, the lead frame is divided into two by cutting between the die pads 3 and 4 and the tab 6 for each unit pattern along the dotted line in the figure. .. As a result, as shown in FIGS.
Two sets of divided lead frames 12 and 13 as shown by are obtained. In the next step, each divided lead frame 12, 1
3 in different assembly lines, as shown in FIGS. 3 (a) and 3 (b).
Assemble the chip and assemble the semiconductor device. That is, for the divided lead frame 12, for example, a planar type transistor chip 14 is mounted on each die pad 3, and for the divided lead frame 13, a mesa type transistor chip 15 is mounted on each die pad 4, and the space between the leads 5 is mounted. Apply wire bonding to and connect internally.
【００１４】続く工程では、上記のようにしてリードフ
レーム上に半導体素子を組立てた分割リードフレーム１
２，１３を一箇所に合流させた上で、図４で示すように
分割リードフレーム１２と１３の向きを揃え、かつダイ
パッド３の間にダイパッド４が入り込んでダイパッド３
と４が定ピッチ間隔で一列に並ぶようにして分割リード
フレーム１２と１３を上下に重ね合わせる。この場合
に、図１で述べたように、特に上側に並ぶ分割リードフ
レーム１２については、ダイパッド３がリード５に対し
て一段低くなるように凹段差ｄを設定しているので、図
４の重ね合わせ状態ではダイパッド３と４が同一面上に
面一に並ぶことになる。なお、前記した分割リードフレ
ーム１２と１３との間の重ね合わせ位置決めには、サイ
ドレール１，２に穿孔した位置決め穴１ａ，１ｂを利用
するものとする。In the subsequent step, the divided lead frame 1 in which the semiconductor elements are assembled on the lead frame as described above.
2 and 13 are merged into one place, the divided lead frames 12 and 13 are aligned in the same direction as shown in FIG. 4, and the die pad 4 is inserted between the die pads 3 so that the die pad 3
The divided lead frames 12 and 13 are vertically stacked so that the wirings 4 and 4 are arranged in a line at a constant pitch. In this case, as described with reference to FIG. 1, since the recessed step d is set so that the die pad 3 is one step lower than the leads 5, especially in the divided lead frames 12 arranged on the upper side, the overlapping of FIG. In the aligned state, the die pads 3 and 4 are arranged flush with each other on the same surface. It should be noted that the positioning holes 1a and 1b drilled in the side rails 1 and 2 are used for the overlapping positioning between the divided lead frames 12 and 13 described above.
【００１５】次に、図４で示した分割リードフレームの
重ね合わせ体をモールド工程に移し、図中の点線で表す
ように隣り合う２個の半導体素子、つまりダイパッド３
と４を１組としてトランジスタモールド加工により一体
に樹脂封止した後、さらにリード５，タブ６の端部とサ
イドレール１，２およびタイバー７との間を切断し、図
５に示した複合形の樹脂封止型半導体装置の製品を完成
する。Next, the overlapped body of the divided lead frames shown in FIG. 4 is transferred to a molding process, and two semiconductor elements adjacent to each other, that is, the die pad 3 are represented by a dotted line in the figure.
5 and 4 as a set are integrally resin-sealed by a transistor molding process, and then the ends of the leads 5 and tabs 6 and the side rails 1 and 2 and the tie bar 7 are cut to form a composite type shown in FIG. To complete the resin-encapsulated semiconductor device product.
【００１６】次に本発明の応用実施例を図６で説明す
る。すなわち、この実施例においては、（ａ）図のリー
ドフレームに対しサイドレール１，２およびタイバー７
に沿って、図示の点線を表す箇所にはピッチ間隔を合わ
せてリードフレームの板厚に相当する高さの凹凸段差１
６を形成するように曲げ加工を施しておき、その後に先
記実施例と同様にリードフレームを二分割して（ｂ),
（ｃ）図に示す分割リードフレーム１２，１３に切り離
す。この切り離し状態では分割リードフレーム１２のダ
イパッド３が前記した凹凸段差１６のうちの凹段部１７
に連結され、一方の分割リードフレーム１３ではダイパ
ッド４が凸段部１８に連結されて配列している。したが
って、分割リードフレーム１２と１３を向きを揃えた上
で、分割リードフレーム１２を上，分割リードフレーム
１３を下にして（ｄ）図のようにサイドレール１，２お
よびタイバー７を上下に重ね合わせれば、前記の凹凸段
部１６同志が互いに嵌合し合ってダイパッド３と４とが
同一面上に並ぶようになる。Next, an application example of the present invention will be described with reference to FIG. That is, in this embodiment, the side rails 1 and 2 and the tie bar 7 are added to the lead frame shown in FIG.
Along the lines shown in the figure, the pitched intervals are aligned with the portions indicated by the dotted lines, and the uneven step 1 has a height corresponding to the thickness of the lead frame.
Bending is performed so as to form No. 6, and then the lead frame is divided into two in the same manner as in the previous embodiment (b),
(C) Separate into the divided lead frames 12 and 13 shown in the figure. In this separated state, the die pad 3 of the divided lead frame 12 has the concave step portion 17 of the uneven step 16 described above.
In one of the divided lead frames 13, the die pad 4 is connected to the convex step portion 18 and arranged. Therefore, after the divided lead frames 12 and 13 are aligned in the same direction, the divided lead frame 12 is on the upper side and the divided lead frame 13 is on the lower side, and the side rails 1 and 2 and the tie bar 7 are vertically stacked as shown in FIG. If they are combined, the uneven step portions 16 are fitted to each other so that the die pads 3 and 4 are arranged on the same plane.
【００１７】[0017]
【発明の効果】以上述べたように、種類の異なる２個の
半導体素子を同一のパッケージで一体に樹脂封止した複
合形構造の樹脂封止型半導体装置を実施対象に、本発明
によれば次記の効果を奏する。 （１）まず、請求項１のリードフレームを採用すること
により、従来では別々に作られていた２組のリードフレ
ームを、一つのリードフレームに纏めてパターン成形す
ることができ、これにより材料のロスを減じて材料取り
効率を高め、リードフレームの材料コストを大幅に節減
できる。As described above, according to the present invention, a resin-sealed semiconductor device having a composite structure in which two semiconductor elements of different types are integrally resin-sealed in the same package is implemented. It has the following effects. (1) First, by adopting the lead frame according to claim 1, two sets of lead frames, which are conventionally made separately, can be collectively formed into one lead frame, and pattern formation can be performed. It can reduce the loss, improve the material taking efficiency, and significantly reduce the material cost of the lead frame.
【００１８】（２）また、請求項２の製造方法を採用す
ることにより、前記の樹脂封止型半導体装置を量産性よ
く低コストで製造でき、さらに請求項３，ないし４の方
法を用いることで、２個の半導体素子のダイパッドが同
一面上に並ぶように高さを揃えて同一パッケージで樹脂
封止できる。(2) Further, by adopting the manufacturing method of claim 2, the resin-encapsulated semiconductor device can be manufactured with high mass productivity and at low cost. Further, the method of claims 3 to 4 is used. Then, the heights are aligned so that the die pads of the two semiconductor elements are arranged on the same surface, and the resin can be sealed in the same package.
【図１】本発明の実施例によるリードフレームのパター
ンを示し、（ａ）はリードフレームのパターンの平面
図、（ｂ）は（ａ）図における矢視Ｘ−Ｘ断面図、
（ｃ）は（ａ）図における矢視Ｙ−Ｙ断面図1A and 1B show a pattern of a lead frame according to an embodiment of the present invention, FIG. 1A is a plan view of the pattern of the lead frame, and FIG. 1B is a sectional view taken along line XX in FIG.
(C) is a cross-sectional view taken along the line YY in FIG.
【図２】図１のリードフレームを二分した後の分割状態
を示し、（ａ）は図１における上半分の分割リードフレ
ームの平面図、（ｂ）は図１における下半分の分割リー
ドフレームの平面図2 shows a split state after the lead frame of FIG. 1 is divided into two parts, (a) is a plan view of the upper half split lead frame in FIG. 1, and (b) is a lower half split lead frame of FIG. Plan view
【図３】図２の各分割リードフレームに半導体チップを
実装した半導体素子の組立状態を示し、（ａ）は図２
（ａ）の分割リードフレームに対応する図、（ｂ）は図
２（ｂ）の分割リードフレームに対応する図3 shows an assembled state of a semiconductor element in which a semiconductor chip is mounted on each divided lead frame of FIG. 2, (a) of FIG.
FIG. 2A is a diagram corresponding to the split lead frame, and FIG. 2B is a diagram corresponding to the split lead frame in FIG.
【図４】図２に示した各分割リードフレームに半導体チ
ップを実装した後、２組の分割リードフレームを重ね合
わせた状態を表す図FIG. 4 is a diagram showing a state in which a semiconductor chip is mounted on each divided lead frame shown in FIG. 2 and then two sets of divided lead frames are superposed on each other.
【図５】本発明の実施対象となる樹脂封止型半導体装置
の外形斜視図FIG. 5 is an external perspective view of a resin-encapsulated semiconductor device to which the present invention is applied.
【図６】本発明の応用実施例によるリードフレームを示
し、（ａ）は図１のリードフレームに凹凸段差を形成し
た平面図、（ｂ）は（ａ）のリードフレームを二分した
下半分の分割リードフレームの正面図、（ｃ）は（ａ）
における上半分の分割リードフレームの正面図、（ｄ）
は（ｂ),（ｃ）の分割リードフレームを上下に重ね合わ
せた状態の正面図6A and 6B show a lead frame according to an application example of the present invention, FIG. 6A is a plan view of the lead frame of FIG. 1 in which uneven steps are formed, and FIG. 6B is a lower half of the lead frame of FIG. Front view of split lead frame, (c) is (a)
Front view of the upper half split lead frame in FIG.
Is a front view of the split lead frames of (b) and (c) that are vertically stacked.
１ サイドレール ２ サイドレール ３ ダイパッド ４ ダイパッド ５ リード ６ タブ ７ タイバー ９ パッケージ １０ 半導体素子 １１ 半導体素子 １２ 分割リードフレーム １３ 分割リードフレーム １４ 半導体チップ １５ 半導体チップ １６ 凹凸段差 １７ 凹段部 １８ 凸段部 1 Side Rail 2 Side Rail 3 Die Pad 4 Die Pad 5 Lead 6 Tab 7 Tie Bar 9 Package 10 Semiconductor Element 11 Semiconductor Element 12 Divided Lead Frame 13 Divided Lead Frame 14 Semiconductor Chip 15 Semiconductor Chip 16 Uneven Step 17 Concave Step 18 Convex Step
Claims (4)
て一体に樹脂封止した樹脂封止型半導体装置に用いるリ
ードフレームであって、ダイパッド，該ダイパッドの一
端より引出したリード，ダイパッドの他端に接続したタ
ブを単位パターンとした多数のパターンをタイバーと組
合わせて一対のサイドレールの間に定ピッチ間隔置きに
配列し、かつ隣り合う単位パターンの向きを交互に反転
させて成形したことを特徴とする樹脂封止型半導体装置
のリードフレーム。1. A lead frame used in a resin-sealed semiconductor device in which two different types of semiconductor elements are integrally resin-sealed as a set, which comprises a die pad, leads drawn from one end of the die pad, and a die pad. A large number of patterns, each having a tab connected to the other end as a unit pattern, were combined with a tie bar and arranged at a constant pitch between a pair of side rails, and the directions of adjacent unit patterns were alternately inverted and molded. A lead frame for a resin-encapsulated semiconductor device, comprising:
て一体に樹脂封止した樹脂封止型半導体装置の製造方法
であって、請求項１記載のリードフレームを各単位パタ
ーンごとにタブを切断してダイパッドの向きが同じ二つ
のグループに分割して切り離し、かつそれぞれの分割リ
ードフレームごとに異種の半導体チップをダイパッドに
マウントして半導体素子を組立てた後に、各分割リード
フレームの向きを揃えてダイパッドが定ピッチ間隔に並
ぶようにサイドレール，タイバーを重ね合わせ、この状
態で隣り合う２個の半導体素子を１組としてモールド加
工により一体に樹脂封止し、しかる後にリードフレーム
の各連結部を切断することを特徴とする樹脂封止型半導
体装置の製造方法。2. A method of manufacturing a resin-encapsulated semiconductor device in which two different types of semiconductor elements are integrally resin-encapsulated as a set, and the lead frame according to claim 1 is tabbed for each unit pattern. After cutting and dividing into two groups with the same die pad orientation, and mounting different semiconductor chips on the die pad for each divided lead frame to assemble semiconductor elements, change the orientation of each divided lead frame. Side rails and tie bars are overlaid so that the die pads are aligned and arranged at regular pitch intervals, and in this state, two adjacent semiconductor elements are set as a set and integrally resin-sealed, and then each lead frame is connected. A method for manufacturing a resin-encapsulated semiconductor device, which comprises cutting a portion.
重ね合わせる分割リードフレームのうち、上側に並ぶ分
割リードフレームについてはダイパッドとリードとの間
の連結部を下向きに曲げ加工し、該ダイパッドとサイド
レール，タイバーとの間に凹段差を形成したことを特徴
とする樹脂封止型半導体装置の製造方法。3. The manufacturing method according to claim 2, wherein among the divided lead frames which are vertically stacked, the connecting portions between the die pad and the lead are bent downward for the divided lead frames arranged on the upper side, and the die pad is manufactured. A method for manufacturing a resin-sealed semiconductor device, characterized in that a concave step is formed between the side rail and the tie bar.
重ね合わせる各分割リードフレームについて、上側に並
ぶ分割リードフレームのダイパッドが凹段部に、下側に
並ぶ分割リードフレームのダイパッドが凸段部に配列す
るように、各分割リードフレームのタイバー，サイドレ
ールに沿って定ピッチ置きに互いに嵌まり合う凹凸段差
を形成したことを特徴とする樹脂封止型半導体装置の製
造方法。4. The manufacturing method according to claim 2, wherein, for each of the divided lead frames that are vertically stacked, the die pads of the divided lead frames arranged on the upper side are concave portions, and the die pads of the divided lead frames arranged on the lower side are convex steps. A method for manufacturing a resin-encapsulated semiconductor device, characterized in that concave and convex steps are formed along the tie bars and side rails of each divided lead frame so as to be fitted to each other at a constant pitch so as to be arranged in the same section.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP6766992A JP2874435B2 (en) | 1991-08-21 | 1992-03-26 | Method for manufacturing resin-encapsulated semiconductor device and lead frame |
Applications Claiming Priority (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP20836291 | 1991-08-21 | ||
| JP3-208362 | 1991-08-21 | ||
| JP6766992A JP2874435B2 (en) | 1991-08-21 | 1992-03-26 | Method for manufacturing resin-encapsulated semiconductor device and lead frame |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH05109957A true JPH05109957A (en) | 1993-04-30 |
| JP2874435B2 JP2874435B2 (en) | 1999-03-24 |
Family
ID=26408884
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP6766992A Expired - Fee Related JP2874435B2 (en) | 1991-08-21 | 1992-03-26 | Method for manufacturing resin-encapsulated semiconductor device and lead frame |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2874435B2 (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0923129A1 (en) * | 1997-12-11 | 1999-06-16 | Siemens Aktiengesellschaft | A lead frame for electronic semi-conductor devices |
| CN108405765A (en) * | 2018-05-16 | 2018-08-17 | 深圳市华龙精密模具有限公司 | A kind of tubulature device of the automatic Trim Molding equipment of semiconductor integrated circuit |
| CN113823569A (en) * | 2020-06-18 | 2021-12-21 | 吴江华丰电子科技有限公司 | Method for manufacturing electronic device |
-
1992
- 1992-03-26 JP JP6766992A patent/JP2874435B2/en not_active Expired - Fee Related
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0923129A1 (en) * | 1997-12-11 | 1999-06-16 | Siemens Aktiengesellschaft | A lead frame for electronic semi-conductor devices |
| CN108405765A (en) * | 2018-05-16 | 2018-08-17 | 深圳市华龙精密模具有限公司 | A kind of tubulature device of the automatic Trim Molding equipment of semiconductor integrated circuit |
| CN108405765B (en) * | 2018-05-16 | 2023-08-08 | 深圳市华龙精密模具有限公司 | Tubing device of automatic rib cutting and forming equipment for semiconductor integrated circuit |
| CN113823569A (en) * | 2020-06-18 | 2021-12-21 | 吴江华丰电子科技有限公司 | Method for manufacturing electronic device |
Also Published As
| Publication number | Publication date |
|---|---|
| JP2874435B2 (en) | 1999-03-24 |
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