JPH05291448A - Lead frame for semiconductor device - Google Patents
Lead frame for semiconductor deviceInfo
- Publication number
- JPH05291448A JPH05291448A JP4087381A JP8738192A JPH05291448A JP H05291448 A JPH05291448 A JP H05291448A JP 4087381 A JP4087381 A JP 4087381A JP 8738192 A JP8738192 A JP 8738192A JP H05291448 A JPH05291448 A JP H05291448A
- Authority
- JP
- Japan
- Prior art keywords
- lead frame
- semiconductor device
- unit patterns
- outer leads
- lead
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/93—Batch processes
- H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
- H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/491—Disposition
- H01L2224/4912—Layout
- H01L2224/49171—Fan-out arrangements
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/13—Discrete devices, e.g. 3 terminal devices
- H01L2924/1304—Transistor
- H01L2924/1306—Field-effect transistor [FET]
- H01L2924/13091—Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Lead Frames For Integrated Circuits (AREA)
Abstract
Description
【０００１】[0001]
【産業上の利用分野】本発明は、ＴＯ−３などで代表さ
れるシングル・エンド・タイプの樹脂封止形半導体装置
に適用するリードフレームに関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a lead frame applied to a single end type resin-sealed semiconductor device represented by TO-3.
【０００２】[0002]
【従来の技術】まず、本発明の実施対象となるシングル
・エンド・タイプの樹脂封止形半導体装置を図２に示
す。図において、１は樹脂パッケージ、２は樹脂パッケ
ージ１から同じ方向に引出した３本のアウタリードであ
り、半導体チップはリードフレームのダイパッドに搭載
して樹脂パッケージ１内に封止されている。2. Description of the Related Art First, FIG. 2 shows a single-end type resin-sealed semiconductor device to which the present invention is applied. In the figure, reference numeral 1 is a resin package, and 2 is three outer leads drawn from the resin package 1 in the same direction. A semiconductor chip is mounted on a die pad of a lead frame and sealed in the resin package 1.
【０００３】次に、図２に示した半導体装置に適用する
リードフレームの従来構造を図３に示す。図において、
３はダイパッド、４はダイパッド３から引出したアウタ
リード、５は前記リード４の両側に並ぶ別なアウタリー
ド、６は各リード４，５，６の相互間を連結したタイバ
ー、８は連結バー、９はサイドレールであり、一枚のリ
ードフレームにはダイパッド３，各リード４，５，６，
タイバー７を単位パターンとして複数の単位パターンが
一列に並んで形成されている。なお、９ａはリードフレ
ームをピッチ送りする際の位置決め穴である。Next, FIG. 3 shows a conventional structure of a lead frame applied to the semiconductor device shown in FIG. In the figure,
3 is a die pad, 4 is an outer lead drawn from the die pad 3, 5 is another outer lead arranged on both sides of the lead 4, 6 is a tie bar connecting the leads 4, 5, 6 to each other, 8 is a connecting bar, and 9 is It is a side rail, and one lead frame has a die pad 3, each lead 4, 5, 6,
A plurality of unit patterns are formed in a line with the tie bar 7 as a unit pattern. In addition, 9a is a positioning hole when the lead frame is pitch-fed.
【０００４】また、かかるリードフレームを使用して図
２の半導体装置を組立てるには、まず図４のようにダイ
パッド３に例えばＭＯＳ−ＦＥＴの半導体チップ１０の
ドレイン電極をダイボンディングし、続いてチップ１０
のゲート電極，ソース電極とアウタリード４，５との間
をボンディングワイヤ１１で接続する。次に、チップ１
０を搭載したリードフレームをトランスファモールド金
型にセットし、金型に注型樹脂を注入して樹脂パッケー
ジ１を形成する。そして、樹脂モールド後にタイバーカ
ットしてリードフレームを分離し図２の製品を得る。To assemble the semiconductor device shown in FIG. 2 using such a lead frame, first, as shown in FIG. 4, the drain electrode of, for example, a MOS-FET semiconductor chip 10 is die-bonded to the die pad 3, and then the chip is chipped. 10
The bonding electrodes 11 connect the gate electrodes and source electrodes of the outer leads 4 and 5. Next, chip 1
The lead frame on which 0 is mounted is set in a transfer mold, and a casting resin is injected into the mold to form a resin package 1. Then, after resin molding, tie bar cutting is performed to separate the lead frame to obtain the product of FIG.
【０００５】[0005]
【発明が解決しようとする課題】ところで、前記のリー
ドフレームを製造するには、一般に銅，あるいは鉄−ニ
ッケル合金などの金属フープ材を材料とし、プレス加
工，フォトエッチング加工法などにより図３のようなパ
ターンを形成するようにしている。一方、リードフレー
ムの製造コストについては金属材料費が加工費よりも高
いことから、製造コストの低減化を進めにには設計の段
階でパターンのスペース効率如何にして高めるか、つま
り金属材料の利用率を如何にして高めるかが大きなポイ
ントになる。In order to manufacture the above-mentioned lead frame, generally, a metal hoop material such as copper or iron-nickel alloy is used as a material, and a press working, a photo-etching working method or the like as shown in FIG. It is designed to form such a pattern. On the other hand, regarding the manufacturing cost of the lead frame, the metal material cost is higher than the processing cost. Therefore, in order to reduce the manufacturing cost, how to improve the space efficiency of the pattern at the design stage, that is, the use of the metal material The big point is how to raise the rate.
【０００６】かかる点、図３に示した従来のリードフレ
ームのパターンを考察すると、各単位パターンのアウタ
リードの相互間には大きな隙間の空白部分が存在し、し
かもこの空白部分に相応する材料はプレスの打ち抜きな
どにより除かれ、破材として処分されるので金属材料
（フープ材）の利用効率が低く、このことが材料費，製
造コストを押し上げる大きな要因となっている。Considering this point, the pattern of the conventional lead frame shown in FIG. 3 has a blank portion with a large gap between the outer leads of each unit pattern, and the material corresponding to this blank portion is pressed. The metal material (hoop material) is not used efficiently because it is removed by punching or the like and disposed of as a broken material, which is a major factor in increasing the material cost and the manufacturing cost.
【０００７】本発明は上記の点にかんがみなされたもの
であり、その目的は前記課題を解決し、パターンのレイ
アウトを高密度化して金属材料の利用効率の向上が図れ
るようにしたリードフレームを提供することにある。The present invention has been made in view of the above points, and an object thereof is to solve the above problems and provide a lead frame in which the layout of patterns is increased in density to improve the utilization efficiency of a metal material. To do.
【０００８】[0008]
【課題を解決するための手段】上記目的を達成するため
に、本発明のリードフレームにおいては、単位パターン
を二列に振り分け、かつ各列の単位パターンの向きを互
いに反転させて千鳥状に配列し、しかも各列の単位パタ
ーンのアウタリードが反対方向から互い違いに入り組む
ように並べて形成するものとする。In order to achieve the above object, in the lead frame of the present invention, the unit patterns are arranged in two rows, and the directions of the unit patterns in each row are reversed and arranged in a zigzag pattern. In addition, the outer leads of the unit patterns in each row are formed side by side so that they are interdigitated from the opposite direction.
【０００９】また、前記構成の実施態様として、単位パ
ターンのアウタリードの先端を反対側列のタイバーに連
結した構成、および二列に並ぶ単位パターンのタイバー
同士を結んで隣り合う単位パターンの間に連結バーを形
成した構成などがある。Further, as an embodiment of the above-mentioned constitution, the outer leads of the unit patterns are connected to the tie bars in the opposite row, and the tie bars of the unit patterns arranged in two rows are connected to be connected between adjacent unit patterns. There is a configuration in which a bar is formed.
【００１０】[0010]
【作用】上記の構成によれば、二列に振り分けた単位パ
ターンのアウタリードが交互に入り組んで一列に並んで
おり、アウタリードの長さ分に相当する幅の領域に二列
分のアウタリードがパターン形成されている。したがっ
て、アウタリードの相互間に隙間として残る空白部分は
極僅となり、これにより金属フープ材利用効率が高ま
る。According to the above construction, the outer leads of the unit pattern distributed in two rows are alternately arranged and arranged in one row, and two rows of outer leads are patterned in a region having a width corresponding to the length of the outer leads. Has been done. Therefore, a blank portion that remains as a gap between the outer leads becomes very small, which improves the utilization efficiency of the metal hoop material.
【００１１】[0011]
【実施例】図１は本発明の実施例を示すものであり、図
３に対応する同一部分には同じ符号が付してある。すな
わち、図示実施例においては、一枚のリードフレームに
ダイパッド３，アウタリード４〜６，タイバー７からな
る単位パターンが上下二列に振り分けて形成されてい
る。ここで上列の単位パターンと下列の単位パターンと
は互いに向きを反転して千鳥状に並び、かつ上列と下列
の単位パターンの各アウタリード４，５，６が反対方向
から互い違いに入り組むように横一列に整列している。
また、各単位パターンのアウタリード３，４，５の先端
は先細り形状にして反対側列のタイバー７に連結されて
おり、さらに上下二列に並ぶタイバー７同士の間を連ね
て隣り合う単位パターンの間には補強用の連結バー８が
形成されている。なお、この連結バー８にはピッチ送り
用の位置決め穴８ａが穿孔されている。DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 1 shows an embodiment of the present invention, in which the same parts corresponding to those in FIG. 3 are designated by the same reference numerals. That is, in the illustrated embodiment, a unit pattern consisting of the die pad 3, the outer leads 4 to 6, and the tie bar 7 is formed in one upper and lower two rows on one lead frame. Here, the unit patterns in the upper row and the unit patterns in the lower row are arranged in a zigzag pattern with their directions reversed, and the outer leads 4, 5, 6 of the unit patterns in the upper row and the lower row are arranged in a staggered manner in opposite directions. They are arranged in a horizontal row.
Further, the tips of the outer leads 3, 4, 5 of each unit pattern are tapered and are connected to the tie bars 7 in the opposite row, and the tie bars 7 arranged in the upper and lower two rows are connected to each other. A connecting bar 8 for reinforcement is formed between them. The connecting bar 8 has a positioning hole 8a for pitch feeding.
【００１２】なお、かかるリードフレームを採用して図
２に示した樹脂封止形半導体装置を組立てるには、図４
で述べたと同様にリードフレームの各単位パターンごと
にダイパッド３に半導体チップ１０をマウントし、かつ
半導体チップ１０の電極とアウタリード５，６との間に
ボンディングワイヤ１１を接続し、この状態でトランス
ファモールドにより樹脂パッケージ１（図２参照）を成
形した後、タイバーカットを施して半導体装置の製品を
完成する。In order to assemble the resin-encapsulated semiconductor device shown in FIG. 2 by using such a lead frame, the process shown in FIG.
As described above, the semiconductor chip 10 is mounted on the die pad 3 for each unit pattern of the lead frame, and the bonding wire 11 is connected between the electrode of the semiconductor chip 10 and the outer leads 5 and 6, and transfer molding is performed in this state. After the resin package 1 (see FIG. 2) is molded by, a tie bar cut is performed to complete a semiconductor device product.
【００１３】[0013]
【発明の効果】以上述べたように、本発明のリードフレ
ームにおいては、単位パターンを二列に振り分け、かつ
各列の単位パターンの向きを互いに反転させて千鳥状に
配列し、しかも各列の単位パターンのアウタリードが反
対方向から互い違いに入り組むように並べて形成したこ
とにより、従来のリードフレームと比べて、特にアウタ
リードの相互間に残る空白部分の発生割合が少なく、こ
れにより材料の利用効率が向上して製造コストの低減化
が図れる。As described above, in the lead frame of the present invention, the unit patterns are divided into two rows, and the directions of the unit patterns in each row are reversed to each other and arranged in a zigzag pattern. Compared to the conventional lead frame, the outer leads of the unit pattern are formed side by side so that they are intertwined with each other in a staggered manner.In particular, there is less blank space left between the outer leads, which improves material utilization efficiency. Therefore, the manufacturing cost can be reduced.
【００１４】また、二列に並ぶタイバーを活用して単位
パターンのアウタリードの先端を反対側列のタイバーに
連結し、さらに二列に並ぶ単位パターンのタイバー同士
を結んで隣り合う単位パターンの間に連結バーを形成し
たことにより、単位パターン間で必要な連結強度が確保
でき、従来のリードフレームにおけるサイドレールに相
当るする連結条が不要となる。Further, by utilizing the tie bars arranged in two rows, the tips of the outer leads of the unit patterns are connected to the tie bars in the opposite row, and the tie bars of the unit patterns arranged in two rows are connected to each other between the adjacent unit patterns. By forming the connecting bar, necessary connecting strength can be secured between the unit patterns, and a connecting strip corresponding to the side rail in the conventional lead frame is not necessary.
【図１】本発明の実施例によるリードフレームのパター
ン展開図FIG. 1 is a pattern development view of a lead frame according to an embodiment of the present invention.
【図２】本発明の実施対象となる樹脂封止形半導体装置
の外形図FIG. 2 is an outline view of a resin-encapsulated semiconductor device to which the present invention is applied.
【図３】従来におけるリードフレームのパターン展開図FIG. 3 is a pattern development view of a conventional lead frame.
【図４】図３のリードフレームに半導体チップをマウン
トした組立状態図4 is an assembly state diagram in which a semiconductor chip is mounted on the lead frame of FIG.
３ ダイパッド ４ アウタリード ５ アウタリード ６ アウタリード ７ タイバー ８ 連結バー 3 Die pad 4 Outer lead 5 Outer lead 6 Outer lead 7 Tie bar 8 Connecting bar
Claims (3)
導体装置の組立用リードフレームであり、ダイパッド,
ダイパッドから引出したアウタリード, 該リードと一列
に並ぶ他のアウタリード, および各リード間を連結した
タイバーを単位パターンとして形成したものにおいて、
単位パターンを二列に振り分け、かつ各列の単位パター
ンの向きを互いに反転させて千鳥状に配列し、しかも各
列の単位パターンのアウタリードが反対方向から互い違
いに入り組むように並べて形成したことを特徴とする半
導体装置用のリードフレーム。1. A lead frame for assembling a single-end type resin-sealed semiconductor device, comprising a die pad,
An outer lead drawn from the die pad, another outer lead arranged in a line with the lead, and a tie bar connecting between the leads are formed as a unit pattern.
The unit patterns are divided into two rows, and the directions of the unit patterns in each row are reversed from each other and arranged in a zigzag pattern, and the outer leads of the unit patterns in each row are arranged side by side in a staggered manner from the opposite direction. Lead frame for semiconductor devices.
単位パターンのアウタリードの先端を反対側列のタイバ
ーに連結したことを特徴とする半導体装置用のリードフ
レーム。2. The lead frame according to claim 1, wherein
A lead frame for a semiconductor device, characterized in that the tips of the outer leads of the unit pattern are connected to tie bars in the opposite row.
て、二列に並ぶ単位パターンのタイバー同士を結んで隣
り合う単位パターンの間に連結バーを形成したことを特
徴とする半導体装置用のリードフレーム。3. The lead for a semiconductor device according to claim 1, wherein the tie bars of the unit patterns arranged in two rows are connected to each other to form a connecting bar between adjacent unit patterns. flame.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP4087381A JPH05291448A (en) | 1992-04-09 | 1992-04-09 | Lead frame for semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP4087381A JPH05291448A (en) | 1992-04-09 | 1992-04-09 | Lead frame for semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH05291448A true JPH05291448A (en) | 1993-11-05 |
Family
ID=13913324
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP4087381A Pending JPH05291448A (en) | 1992-04-09 | 1992-04-09 | Lead frame for semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH05291448A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2012235011A (en) * | 2011-05-06 | 2012-11-29 | Shindengen Electric Mfg Co Ltd | Metallic mold, device manufacturing apparatus and device manufacturing method |
| CN115172320A (en) * | 2022-09-08 | 2022-10-11 | 广东气派科技有限公司 | High-density pin TO247 packaging lead frame and manufacturing method thereof |
-
1992
- 1992-04-09 JP JP4087381A patent/JPH05291448A/en active Pending
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2012235011A (en) * | 2011-05-06 | 2012-11-29 | Shindengen Electric Mfg Co Ltd | Metallic mold, device manufacturing apparatus and device manufacturing method |
| CN115172320A (en) * | 2022-09-08 | 2022-10-11 | 广东气派科技有限公司 | High-density pin TO247 packaging lead frame and manufacturing method thereof |
| CN115172320B (en) * | 2022-09-08 | 2022-12-06 | 广东气派科技有限公司 | High-density pin TO247 packaging lead frame and manufacturing method thereof |
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