JPS61194854A - Semiconductor device and manufacture thereof - Google Patents

Semiconductor device and manufacture thereof

Info

Publication number
JPS61194854A
JPS61194854A JP60034368A JP3436885A JPS61194854A JP S61194854 A JPS61194854 A JP S61194854A JP 60034368 A JP60034368 A JP 60034368A JP 3436885 A JP3436885 A JP 3436885A JP S61194854 A JPS61194854 A JP S61194854A
Authority
JP
Japan
Prior art keywords
sealing
semiconductor device
pellet
package
cap
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP60034368A
Other languages
Japanese (ja)
Inventor
Atsushi Moriya
森谷　惇
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Akita Electronics Systems Co Ltd
Original Assignee
Hitachi Ltd
Akita Electronics Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd, Akita Electronics Co Ltd filed Critical Hitachi Ltd
Priority to JP60034368A priority Critical patent/JPS61194854A/en
Publication of JPS61194854A publication Critical patent/JPS61194854A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/02—Containers; Seals
    • H01L23/10—Containers; Seals characterised by the material or arrangement of seals between parts, e.g. between cap and base of the container or between leads and walls of the container
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/161—Cap
    • H01L2924/1615—Shape
    • H01L2924/16152—Cap comprising a cavity for hosting the device, e.g. U-shaped cap
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/161—Cap
    • H01L2924/1615—Shape
    • H01L2924/16152—Cap comprising a cavity for hosting the device, e.g. U-shaped cap
    • H01L2924/1617—Cavity coating

Abstract

PURPOSE:To avoid short circuit between leads or between electrodes caused by free movement of fine foreign substances by a method wherein an internal surface of a cavity of a package is coated with a material substantially same as a sealing material when a pellet is airtightly sealed. CONSTITUTION:An internal bottom surface 11a of a cap 11 is coated with low melting point glass 12 which is the same material as a sealing material by a method such as coating. The cap 11 and a substrate 2 are put into a sealing furnace while being placed on a jig. At that time, fine foreign substances 13 adhering to the surface of the pellet fall onto the glass 12 applied on the bottom surface 11a. After heating, the substrate 2 and the cap 11 are taken out of the sealing furnace and cooled. The melted glass 12 is solidified and the airtight sealing of the inside of the package is achieved. With this constitution, short circuit between leads 6 or between electrodes caused by free movement of the foreign substances 13 is avoided.

Description

【発明の詳細な説明】 〔技術分野〕 本発明はペレットを気密封止してなる半導体装置に適用
して有効な技術に関するものである。DETAILED DESCRIPTION OF THE INVENTION [Technical Field] The present invention relates to a technique that is effective when applied to a semiconductor device formed by hermetically sealing a pellet.

〔背景技術〕[Background technology]

信顛性の高い半導体装置の封止方法の一つとして気密封
止法がある。この封止方法は、たとえばサーディップ（
ＣＥＲＤＩＰ）型の半導体装置を例にして説明すると以
下のように行われる。Hermetic sealing is one of the highly reliable sealing methods for semiconductor devices. This sealing method can be used, for example, using cerdip (
Taking a CERDIP type semiconductor device as an example, the process is explained as follows.

すなわち、この半導体装置は、セラミックからなる基板
にペレットを金−シリコン共晶等で取付けた後、４２７
０イもしくはコバール等からなるリードを低融点ガラス
で基板上に固定し、リードとペレットをアルミニウム等
のワイヤで結線したのち、前記ペレットを低融点ガラス
を用いてキャンプで気密封止して製造されるものである
。That is, this semiconductor device is manufactured by attaching pellets to a substrate made of ceramic using gold-silicon eutectic or the like.
A lead made of aluminum or Kovar is fixed on a substrate using low-melting glass, the lead and the pellet are connected with a wire made of aluminum, etc., and the pellet is hermetically sealed using low-melting glass. It is something that

ところで、この種の気密封止型半導体装置は製造途中で
パッケージ内部に微小な異物が混入したまま封止される
ことがある。この異物が、輸送時等にパッケージにかか
る振動によりパッケージ内を自由に動き回り、これが原
因となってワイヤまたはパッド等の電極間のショートを
引き起こす場合があることが知られている。By the way, this type of hermetically sealed semiconductor device may be sealed with minute foreign matter mixed inside the package during manufacturing. It is known that this foreign material moves freely within the package due to vibrations applied to the package during transportation, etc., and this may cause a short circuit between electrodes such as wires or pads.

そのため、気密封止型半導体装置では製品完成後にパッ
ケージ内の可動異物混入を検査する工程が必要であった
。Therefore, hermetically sealed semiconductor devices require a step of inspecting the package for movable foreign matter after the product is completed.

この点につき、キャンプの取付は前に圧搾空気をパンケ
ージのキャビティに吹き付けて異物を除去するスクリー
ニング工程を付加することが考えられる。In this regard, it is conceivable to add a screening process to remove foreign substances by blowing compressed air into the cavity of the pan cage before installing the camp.

しかし、前記方法によっては強く付着している異物は完
全に取り除くことができないのみならず、圧搾空気の吹
き付けの際の風圧によりワイヤ間のショートが起こる場
合のあることが本発明者によって明らかにされた。However, the present inventor has revealed that not only is it not possible to completely remove strongly adhered foreign substances depending on the method described above, but also that short circuits may occur between the wires due to the wind pressure when compressed air is blown. Ta.

なお、異物除去のための半導体装置の製造工程における
スクリーニング技術について記載されている例として、
昭和５７年１１月１５日、株式会社工業調査会発行「電
子材料」１１月号別冊、Ｐｌｏｏ−Ｐ２Ｏ３がある。In addition, as an example of a screening technology in the manufacturing process of semiconductor devices for removing foreign substances,
On November 15, 1980, there is a separate issue of the November issue of "Electronic Materials" published by Kogyo Research Association Co., Ltd., Ploo-P2O3.

［発明の目的］ 本発明の目的は、気密封止型半導体装置のキャビティ内
の微小異物の自由移動が原因となるリード間または電極
間のショート等を防止して信頼性本発明の前記ならびに
その他の目的と新規な特徴は、本明細書の記述および添
付図面から明らかになるであろう。[Object of the Invention] An object of the present invention is to prevent short-circuits between leads or electrodes caused by the free movement of minute foreign matter within the cavity of a hermetically sealed semiconductor device, thereby improving the reliability of the above and other aspects of the present invention. The objects and novel features of the invention will become apparent from the description of this specification and the accompanying drawings.

［発明の概要］ 本願において開示される発明のうち代表的なものの概要
を簡単に説明すれば、次の通りである。[Summary of the Invention] A brief overview of typical inventions disclosed in this application is as follows.

すなわち、ペレットを気密封止する際に、パッケージの
キャビティ内面に封止材と実質的に同じ材料からなる物
質を被着することにより、封止の際に微小異物が固定さ
れるため、該微小異物の自由移動によるリードまたは電
極間のショート等を防止することができる。That is, when the pellet is hermetically sealed, a substance made of substantially the same material as the sealing material is applied to the inner surface of the cavity of the package, thereby fixing the minute foreign matter during sealing. Short circuits between leads or electrodes due to free movement of foreign matter can be prevented.

［実施例］ 第１図および第２図は本発明の一実施例である半導体装
置の製造方法を断面図で１順次示したものである。[Embodiment] FIGS. 1 and 2 are sectional views sequentially showing a method for manufacturing a semiconductor device according to an embodiment of the present invention.

本実施例の半導体装置１はいわゆるサーディツプ型の半
導体装置である。以下この半導体装置の製造方法につい
て順次説明する。The semiconductor device 1 of this embodiment is a so-called cerdip type semiconductor device. The method for manufacturing this semiconductor device will be sequentially explained below.

まず、アルミナからなる基板２に形成された凹部３にペ
レット４を金もしくは銀のペースト５で取付けた後、該
基板２の表面のペレット４の周囲に４２７０イからなる
リード６を低融点ガラス７で取付ける。First, a pellet 4 is attached to a recess 3 formed in a substrate 2 made of alumina using gold or silver paste 5, and then a lead 6 made of 4270 mm is attached to a low melting point glass 7 around the pellet 4 on the surface of the substrate 2. Install it with

次に、ペレット４上に設けられたアルミニウムからなる
バッド８と前記リード６のペレット側光０ｆｉｌとをア
ルミニウム等のワイヤ９でボンディングしペレット４と
リード６間の電気的導通を達成する。Next, a pad 8 made of aluminum provided on the pellet 4 and the pellet side light 0fil of the lead 6 are bonded with a wire 9 made of aluminum or the like to achieve electrical continuity between the pellet 4 and the lead 6.

次に、図示しない治具上に、袖部１０を有する断面コ字
状のキャンプ１１を開口部を上にして載置し、封止代で
ある袖部１０の端面ｔＯａおよびキャップ１１の内側の
底面１１ａに封止材と同じ材質の低融点ガラス１２を塗
布、ボッティング等の方法で被着する（第１図）。Next, the camp 11 having a U-shaped cross section and having the sleeve portion 10 is placed on a jig (not shown) with the opening facing upward. A low-melting glass 12 made of the same material as the sealant is applied to the bottom surface 11a by a method such as coating or botting (FIG. 1).

さらに、治具上のキャップ１１の上に前記のペレット４
およびリード６の取付が完了した基板２をベレット取付
は面側を下にしてキャップ１１のその後、上記キャンプ
１１及び基板２を治具上に！１２置したままの状態で封
止炉（図示せず）に入れる。このとき、封止炉に移送す
る際にパッケージにかかる振動もしくは封止炉の加熱に
より、基板２またはペレット表面に付着した微小異物１
３はキャップ１１の内側の底面１１ａ上に塗布された低
融点ガラス１２の上に落ちて（る。Further, the pellet 4 is placed on the cap 11 on the jig.
Then, attach the board 2 with the lead 6 attached with a pellet with the surface side facing down, then attach the cap 11, and then place the camp 11 and the board 2 on the jig! 12 Place it in a sealing furnace (not shown) while keeping it there. At this time, minute foreign matter 1 attached to the substrate 2 or the pellet surface due to the vibration applied to the package or the heating of the sealing furnace during transfer to the sealing furnace.
3 falls onto the low melting point glass 12 coated on the inner bottom surface 11a of the cap 11.

さらに加熱した後、これら基板２とキャップ１１を封止
炉から取り出し、常温で冷却することにより、溶融した
低融点ガラス１２が固化し、基板２とキャンプ１１の袖
部１０の端面１０ａとが密着する状態となり、パッケー
ジ内部の気密封止が達成される。After further heating, the substrate 2 and cap 11 are taken out of the sealing furnace and cooled at room temperature, whereby the molten low melting point glass 12 solidifies, and the substrate 2 and the end surface 10a of the sleeve portion 10 of the camp 11 are brought into close contact with each other. The inside of the package is hermetically sealed.

一方、キャンプ１１の内側に落下した微小異物１３はキ
ャンプ１１の内側の低融点ガラス１２の溶融・固化にと
もないキャップ内面１１ａに固定され、不動状態となる
（第２図）。On the other hand, as the low melting point glass 12 inside the camp 11 melts and solidifies, the minute foreign matter 13 that has fallen inside the camp 11 is fixed to the cap inner surface 11a and becomes immobile (FIG. 2).

最後にパッケージ外部に突出した部分のり一ド６を一本
ずつ切断成形して独立した状態にするこ上記のように本
実施例によれば、封止の際にキャップ１１の封止代であ
る袖部端面１０ａのほかにキャンプ内側の底面１１ａに
わ封止材でアル低融点ガラス１２を被着しておくことに
より、封止の際に落下してくる微小異物１３を固定でき
るため、製品完成後に該異物１３が原因となって生じる
ワイヤのショートもしくは電極間ショートを防止するこ
とができる。Finally, according to this embodiment, the parts of the glue 6 that protrude outside the package are cut and molded one by one to make them independent.As described above, according to this embodiment, the sealing margin of the cap 11 is In addition to the end surface 10a of the sleeve part, by covering the bottom surface 11a inside the camp with Al low melting point glass 12 using a sealing material, it is possible to fix the minute foreign matter 13 that falls during sealing, thereby making it possible to secure the product. It is possible to prevent wire shorts or shorts between electrodes caused by the foreign matter 13 after completion.

また、本実施例によれば、キャップ１１の内面１１ａに
低融点ガラス１２を被着するという僅かな工程を付加す
るのみでワイヤ９またはパッド８間のショートを防止で
きる信頼性の高い半導体装置を提供することができる。Furthermore, according to this embodiment, a highly reliable semiconductor device can be produced in which short circuits between wires 9 or pads 8 can be prevented by adding a small step of coating low melting point glass 12 on inner surface 11a of cap 11. can be provided.

［効果］ （ｌ）、ペレットを気密封止してなる半導体装置のパッ
ケージのキャビティ内面に封止材を被着して加熱封止す
ることにより、封止の際に微小異物が固定されるため、
該微小異物の自由移動によるリードまたは電極間のショ
ートを防止することができる。[Effect] (l) By applying a sealing material to the inner surface of the cavity of a semiconductor device package made by hermetically sealing a pellet and sealing with heat, minute foreign matter is fixed during sealing. ,
Short circuits between leads or electrodes due to free movement of the minute foreign matter can be prevented.

（２）、ペレットを気密封止してなる半導体装置の製造
の際に、パッケージ基板にペレットを取付け、電極間結
線を行った後、封止代およびパンケージ内面に封止材を
被着して加熱する製造工程とすることにより、わずかな
封止材の被着工程の付加のみで信頼性の高い半導体装置
を提供することができる。異物固定材としての低融点ガ
ラス体ｉｔａは、封止材１２と実質的に同じ軟化点を持
ち、パンケージの封止温度において確実に軟化する。そ
れ故に、異物は良好に固定される。(2) When manufacturing a semiconductor device made by hermetically sealing a pellet, after attaching the pellet to a package substrate and making connections between electrodes, a sealing material is applied to the sealing margin and the inner surface of the pan cage. By employing a manufacturing process that involves heating, a highly reliable semiconductor device can be provided with only a slight addition of a sealing material deposition process. The low melting point glass body ita as the foreign matter fixing material has substantially the same softening point as the sealing material 12, and is reliably softened at the sealing temperature of the pan cage. Therefore, foreign objects are well fixed.

（３）、前記（１）および（２）より可動異物の混入テ
スト工程を省略することができ、気密封止型の半導体装
置の製造効率を向上させることができる。(3) According to (1) and (2) above, the step of testing the presence of movable foreign objects can be omitted, and the manufacturing efficiency of hermetically sealed semiconductor devices can be improved.

以上本発明者によってなされた発明を実施例に基づき具
体的に説明したが、本発明は前記実施例に限定されるも
のではなく、その要旨を逸脱しない範囲で種々変更可能
であることはいうまでもない。Although the invention made by the present inventor has been specifically explained above based on Examples, it goes without saying that the present invention is not limited to the Examples and can be modified in various ways without departing from the gist thereof. Nor.

たとえば、実施例では封止材として低融点ガラスを用い
た場合についてのみ説明したが、これに限られるもので
はなく、他の封止材であってもよい。For example, in the embodiment, only the case where low melting point glass is used as the sealing material has been described, but the present invention is not limited to this, and other sealing materials may be used.

さらに、基板、キャップ、リード等の部材の材質につい
ても実施例に記載されたものに限定されない。Furthermore, the materials of members such as the substrate, cap, and leads are not limited to those described in the embodiments.

［利用分野］ 以上の説明では主として本発明者によってなされた発明
をその背景となった利用分野である、いわゆるサーディ
ンプ型の半導体装置に適用した場合について説明したが
、これに限定されるものではなく、たとえばチップキャ
リア型等のパッケージ形状のものであってもパッケージ
内部を気密封止してなる半導体装置であればこれらに適
用して信頼性の高い半導体装置を得ることができる。[Field of Application] In the above explanation, the invention made by the present inventor was mainly applied to a so-called sardimp-type semiconductor device, which is the field of application that formed the background of the invention, but the present invention is not limited to this. For example, even if the semiconductor device is in a package shape such as a chip carrier type, as long as the inside of the package is hermetically sealed, the present invention can be applied to these devices to obtain a highly reliable semiconductor device.

【図面の簡単な説明】 第１図および第２図は本発明の一実施例である半導体装
置の製造方法を順次示す断面図である。 １・・・半導体装置、２・・・基板、３・・・凹部、４
・・・ペレット、５・・・ペースト、６、、、ｌｌ−Ｌ
ｊ　　７．、、都ｎ−占ゼ石フ　ｑｏ、。 パッド、９・・・ワイヤ、１０・・・油部、１０ａ・・
・袖部端面、１１・・・キャップ、ｌｌａ・・・キャン
プ内側底面、１２・・・低融点ガラス。BRIEF DESCRIPTION OF THE DRAWINGS FIGS. 1 and 2 are cross-sectional views sequentially showing a method for manufacturing a semiconductor device according to an embodiment of the present invention. DESCRIPTION OF SYMBOLS 1... Semiconductor device, 2... Substrate, 3... Recessed part, 4
...Pellet, 5...Paste, 6,...ll-L
j7. ,, capital n-zanzekifu qo,. Pad, 9...Wire, 10...Oil part, 10a...
- Sleeve end surface, 11... Cap, lla... Camp inner bottom surface, 12... Low melting point glass.

Claims (1)

【特許請求の範囲】 １、ペレットを気密封止してなる半導体装置であって、
パッケージのキャビティ内面に封止材と実質的に同じ材
料からなる物質を被着したことを特徴とする半導体装置
。 ２、上記物質が低融点ガラスからなることを特徴とする
特許請求の範囲第１項記載の半導体装置。 ３、ペレットを気密封止してなる半導体装置の製造方法
であって、パッケージ基板にペレットを取付け、電極間
結線を行った後、封止代部分およびパッケージ内面に封
止材を被着して加熱溶融する半導体装置の製造方法であ
って、上記ペレットの主面が下方に位置する状態をもっ
て上記封止材を加熱溶融させることを特徴とする半導体
装置の製造方法。[Claims] 1. A semiconductor device formed by hermetically sealing a pellet,
A semiconductor device characterized in that a substance made of substantially the same material as a sealing material is coated on the inner surface of a cavity of a package. 2. The semiconductor device according to claim 1, wherein the substance is made of low melting point glass. 3. A method for manufacturing a semiconductor device by hermetically sealing a pellet, which includes: attaching the pellet to a package substrate, connecting the electrodes, and then applying a sealing material to the sealing margin and the inner surface of the package. 1. A method for manufacturing a semiconductor device that is heated and melted, the method comprising heating and melting the sealing material with the main surface of the pellet facing downward.
JP60034368A 1985-02-25 1985-02-25 Semiconductor device and manufacture thereof Pending JPS61194854A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP60034368A JPS61194854A (en) 1985-02-25 1985-02-25 Semiconductor device and manufacture thereof

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP60034368A JPS61194854A (en) 1985-02-25 1985-02-25 Semiconductor device and manufacture thereof

Publications (1)

Publication Number Publication Date
JPS61194854A true JPS61194854A (en) 1986-08-29

Family

ID=12412227

Family Applications (1)

Application Number Title Priority Date Filing Date
JP60034368A Pending JPS61194854A (en) 1985-02-25 1985-02-25 Semiconductor device and manufacture thereof

Country Status (1)

Country Link
JP (1) JPS61194854A (en)

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