JPS61192354U - - Google Patents
Info
- Publication number
- JPS61192354U JPS61192354U JP7435885U JP7435885U JPS61192354U JP S61192354 U JPS61192354 U JP S61192354U JP 7435885 U JP7435885 U JP 7435885U JP 7435885 U JP7435885 U JP 7435885U JP S61192354 U JPS61192354 U JP S61192354U
- Authority
- JP
- Japan
- Prior art keywords
- signal
- bus line
- address
- latch circuit
- microcomputer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000010586 diagram Methods 0.000 description 2
Landscapes
- Bus Control (AREA)
- Information Transfer Systems (AREA)
Description
第１図は本考案のバスライン信号ラツチ回路の
一実施例を示すブロツク系統図、第２図は第１図
の実施例を説明するためのタイムチヤート、第３
図は従来のバスライン信号ラツチ回路のブロツク
系統図、第４図は第１図および第３図の動作説明
用のタイムチヤートである。
１……反転回路、２……トリガラツチ回路、２
８……アドレスデコーダ、Ａ，Ｂ，Ｃ，Ｄ，Ｇ，
Ｏ……端子。
FIG. 1 is a block system diagram showing one embodiment of the bus line signal latch circuit of the present invention, FIG. 2 is a time chart for explaining the embodiment of FIG. 1, and FIG.
The figure is a block system diagram of a conventional bus line signal latch circuit, and FIG. 4 is a time chart for explaining the operations of FIGS. 1 and 3. 1... Inverting circuit, 2... Trigger lock circuit, 2
8...Address decoder, A, B, C, D, G,
O...Terminal.
Claims (1)
信号とをＣＰＵからの制御信号により時分割し、
ポートおよびバスラインを共通に用いるマイクロ
コンピユータの前記バスラインより供給される時
分割されたアドレス信号をラツチして、アドレス
デコーダに供給するバスライン信号ラツチ回路に
おいて、前記制御信号の正負を反転する反転回路
と、この反転回路の出力信号がローレベルからハ
イレベルに変化するエツジによつて前記ポートお
よびバスラインを介して出力される前記アドレス
信号をラツチするトリガラツチ回路とを有し、こ
のトリガラツチ回路の出力信号を前記アドレスデ
コーダに供給するようにしたことを特徴とするバ
スライン信号ラツチ回路。 The address signal and data signal of the microcomputer are time-divided by the control signal from the CPU,
In a bus line signal latch circuit that latches a time-divided address signal supplied from the bus line of a microcomputer that uses a port and a bus line in common, and supplies it to an address decoder, an inverting circuit that inverts the polarity of the control signal is used. and a trigger latch circuit for latching the address signal outputted through the port and the bus line by an edge at which the output signal of the inverting circuit changes from a low level to a high level. A bus line signal latch circuit, characterized in that the output signal is supplied to the address decoder.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP7435885U JPS61192354U (en) | 1985-05-20 | 1985-05-20 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP7435885U JPS61192354U (en) | 1985-05-20 | 1985-05-20 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS61192354U true JPS61192354U (en) | 1986-11-29 |
Family
ID=30614582
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP7435885U Pending JPS61192354U (en) | 1985-05-20 | 1985-05-20 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS61192354U (en) |
-
1985
- 1985-05-20 JP JP7435885U patent/JPS61192354U/ja active Pending
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