JPH01139633U - - Google Patents
Info
- Publication number
- JPH01139633U JPH01139633U JP3540288U JP3540288U JPH01139633U JP H01139633 U JPH01139633 U JP H01139633U JP 3540288 U JP3540288 U JP 3540288U JP 3540288 U JP3540288 U JP 3540288U JP H01139633 U JPH01139633 U JP H01139633U
- Authority
- JP
- Japan
- Prior art keywords
- address
- circuit
- signal
- outputs
- comparator
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000010586 diagram Methods 0.000 description 4
Landscapes
- Compression, Expansion, Code Conversion, And Decoders (AREA)
Description
第１図は本考案の一実施例を示す回路図、第２
図は第１図に示すアドレスデコード回路の一使用
例を示すブロツク図、第３図ａ，ｂは従来の一例
を示す回路図である。
１……アドレス設定器、２……ラツチ回路、３
……コンパレータ、４……論理積回路。
Figure 1 is a circuit diagram showing one embodiment of the present invention, Figure 2 is a circuit diagram showing an embodiment of the present invention.
This figure is a block diagram showing an example of the use of the address decoding circuit shown in FIG. 1, and FIGS. 3a and 3b are circuit diagrams showing an example of the conventional address decoding circuit. 1...Address setter, 2...Latch circuit, 3
...Comparator, 4...Logic product circuit.
Claims (1)
定器、 (B) ＣＰＵのデータバスを入力し、第１のアド
レス信号により前記データバスの内容を保持する
ラツチ回路、 (C) 前記アドレス設定器の出力と前記ラツチ回
路の出力とを比較し、値が等しい間コンパレータ
信号を出力するコンパレータ、 (D) 前記コンパレータ信号と、第２のアドレス
信号にもとずいてチツプセレクト信号を出力する
論理積回路、 とを含むことを特徴とするアドレスデコード回
路。[Scope of Claim for Utility Model Registration] (A) An address setter that sets a reference address; (B) A latch circuit that inputs a data bus of a CPU and holds the contents of the data bus by a first address signal; (C) a comparator that compares the output of the address setter and the output of the latch circuit and outputs a comparator signal while the values are equal; An address decoding circuit comprising: an AND circuit that outputs a select signal;
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP3540288U JPH01139633U (en) | 1988-03-16 | 1988-03-16 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP3540288U JPH01139633U (en) | 1988-03-16 | 1988-03-16 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH01139633U true JPH01139633U (en) | 1989-09-25 |
Family
ID=31262050
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP3540288U Pending JPH01139633U (en) | 1988-03-16 | 1988-03-16 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH01139633U (en) |
-
1988
- 1988-03-16 JP JP3540288U patent/JPH01139633U/ja active Pending
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