JPS61189639U - - Google Patents

Info

Publication number
JPS61189639U
JPS61189639U JP7382885U JP7382885U JPS61189639U JP S61189639 U JPS61189639 U JP S61189639U JP 7382885 U JP7382885 U JP 7382885U JP 7382885 U JP7382885 U JP 7382885U JP S61189639 U JPS61189639 U JP S61189639U
Authority
JP
Japan
Prior art keywords
output
input
circuit
circuits
signal
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP7382885U
Other languages
Japanese (ja)
Other versions
JPH042511Y2 (en
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP7382885U priority Critical patent/JPH042511Y2/ja
Publication of JPS61189639U publication Critical patent/JPS61189639U/ja
Application granted granted Critical
Publication of JPH042511Y2 publication Critical patent/JPH042511Y2/ja
Expired legal-status Critical Current

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  • Circuits Of Receivers In General (AREA)

Description

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は、本考案による現用1系統、予備1系
統の高周波回路系(受信機)の第1の実施例の構
成を示すブロツク図、第2図は第1図の構成の入
力回路の具体的な回路図、第3図は本考案による
現用1系統、予備1系統の高周波回路系(高出力
増幅器)の第2実施例の構成を示すブロツク図、
第4図は従来の現用1系統、予備1系統の高周波
回路系(受信機)で切替回路が入力側に設けられ
ている例を示すブロツク図、第5図は従来の現用
1系統、予備1系統の高周波回路系(高出力増幅
器)で切替回路が出力側に設けられている例を示
すブロツク図である。 1,2……高周波回路(受信機)、9,10…
…高周波回路(高出力増幅器)、5……低雑音増
幅器、6……周波数変換器、7……中間周波増幅
器、3,4,12……ハイブリツド、8,11…
…SPDT切替回路、13,14,15,16…
…伝送線路、19,20,25,26……トラン
ジスタ、17,18……入力整合回路、21,2
2……スイツチ、23,24……出力整合回路、
CMD1,CMD2,CMD3……外部制御信号
、VD……トランジスタ電源。
FIG. 1 is a block diagram showing the configuration of a first embodiment of a high-frequency circuit system (receiver) with one active system and one backup system according to the present invention, and FIG. 2 shows a specific example of the input circuit having the configuration shown in FIG. FIG. 3 is a block diagram showing the configuration of a second embodiment of a high-frequency circuit system (high-output amplifier) with one active system and one standby system according to the present invention,
Figure 4 is a block diagram showing an example of a conventional high-frequency circuit system (receiver) with one working system and one standby system in which a switching circuit is provided on the input side. FIG. 2 is a block diagram showing an example in which a switching circuit is provided on the output side of a high frequency circuit system (high output amplifier) of the system. 1, 2...High frequency circuit (receiver), 9, 10...
...High frequency circuit (high output amplifier), 5...Low noise amplifier, 6...Frequency converter, 7...Intermediate frequency amplifier, 3, 4, 12...Hybrid, 8, 11...
...SPDT switching circuit, 13, 14, 15, 16...
...Transmission line, 19,20,25,26...Transistor, 17,18...Input matching circuit, 21,2
2...Switch, 23, 24...Output matching circuit,
CMD1, CMD2, CMD3...External control signal, VD...Transistor power supply.

Claims (1)

【実用新案登録請求の範囲】[Scope of utility model registration request] 入力側に外部からの制御によりその入力インピ
ーダンスが開放状態になり且つ信号の通過が遮断
される入力回路を有するか、又は出力側に外部か
らの制御により出力信号が遮断され且つその出力
インピーダンスが開放状態となる出力回路を有す
るか、又は前記入力回路と前記出力回路の両者を
共に有する複数の同種の高周波回路の前記各入力
回路の入力端および/又は前記各出力回路の出力
端がそれぞれほぼ2分の1波長の整数倍の電気長
を有する伝送線路を介して前記各入力端は共通の
信号入力端へ、また、前記各出力端は共通の信号
出力端へ結合されていることを特徴とする高周波
回路系。
Either the input side has an input circuit whose input impedance is set to an open state and signal passage is blocked by external control, or the output side has an input circuit whose output signal is cut off and its output impedance is opened by external control. The input end of each of the input circuits and/or the output end of each of the output circuits of a plurality of high frequency circuits of the same type have an output circuit that becomes a state, or have both the input circuit and the output circuit, respectively. Each of the input terminals is coupled to a common signal input terminal, and each of the output terminals is coupled to a common signal output terminal via a transmission line having an electrical length that is an integral multiple of a wavelength. High frequency circuit system.
JP7382885U 1985-05-18 1985-05-18 Expired JPH042511Y2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP7382885U JPH042511Y2 (en) 1985-05-18 1985-05-18

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP7382885U JPH042511Y2 (en) 1985-05-18 1985-05-18

Publications (2)

Publication Number Publication Date
JPS61189639U true JPS61189639U (en) 1986-11-26
JPH042511Y2 JPH042511Y2 (en) 1992-01-28

Family

ID=30613554

Family Applications (1)

Application Number Title Priority Date Filing Date
JP7382885U Expired JPH042511Y2 (en) 1985-05-18 1985-05-18

Country Status (1)

Country Link
JP (1) JPH042511Y2 (en)

Also Published As

Publication number Publication date
JPH042511Y2 (en) 1992-01-28

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